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A new IFFT/FFT hardware implementation structure for OFDM applications

Conference Paper · January 2005

DOI: 10.1109/APCCAS.2004.1413074 · Source: IEEE Xplore

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A NEW IFFT/FFT HARDWARE IMPLEMENTATION STRUCTURE FOR
OFDM APPLICATIONS
Shung-Chih Chen Chao-Tang Yu Chia-Lian Tsai
scchen@mail.stut.edu.tw ctyu@mail.stut.edu.tw m9030221@y&oo.com.~ jjtang@cadl.eecs.stut.edu.tw
Department of Electronic Engineering, Southem Taiwan University of Technology
ABSTRACT
In OFDM applications, IFFTFFT hardware in the trans-
ceiver is usually designed jointly to carry out IFFT and
FFT functions for transmission and receiving processes,
respectively. In this paper, we present a new IFFT/FFT
hardware implementation structure with less complexity
for OFDM applications. The proposed method can be ap-
plied to existing various FFT algorithms while implement-
ing the OFDM. The 64point IFFT/FFT chips for the
Radix-4/2 and Radix-Z14/8 algorithms based on the pro-
posed scheme are implemented by using TSMC .35jm,
TSMC 2 S p m and UMC . I 8 p CMOS technologies. The
implementation results show that our method can achieve a
less complexity and area-efficiency IFFTFFT processor.
1. INTRODUCTION
Recently, the demands for high speed of multimedia
transmission in wired/wireless communication systems
have increased enormously [I]. In order to speed up
transmission data rate in a given finite bandwidth, many
different technologies have been developed in these sys-
t e m , such as W A N (IEEE 802.11dg), digital audio
broadcasting (DAB) and asymmetric digital subscribe line
(ADSL). The most popular one of the technologies is the
orthogonal frequency division multiplexing (OFDM), and
it has been widely used in the above systems [2]. In es-
sence, the OFDM can be viewed as in frequency domain
where data is canied by different sub-canier frequencies.
The OFDM implementation is only feasible by utilizing a
real-time FFT processor to replace the bank of
(de)modulator for individual sub-carriers. The FFTiIFFT
algorithms considered here are mainly for the OFDM ap-
plications.
In OFDM applications, a jointly designed IFFTFFT hard-
ware in the transceiver is used to cany out IFFT and FFT
functions for transmission and receiving processes, respec-
tively. In general, IFFT/FFT processor will be designed to
use a common hardware to perform IFFT or FFT functions
in a time, where which function should be carried out is
controlled by a selection signal. Due to the similarity of
mathematical computation for IFFT or FFT processing,
conventionally, the common hardware design is mainly
focused on FFT calculation and many FFT algorithms
0-7803-8660-4104R20.00 02004 IEEE
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The 2004 IEEE Asia-Pacific Conference on
Circuits and Systems, December 6-9,2004
Jing-Jou Tang
have been developed in the literature. Therefore, based on
various FFT algorithms, the IFFTFFT core hardware is
implemented. Meanwhile, by adding a coefficient table or
switching circuits, the implemented IFFTFFT processor
can cany out IFFT and FFT functions through a control
signal. One example is shown as Fig. 1 w h e r e S E F T is
the control signal that can control this core to perform FFT
or IFFT functions [3-71. As we know, the IFFT/FFT com-
putation results need to be buffered at the output stage for
OFDM applications. By examining the mathematical com-
putations of IDFT(1nverse discrete Fourier Transform) and
DFT(Discrete Fourier Transform), we notice that IFFT
function can be implemented by a FFT processor with
designed output buffers. Considering the hardware com-
plexity and the implementation chip area, we propose a
novel IFFTFFT hardware implementation structure for
OFDM applications. In our method, the common computa-
tion core is based on a FFT algorithm, and the output
buffer is designed so that the IFFTFFT functions can be
performed by only switching the output buffers. The block
diagram shown in Fig. 2 explains this proposed scheme.
-
IFFTIFFT
", I
I
-
lPPTIFFT
Fig. 1 A general IFFTFFT sUuchxe for OFDM implementations.
!! !I
IFFTEFT
IFFTIFFT
Fig. 2 The proposed IFFTiFFT structure for OFDM implementa-
tions.
In Section 2, we will examine the IDFT and DFT mathe-
matical computations and present a new IFFTBFT hard-
ware structure with less complexity for OFDM implemen-
1093
 tations. I n Section 3, the proposed method will be applied
to existing various FFT algorithms, namely, the Radix-412
and Radix-21418 algorithms while implementing the
OFDM by using TSMC .3Spm, TSMC . 2 5 p and
UMC , l S p CMOS technologies. For the purpose of
comparison, the conventional IFFTEFT hardware struc-
tures [3, 41 are also implemented by the same technologies.
Finally, some concluding remarks are made in Section 4.

2. IFFT/FFT HARDWARE STRUCTURE DESIGN

The N-point DFT and IDFT are defined as

N-l
Comparing Eqs (3.1)-(3.4) and Eqs (4.1)-(4.4), we can
DFT: X ( k ) = c x ( n ) o : , OikSN-l (1) have the following relationships:
"-0
1 I I
flO)=NY(Q, HI)=- Y(N-l), AZ)=-Y(N-Z)
N N
...flN-l)=-Y(l)
1
N

Observing the above relationships, we may conclude that

where the coefficient the IDFT function can be implemented by a FFT processor
where only reordering and scaling operations on the FFT
output are added. A MATLAB numerical example shown
in Fig. 3 is used to verify this idea. Therefore, we propose
is called a twiddle factor. Let x(n), n = 0, 1, _.., N-1 be the a new IFFTRFT hardware implementation structure for
input data of a DFT processor. By using Eq. (I), we have OFDM applications by redesigning the output buffering
the output data denoted as Y(k), k = 0, 1, .._,N-l which strategy based on the above relationships. In this way, only
are expressed as follows: a common FFT computation core hardware is used. Figs. 4
and 5 show an example of the hardware of w," multiplier
(3.1) for FFT and IFFTRFT, respectively. Obviously, our im-
plementation structure can reduce the complexity of
IFFTiFFT hardware and the implementation chip area.

I
N-l
Y(2)= y
, x(n)o;' (3.3)
n=o

Again, the same data x is fed into an IDFT processor. By m

employing Eq. (2), we can have the output data expressed o , o D a ( o l o Q
(a) Input sequencex(n) (b) 64-point FFT output
as Eqs. (4.1)-(4.4). Note that the term, W," = I , is multi-
plied to the twiddle factor on purpose while doing the cal-
culation, but this operation won't change the IDFT compu-
tation results.

a z o
(c) Reordered and scaled
U m 02b to ? w (o n
(d) 64-point IFFT output
m A
64-point FFT output
Fig. 3 MATLAB numerical example

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Fig. 4 The hardware of W," multiplier for FFT.
- tables. From the tables, we can see that the IFFTPFT chip
,FFT/FF-r-
Fig. 5 The hardware of W," multiplier for IFFTEFT [3,4]
3. IFFT/FFT IMPLEMENTATIONS
The proposed structure can be integrated with existing
various FFT algorithms to implement a OFDM chip. For
the purpose of comparison, in this section, several 64-point
IFFT/FFT chips are carried out by using existing various
FFT algorithms, namely, Radix-4/2 [4] and Radix-2/4/8 [SI
algorithms with different pipeline structures. Here, the
SDF (single-delay feedback) pipeline architecture using
delay feedback buffering strategy and the MDC (multiple-
delay commutator) pipeline architechwe using delay com-
mutator buffering strategy are considered in the implemen-
presented in Table 2 and Table 3, respectively. In the ta-
bles, a P W , ~ l2; p, 4 , 5, 6 represents the CMOS tech-
nologies with a layers of ploy and ,b layers of metal, re-
spectively. The chip area is expressed in terms of gate
count or layout area. The processing speed is represented
by the shortest processing cycle of IFFT/FFT processor.
Due to a common FFT hardware is used in our approach,
the complexity of hardware structure can be reduced. And
this can result in the chip area reduction, which can be
verified by the chip implementation results listed in the
area implemented with our hardware structure is smaller
than that of [3-71. The processing speed also can be im-
proved. slightly in all cases.
Table I The implementation results for using the radix-U4/8
FFT algorithm with the SDF pipeline architecture.
I I Radix-2/4/8 FFT Alaorithm I
Conventional struc-
Proposed structure
Technology
. 3 5 p TSMC
lP4M
24195
(Gate count) I 23173 115.54 ns
"'l(Gate count)

tation [9-10]. One example of the radix-4/2 FFT algorithm

with SDF pipeline architectures based on our proposed
technique is presented in Fig. 6.By using TSMC .35pm,
TSMC .25pm and UMC .18pm CMOS technologies, the
IFFTPFT chips are implemented with two structures. One
is the conventional structure [3-41 shown in Fig. 1, the
other is the proposed structure. The multiplier area reduc- Table 2 The implementation results for using radix-4R FFT
tion technique developed in [3] is also used in all cases. algorithm with SDF pipeline architecture.
Fig. 7 presents a layout of 64-point IFFTFFT for radix-
2/4/8 with SDF pipeline architecture based on ow scheme
where TSMC .35pm CMOS technology is used.
~~ ~~
-
I F F T E F T I

.w ~ W I t

Fig. 6 The radix-4/2 FFT algorithm with SDF pipeline architec-

tures based on the proposed technique

The implementation results using the radix-2/4/8 FFT al-

gorithm with the SDF pipeline architecture are shown in
Table 1. The implementation results using radix-4/2 FFT
algorithm with SDF and MDC pipeline architectures are

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 Table 3 The implementation results for using radix-412 FFT
algorithm with MDC pipeline architecture.
I I Algorithm Radix-4/2
Process Conventional struc-
Proposed structure
Technology
1.35z2:MC12.379 Mum2 124.39 nsl2.279 M~m~123.36
ns I theuse of multiplier area reduction technique in
I.25cfn:MC/722.2 Kum2 118.57 ns1689.4Kum2 117.11 ns I
4. CONCLUSIONS
By examining the mathematical computation of IDFT and
DFT, we show that IFFT can be implemented by a FFT
processor with designed output buffers. Considering the
hardware complexity and the implementation chip area, we
present a new IFFTiFFT hardware implementation struc-
ture for OFDM applications. In our method, a common
FFT core is used with a designed output buffering strategy
so that the IFFTiFFT functions can be performed on selec-
tion. The proposed method can be applied to existing vari-
ous FFT algorithms while implementing the OFDM. The
64-point IFFT/FFT chips for the Radix-4/2 and Radix-
2/4/8 algorithms based on the proposed scheme are im-
plemented by using TSMC . 3 5 p n , TSMC .25,1im and
UMC . I 8 p CMOS technologies. The implementation
hardware results show that our method can achieve a less
complexity and area-efficiency IFFTRFT processor.
Fig. 7 A layout of 64-point IFFTiFFT for radix-2/4/8algorithm
with SDF pipeline architecture.
1096
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