PROJECT REPORT Project Title: RTL Modeling of a Dual-Clock Asynchronous FIFOTable of Contents EM CHUN 2. YRU CAU THIET KE.. 3.1 Ci trie FIFO 3.1.1. Dusl-port memory..... 3.1.2. Control Unit... 4. VHDL CODE. 4.1. Bin m6 ta FIFO. 7 42. Dual port memory 43. Miy tao dia chi R 5. KIEM CHUN SL Test Bench 2B 5.2. Két qua mo phong 18 6. KET LUAN Appendix A: VHDL Code (nén thanh | file va giri vao email cla GV). List of Tables References.1. KHAINIEM CHUN¢ FIFO li gi? FIFO, viét tit cia cum tir tiéag Anh First-In-First-Out) la mét cau tric b6 dém vong trong 6 dit ligu durge ghi vao truée s® durge doc ra true. FIFO thug durge sit dung lim b} dém dé truyén ot ligu gita hai he théng ma 6 do ¢6 sur khde bigt vé in s6 xung nhip gita bén truyén va nhan di ligu, Vi ly do nay, cde FIFO gbm_2 cing digu khién doc vi ghi dit ligu dc lip FIFO module duge dac tumg boi 2 thong sé: - Bang thing cia FIFO: wong durong véi kich thude ctia mot phan tir dir ligu durge dgctviét trong mot chu ky doe/viét. ~ D6 sau ciia FIFO: tuong img v6i sé phn tir dtr ligu 161 da ma FIFO 6 thé thé lou tit duge. FIFO khéng déng b9 (Dual-Clock Asynchronous FIFO)? ‘Nhu da trinh bay 6 trén, mot FIFO gim 6 giao dién doc va ghi dir ligu dc lip. Dual- Clock asynchronous FIFO 6 nghia li qua trinh doc va viét dir ligu khong dure déng bd béi cing 1 xung clock. N6i mot cach cu thé, dO ligu vio duge ghi vao FIFO béi 1 mién xung clock, va duge doe ra khdi FIFO béi 1 miga xung clock hic, va hai xung clock niy kang duoc déng b6 voi nhau. Ging dyng ciia Dual-Clock Asynchronous FIFO? C6 vai ud quan trong trong vige dém dé ligu cin truo déi gita cde mién clock khée nnhau, khi mi vige ghi dit ligu va doc dir ligu hoat dng véi hai xung clock dc lép nhau [11]. YEU CAU THIET KE ‘Dé xuat va thuc hién mét kién tric b6 dém FIFO (First-In First-Out: dit ligu duoc ghi vao FIFO tric sé urge doc ra trade) khong dng b) véi 2 tin higu xung nhip clock doe lap cho thao tic ghi dit ligu vi doe dt Lieu. ‘MO hinh hoat dong cua FIFO doc mo ta trong Figure |. FIFO 1a mot mang cée phin tr nhé duoe quan ly gidng nhu mot bé dém vang: tite li khi dit ligu durge ghi/doe dén dia chi lén hat cita mang né sé diac thiét lap 43 quay lai tir dia chi 0. Mai FIFO thwamg e 2 con tr dia chi dé quan ly vi tri 6 nhé c6 thé doc (Rptr) va vi tri 6 nhé due phép ghi di ligu téi (Wptr). Khi thue hign mét thao téc doc FIFO, ndi dung ciia 6 nhé duge tri t6i boi Rptr (c6 dia chi duoe hm trong Rptr) duge doc va gid tri cua Rptr duoc ting mét don vi. Twong tu, khi thue hign mét thao téc doc FIFO, ndi dung ciia 6 nhé duge tro t6i boi Wptr (c6 dia chi duoc hina trong Wptr) duge doc va gii tri cia Wptr duge ting mot don vi, Ngoai ra né cing cin c6 2 BIbign trang thai d& lua trang thai diy (FULL) hay rng (EMPTY) oiia FIFO. C5 2 cdich 43 quyét dink trang thai FULL vi EMPTY cita FIFO. Trong mé hinh mét Figure la, Trang théi EMPTY twong ing khi con tré dge Rptr tré t6i cing mgt vj tri voi con tré viét Wptr. Khi FIFO duoc reset, né duoc thiét lip ti trang thai nay véi con tr Rptr vi Wptr cling tro t6i 6 nhé dia chi0. Trang théi FULL xdy ra khi gid tri Wptr + 1 = Rptr. Mac dit trong trong hop nay mang nhé vin con mot 6 nhé (c6 dia chi twong img voi gid tri cba Wotr) chira woe ghi dir ligu, nhung ching ta khdng thd lua df ligu tdi né. Bidu niy bei vi sau khi ghi dir ligu t6i 6 nhé nay, gid tri cla Wptr duc ting lén mot | don vi va cing trd t6i mot 6 nhé v6i Rptr, va chiing ta khong phn biét duoc day 1a trang théi EMPTY hay FULL. Trong mé hinh mét Figure 1b, 48 trnh vige ling phi mét phan tir nhé cite FIFO khi & trang thii FULL, no thém vao mét bién dém (Data_Cnt) sé 6 nhé cia FIFO dang duge sir dung. Gia tr cia Data_Cnt durgc tang 1 don vi sau méi thao tic viet t6i FIFO, va due giém di mét don vi sau méi thae téc doc dir ligu tir FIFO. Trang thai EMPTY va FULL s duge quyét dink dua vao gid tri eta Data_Cnt: oj 4 Cae die tinh chit yéu € Néu Data_Cnt = 0, FIFO 6 trang thai EMPTY, ‘Néu Data_Cni = I, FIFO 6 trang thai FULL. Rptr q Rptr Wptr Wotr Fuse Full Sta Emply_Sta Emply_Sta N Data_Cnt (a) (b) Figure 1. M6 h guyén ly hogt dong cia FIFO FIFO: + Hai giao dign ghép noi doc viéi dit ligu, mét cho viét dit ligu t6i FIFO, m6t cho doc dit igu tie FIFO: Hoat dong doc vi viét duge diéu kh doc/viét dc lap, Bus dir ligu doc va bus di ligu viét dée lap, Trang thai FIFO day (Full): hoat dong vist ti FIFO chi droe cho phép khi FIFO khong 6 tang théi khing day (tin higu trang théi FULL khdng active) in boi 2 xung nhip clock va tin higu cho phép 4]- Trang thii FIFO rng (Empty): hoat déng doc tir FIFO chi duge thue hign hi FIFO khong 6 trang thai rng (tin higu trang thai EMPTY khdng active) - Trang thai sou Reset: FIFO duoc dura tdi trang thai Empty, dng thii cde con tro doc viét duge x6a vé 0. + Dung tong va d6 rong cia Bus die lew: - D6 séu FIFO (sé phin ti nhé cia FIFO): duge xée dink qua tham sé ADD_WIDTH cia thiét ké . . - Dé rong bus dir ligu: durge xée dinh qua tham s6 WIDTH otia thiét ké 3. THIET KE 3.1. Chu trie FIFO Céu tric cia mét FIFO khong dng b6 véi véi 2 tin higu xung nip clock de lip cho thao tac ghi dit ligu va doc dit liéu duge chi ra trong hinh Error! Reference source not found... Reset R_CLK Reset RCLK IN_DATA ouT_paTa Dataln "PATA a port Memo "| —- Dataout WADD WENA R_ENA_R_ADD 7 [Res] [Res] Y WOK Rest ROK Rea Wadd_cnt (“| ) Radd_cnt FULL < Conical + EMPTY ——1 FIFO WE RE Figure 2.Mé ti chu tréc edn dual-clock asynchronous FIFO.Table 1. Description of /O port of FIFO Signals | Direction | Width (bits) | Reset Value Description Write Interface Datain 1N FLIT SIZE | Don'teare _ | Cdng nhip di ligu 6i FIFO We 1 1 0 Cho phép ghi dt ligu tsi FIFO WE="1': Cho phip ghi w_cLK 1 1 Undefined _ | Tin higu Clock cho thao ti vigt FULL our 1 o Thong tin trang thai ua FIFO day hay khng? FULL ~1: FIFO diy Read Interface Dataout out] FLIT_SIZE | Don'tcare | Céng xuit dt gu Khoi FIFO RE 1N 1 0 Cho php doc di ligu khai FIFO RE = ‘1’: Cho phép doc RCLK IN 1 Undefined _| Tin higu Clock cho thao tac doc EMPTY our [1 ‘Thong tin trang thai cia FIFO diy hay khéng? EMPTY = 1: FIFO Reset IN 1 0 Tin higu reset khéng dng bé, tick ccue mite thap, xéa b} nhér va céc thanh ghi trang thai bén trong FIFO Generic DATA_WIDTH FLIT_SIZE FIFO data width in bit ADDR_WIDTH Address width 3.1.1. BG nhé (Dual-port memory) BO nhé duge ding dé luu dit ligu tam théi trong FIFO. Dé hé tro kha ning doc viét déng thoi, mét b6 khdi nhé hai cing doc viet duge st dung. éu khién (Control Unit) Don vi digu khién 8 chire ning tao ra céc tin higu digu khién (ahr chi sa trong hinh Figure 3) qué trinh ghi dit ligu ti béa ngoai vio FIFO eing alu qué trinh ly dit ligu tir FIFO va viét ra bén ngoai. [6]Nev day 8 ward cud Néuday la 6 nko téog ‘ung rag FIFO ‘us cng tang FIFO Empty_out FulLout ReadEnin WriteErin roux fF] WCLK { bot —— bin Row_cnt © XK ct ENKpt9 A Rptr c cH pir Wotrcnt ¢ cH Wptr c cH (a) Read FIFO Timing ow ‘¢ FIFO Timing Figure 3. Gia 48 thoi gian cho cite tin hifu ditu Khim dge/vige FIFO, Cha y ring, rong hinh wen dura ra trudmg hop dic bigt cho c& thao tie doc (doe tir dt ligu cuéi eiing e6 trong FIFO) va viet (vio vi tri trdng cudi ciing e6 trong FIFO), Do dé, sau thao tac doc va viét, cdc tin higu Empty_out va Full_out tuong ting déu tu déng chuyén lén 1 dé bao trang thii Empty hoi Full cia FIFO mit cich twong ting. Trong trang hop cén lai, eée tin higu nay sé tiép tuc duy tri mite 0. 6 hai bd dém dia chi duge sir dung cho vige to ra céc dia diéu khién doe/viét dt lieu ra/téi bé nhs béa trong ciia FIFO. Cée b6 dm dia chi e6 thé duge thiét ké theo phuong phip dém nhi phin hode dé theo ma Grey. tuy nhién phuong phap duoc sir dung phai la nhur nhaw cho bé dém dia chi viét va doc dé dam bio qué trinh doc va viét dién ra theo cing mét trat tu. 4. VHDL CODE 4.1, Bin m6 ti FIFO VHDL file: FIFO.vhd == (C) COPYRIGHT 2014 ALL RIGHTS RESERVED ~- The entire notice above must be reproduced on all authorized copies. sync_FIFO.vhd ‘ctor Nguyen= Date: Version : 0.1 -- Description : A processing Element. Modification History: Date By Version Change Description 05/08.2015 0.1 Original library ieee; use icee.std_logie_1164.all; use iece.std_logic_unsigned.all: ~-use work.User _lib.all; Entity ASYNC_FIFO is generic ( DATA_WIDTH :integer := 8; ~ FIFO word width ADDR_WIDTH sinteger :~ 8 ~ Address width } port ( ~ Reading por. Data_out + out std_logie_vector (DATA_WIDTH-1 downto 0); Empty_out + out sid_logie. ReadEa_in in std_logic; RCIk_in sin std_fogie; ~ Writing port. Data_in in std_logic_vector (DATA_WIDTH-1 downto 0); Full_out out std logic; WriteEn_in in std_logic: WClk in sin std logic; ~ Reset nReset_in sin std_logie } end ASYNC_FIFO, architecture rtl of ASYNC_FIFO is signal Wptr = std_logic_vector (ADDR_WIDTH-I downto 0) <= (others => 0" signal Rptr_—_: std_logic vector (ADDR_WIDTIHI-1 downto 0) := (others —>'0'); signal Wptr_Cnt = std_logic_vector (ADDR_WIDTH-1 downto 0) == (others => 0°: signal Rptr Cnt: std_logie vector (ADDR_WIDTH-I downto 0) = signal Int_WrENA : std_logic ; signal In REENA _ : std_logic ; signal Empty sta std_logic; signal Full_sta std_logic; signal data_ent integer == 0; component counter_Nbit is reneric (COUNTER _WIDTH sinteger = 8 : port( Clk sin sid_logie, Enable: in std_logie; Clear: in std logic; Dout —: out std logic_vecto(COUNTER_WIDTH - | downto 0) end component; component dpmem2clk is generic ( DATA WIDTH integer Word Width ADDR_WIDTH integer = 8 — Address width ): port ( ~- Writing port Welk in std_logie; ~- write clock Wen in std logic; -- Write Enable Wadd in sid_logic_vector(ADDR_WIDTH -1 downto 0); ~ Write Address Dawain in stl logic vectonDATA WIDTH -I downto 0); -- Input Data ~ Reading port Relk in std_logic; -- Read clock Ren 1 std_logic; ~ Read Enable Radd in std_logie_vector(ADDR_WIDTH -1 downto 0); ~ Read Address Dataout _: out std_logie_vector(DATA_WIDTH -1 downto 0); ~ Output data ~ Clear Reset sin sid_logie -~- Reset input ): end component; begin ~ Dual port memory with 2 clocks memeore : dpmem2clk Generic map ( DATA WIDTH => DATA_ WIDTH, ADDR_WIDTH => ADDR_WIDTH) port map ( Welk => WCIk_in, Int_WrENA, Data_out, Reset _in~- Logic for computing next write address Wadd_Cnt: counter_Nbit Generic MAP (COUNTER_WIDTH => ADDR_WIDTH) port map ( Ck => WClk in, Enable Int_WrENA, Clear nReset_in, Dout => Wptr_Cnt » ~- Register for write address : Process (WCLK_IN, nReset_in) IfnReset_in ="0'then Wptr < 0); elsif (WCLK_IN ='0) and (WCLK_IN'Event) then then Wptr <> Wptr_Cat; else ‘Wptr <= Wptr, ~end if, end if End Process Wptr_proc; -- Logie for computing Next Read address Radd_Cnt: counter Nbit Generic MAP (COUNTER_WIDTH => ADDR_WIDTH) port map ( Clk RClk_in, Enable => Int_ RdENA, Clear nReset_in, Dout => Rptr_Cnt } ~- Register for Read address Rpir_proe: Process (RCLK_IN, nReset_in) BEGIN If nReset_in="0'then Rpt < (others => 01), elsif (RCLK_IN = '0’) and (RCLK_IN'Event) then ~if Int RdENA ="1' then Rptr = Rptr_Cnt; else Rptr <= Rptr; ~end if end ifs End Process rptr_proc: ~ Fulv/Empty Empty sta <="I" when (Wptr Cnt =Rptr Cnt) else 10)Full sta <=T' when (Rpir_Cat = Wpir_ Empty out <= Empty sta: Full_out <= Full_sta; iat + "T") else 0! ~ Internal Read/Write enable ~Int_WrENA <= WriteEn_in and (not Full_sta) and (WriteEn_in nand ReadEn_in); ~Int_RdENA <= ReadEn_in and (not Empty_sta) and (WriteEn_in nand ReadEn_in); Int_WrENA < WriteEn_in and (not Full_sta); Int_RdENA <= ReadEn_in and (not Empty sta): end architecture; Ban mé ta bé ahé Dusl-port memory VHDL file: dpmem.vhd Tibrary ieee; use ieeestd_logic_1164all; use ieee.std_logic_unsigned.all; ~ Synchronous Dual Port Memory entity dpmem2clk is generic ( DATA WIDTH integer = 8; — Word Width ADDR_WIDTH integer <8 Address width ): port ( ~- Writing Welk in std_logic; write clock Wen in std logic; Write Enable Wadd + in_std_logic_vector(ADDR_WIDTH -I downto 0); --Write Address Datain in std_logic_vectorDATA_WIDTH -1 downto 0) := (others =>"0'; ~ Input Data Reading Relk in std logic; -- Read clock Ren in stdlogic; -- Read Enable Radd std_logic_vector(ADDR_WIDTH -1 downto 0); ~Read Address Dataout nut std_logie_vectonDATA_WIDTH -1 downto 0); ~ Output data nReset + in_std_logic ~ Reset input }: end dpmem?elk, architecture dpmem_arch of dpmem2clk is type DATA_ARRAY is array (integer range <>) of std logic vector(DATA WIDTH -I downto 0): ~ Memory Type aySignal data DATA_ARRAY(0 to (2**ADDR_WIDTH) -1) = (others => (others > 0); ~Local data begin --dpmem_arch -- purpose: Read process type: sequential inputs : Relk outputs: ReProc : process (Relk, nReset) begin ~- process ReProc if nReset ='0' then Dataout <= (others elsif Relkevent and Relk then rising clock edge if Ren ="I'then Dataout <= data(conv_integer(Radd)); else Dataout <= (others > 'Z'); end if; endif, end process ReProc; -- purpose: Write process type: sequential inputs : Welk outputs: WiProc : process (Welk) begin ~ process WrProc if Welk’event and Welk ="I' then ~- rising clock edge if Wen ='I' then data(conv_integer(Wadd)) <= Datain; endif; end if, end dpmem arch; 4.3. BO dém dia chi Counter_Nbit.vhd library IEEE; use IEEESTD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity counter Nbitis gencric ( COUNTER WIDTH :integer = 8 } 112)port Clk : in STD_LOGIC; Enable: in std_logic; Clear: in STD_LOGIC; Dout = out STB_LOGIC_VECTOR(COUNTER_WIDTH - 1 downto 0) ‘ end counter_Nbit; architecture counter_arch of counter_Nbit is signal m : std_logic_vector (COUNTER_WIDTH-| downto 0); begin counting : process (Clk,Clear, enable) is begin if (Clear ='0) then m < (others => '0’) elsif (CIk'EVENT AND Clk if (Enable ~'1') then m<=mé+l; else end if: end if 1) then end process counting; Dout <=m; end counter_arch; 5. KIEM CHU S.1.Test Bench library ieee: use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ASYNC_FIFO_TB is end entity ASYNC_FIFO_TB; architecture RTL of ASYNC_FIFO_TB is ‘component ASYNC_FIFO is generic ( DATA_WIDTH -integer ADDR_WIDTH :integer } 013]port( ~ Reading port. Data_out + out std_logic_vector (DATA WIDTH - | downto 0); Empry_out out std_logi ReadEn_in in std_logic: RCIk_in in std_logie; ~ Writing port. Data_in in std_logie_ vector (DATA_WIDTH - I dowato 0); Full_out out std_logi WriteEn_in in std_logi WClk_in sin std_logic; ~ Reset nReset_in in std_logic end component ASYNC_FIFO; CONSTANT DAT_WIDTH 2 INTEGER CONSTANT ADD_WIDTH _: INTEGER signal MASTER_ RST td logic signal WR_CLK _: std_logic signalWR_EN std logic :="0' signal DATA 1: std_logic_vecto(DAT_WIDTH - | downto 0) == (others => 0‘); signalRD_CLK std logic signal RD_EN std_logic signal DATA_O _: std_logic_vector(DAT_WIDTH - I downto 0) == (others > '0'); signal FULL std_logic signalEMPTY std logic =='I’ signal DATA_OUT_COUNT : std_logic_vector(DATA_WIDTH-I downto 0) begin ~ Generate reset signal process begin MASTER RST <'0; wait for 10 ns; MASTER_RST wait for 2670 ns; --MASTER_RST wait for 2 ns; ~MASTER_RST <="; wait; end process; ASYNC_FIFO_INST_I : ASYNC_FIFO generic map ( DATA WIDTH => DAT WIDTH, U4)ADDR_WIDTH > ADD_WIDTH ) port map( ~ Reading port. Data_out DATA_O, Empty_out EMPTY, ReadEn_in RD_EN, RCIk in > RD_CLK, ~ Writing port. Data_in DATA I, Full_out = FULL, WriteEn_in > WR_EN, WClk_in WR_CLK, ~ Reset nReset_in => MASTER_RST » ~ Generate write clock process begin while True loop WR_CLK = 0; wait for 3 ns; WR_CLK ="1'; wait for 4 ns; end loop; end process: ~ Generate read clock process begin while True loop RD_CLK <= wait for 2 ns; RD_CLK wait for 3 ns; end loo; wait; end process; ~ Write process process begin ‘wait for 20 ns; —Test write full wait until falling edge(WR_CLK); wait for I ns: 03]Torin I to 256 loop DATA_I < std logic_vector(to_unsigned(i, DAT_WIDTH)); — wait for 1 as; WR_EN <="I'; wait for 6 n: ~ Test Bypass wait until Empty = wait for 25 ns: WR_EN ='T; DATA 1 wait for 6 as; WR_EN wait for I ns; WR_EN='I; wait for Ins; ~ Test read/write parallel wait for 10 ns; ~-wait until falling edge(WR_CLK); ~-wait for | ns; ~for iin 10 t0 20 loop WR_EN <='1' DATA_I <= std_logic_vector(to_unsigned(i, DAT_WIDTH)); wait for 3 as; WR_EN <= wait for 3 ns; ~-end loop; waits end process; ~ Read process process begin ~ Read until FIFO empty wait for 1820 ns; wait until falling_edge(RD_CLK); wait for I ns; for iin 1 to 256 loop RD EN<="l; wait for 4 n RD _EN<=0; wait for I ns: 116)‘end loops — test Bypass wait for 15 ns; RD_EN<"1’ wait for 4 ns; RD_EN< wait for | as; RD _EN<="l’ wait for4 ns; RD_EN<= wait for I ns; ~ Test read/write parallel ~-wait for 26 ns; wait for 79 ns; wait until falling_edge(RD_CLK); wait for | ns; for iin 1 to 2 loop RD_EN<="T; wait for? end process; ~process —begin = Bypass test ~ wait for 2615 ns: — waituntil falling edge(RD_CLK); = wait for | ns; - WR_EN<='I'; - RDEN - DATA _1<=X"34"; — wait until rising edge(RD_CLK), ~ wait until rising_edge(RD_CLK): - WREN< - RDEN — wait until rising edge(RD_CLK); - WREN<= - RDEN — wait until rising edge(RD_CLK), - WREN<= - RDEN = wait for 2 ns; = wait: 07)end proc end RTL: 5.2. Két qua mé phong Figure 4 Két qua chay mb phing qua trinh vit dt tigu vio FIFO. Figure 4 chi ra dan séng m6 phong qué trinh ghi ligp tiép dir ligu vao FIFO. Cha y ring tin higu Empty chuyén tur 1 xuong 0 khi phan tir dir iéu dau tién duoc ghi vao FIFO, diéu nay bao higu ring trong FIFO da 6 dit lifu vi 6 thé tién hanh qué trinh doe tir FIFO. Figure 5. Két qui chay mé phing qua trinh dge d0 liga, Figure 5 chi ra két qua chay mé phong qué trinh ghi dit ligu dén khi khién bé dém FIFO diy. Diéu nay duoc nhan biét théng qua quan sat that tin higu Full chuyén tir 0 lén 1. Lic ny khéng thé tiép tue ghi dit ligu vao FIFO duge nia. Muén ghi dir ligu voa FIFO can tién hanh doc di liga ra khoi FIFO. Khi phan tir diu tién duoe doc ra khdi FIFO, tin higu Full jeu Ide nay da c6 vi wi tréng ben trong FIFO dé ghi dat ligu méi vao chuyén wr 1 vé 0, bao U8)Figure 6. Két quai mi phéng gus trinh dgc/viétdign ra dng thai. Figure 6 chi ra két qua m6 phéng doc dit ligu ra khéi FIFO dén khi Empty chuyén tir 0 ln 1, bao higu ring to’ b6 dit ligu trong FIFO da duge doc ra hét. Tiép dén, két qua m6 phong chi ra hoat dong doe/vidt t6i FIFO duge tién hanh déag thoi. 6. KET LUAN Dir ligu duov ghi vao FIFO va duge doc ra theo ding thir ty di duoc dua vio, thoa man yeu cau vé nguyén ly lam vige etta FIFO. Trang thai rng hode day ctia FIFO da duge chi ra dling béi cée tin higu EMPTY va FULL, Qué trinh doc vigt duge tiénn hinh tich bigt hoe dng thoi bai ede tin higa xung hip d6c lip. 119]List of Figure Figure 1. Mé hinh nguyén ly hoat déng cia FIFO. Figure 2. Mé ta cau tnic cita dual-clock asynchronous FIFO. Figure 3. Gian 46 thoi gian cho cdc tin higu diéu khién doc/vigt FIFO. Figure 4. Két qui chay mé phéng qui trinh viét dit ligu vio FIFO. Is Figure 5. Két qui chay mo phong qué trinh doe dt ligu,.... Figure 6. Két qui m6 phong qua trinh doc/viét din ra ding théList of Tables 6 Table 1. Description of /O port of FIFO. Table 2. Description of VO port of dual-port memory... Error! Bookmark not defined. [22]References 11) Christophe Bobda, “Introduction to Reconfigurable Computing - Architectures, Algorithms, and Applications”. Springer, 2007. ip] A. Shoa and S. Shirani, “Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey”, Journal of VLSI Signal Processing, Vol. 39, pp.213-235, 2008, Springer Science. is] G. Theodoridis, D. Soudris and S. Vassiliadis: “A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools Basic Definitions, Critical Design Issues and Existing Coarse-grain Reconfigurable Systems”, Springer 2008, p89-149. i) Kathryn S. McKinley, Steve Cart, Chau-Wen Tseng: “Improving Data Locality with Loop Transformations’, ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 18, Issue 4, July 1996, Pages 424 - 453. 1) Gajski D., Dutt N., Wu A., Lin, S: “High-Level Synthesis, Introduction to Chip and System Design”, Kluwer Academic Pub. (1992), is) Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala: “Handbook of signal processing systems”, p449-p485, Ist Edition, September 1, 2010, Springer; ISBN- 10: 1441963448, im S. Sohoni, and R. Min, et al. “A study of memory system performance of multimedia applications”. SIGMETRICS Performance 2001, pages 206-215. is) lain E, Richardson: “The H.264 advanced video compression standard”, second edition, 2010, John Wiley & Sons, Ltd. 1 M. Zhu, L. Liu, S. Yin, et al.: "A Cycle-Accurate Simulator for a Reconfigurable Multi- Media System,” IEICE Transactions on Information and Systems, vol. 93, pp. 3202-3210, 2010. tno} Hung K. Nguyen, Peng Cao, Xuexiang Wang, Jun Yang, Longxing Shi, Min Zhu, Leibo Liu, Shaojun Wei: Hardware Software Co-design of H.264 Baseline Encoder on Coarse- Grained Dynamically Reconfigurable Computing System-on-Chip,_ 1EICE TRANSACTIONS on Information and Systems (SCI index), Vol.E96-D, No.3, pp.601- 615, 2013, ti) Cummings, C. (une 2005). Simulation and Synthesis Techniques for Asynchronous FIFO Design. 112] Pham, A. H. (2005, May 15). winw.asic-world.com. Retrieved from www.as world.com/examples/vhdV/asyn_fifo.html [23]