LOGIC DESIGN LABORATORY

Course Based Project on

“DIGITAL DICE ROLLER”

BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING
by

S.YASASWI 22071A04R3

VAISHNAVI BALAJI 22071A04R7

VNR VIGNANA JYOTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY

(An Autonomous Institute, Affiliated to JNTU H, Accredited with NAAC ‘A++’ grade, Approved by
AICTE, New Delhi) Bachupally, Nizampet SO,Hyderabad, Telangana - 500090.
2023-24
VNR VIGNANAJYOTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY
(An Autonomous Institute, Affiliated to JNTUH, Accredited with
NAAC ‘A++’ grade, Approved by AICTE, New Delhi) Bachupally,
Nizampet SO, Hyderabad, Telangana 500090.
 DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that the project entitled “DIGITAL DICE ROLLER ” is a bonafide record
of the work done by S.YASASWI (22071A04R3) and VAISHNAVI BALIJI
(22071A04R7), for the completion of course ‘LOGIC DESIGN LABORATORY’ of
ELECTRONICS AND COMMUNICATION ENGINEERING at VNR VIGNANA JYOTHI
INSTITUTE OF ENGINEERING AND TECHNOLOGY, HYDERABAD during the
academic year of 2023-2024.

Course co-ordinators: Head of the Department

Dr. N. Neelima, Assistant Professor Dr. S. Rajendra Prasad

Mr. C. Kaushik, Assistant Professor Professor & HOD, ECE
CONTENTS:

Abstract.

1. Introduction.

2. Software and Simulator Used

3. Implementation of TIC TAC TOE Game in Verilog

4. Verilog Code for TIC TAC TOE Game

5. Results and Discussion

6. Conclusion and future Scope

ABSTRACT:

The "Digital Dice Roller" project aims to create a versatile and interactive digital
dice using Verilog hardware description language. This project leverages the
power of field-programmable gate arrays (FPGAs) to implement a random number
generator and a user-friendly interface. The digital dice emulates the traditional
six-sided die commonly used in board games and provides a modern, electronic
alternative. The core functionality includes generating random numbers in the
range of 1 to 6, simulating the roll of a physical die.

The Verilog hardware description language is employed to describe the

functionality of the digital dice roller. The code is synthesized using Vivado, a
high-level synthesis tool, and implemented on an FPGA platform. The resulting
hardware design is capable of producing random numbers that mimic the statistical
distribution of a fair six-sided die.

Key Features:

Random Number Generation: The Verilog code incorporates a pseudo-random

number generator (PRNG) to simulate the unpredictability of a dice roll,
ensuring fairness and randomness in the outcomes.

User Interface: The digital dice is equipped with a user interface, which could
include buttons for rolling the dice and displaying the result using LEDs or a 7-
segment display.

Configurability: The project is designed to be easily configurable, allowing users

to customize aspects such as the display format, the number of dice to roll, and
the method of displaying results.

Real-time Interaction: The digital dice roller provides an engaging real-time

interaction, mimicking the tactile experience of physically rolling a die, but in a
digital and electronic form.

Verilog Implementation: The entire project is implemented in Verilog, leveraging

the hardware description language to model the logic of the dice roller. This
includes the random number generation, user input processing, and display
control.
INTRODUCTION:

The project on a digital dice roller implemented in Vivado using Verilog code
brings forth an innovative approach to simulating the randomness of rolling a
traditional six-sided die. Unlike conventional methods relying on FPGA
technology, this project explores a purely software-based implementation
within the Vivado design suite. By leveraging Vivado's robust design
environment without the use of FPGA hardware, the focus is on achieving a
streamlined and efficient digital dice roller.

The key element of this project is the Verilog code, meticulously crafted to
implement a pseudo-random number generator (PRNG) that emulates the
randomness associated with physical dice rolls. The absence of dedicated FPGA
hardware places emphasis on the software-centric design, making it accessible
for a broader range of applications without the need for specialized hardware.

This project caters to recreational board games and educational contexts,

offering a versatile digital dice roller solution. The software-based approach
simplifies the implementation process, making it suitable for scenarios where
dedicated FPGA hardware may not be readily available or required.

In essence, this project explores the realm of digital dice rolling without
relying on FPGA technology, showcasing the adaptability and efficiency of a
software-driven approach within the Vivado design suite.

ADVANTAGES:
Implementing a digital dice roller in Vivado using Verilog code presents several
advantages:

1. Cost Efficiency:
Eliminating the need for dedicated FPGA hardware reduces costs associated
with hardware development and procurement.
2. Accessibility:
A software-based approach makes the project more accessible to a wider
audience, as it doesn't require specialized FPGA knowledge or hardware.

3. Ease of Deployment:
The absence of FPGA hardware simplifies the deployment process. The project
can be easily executed on various platforms without concerns about hardware
compatibility.

4. Flexibility:
Software-driven implementations provide greater flexibility for modifications
and updates. Changes to the dice roller logic can be made more readily in a
software environment.

5. Learning and Educational Value:

The project offers educational benefits by allowing users to focus on Verilog
programming and digital design concepts without the additional complexity of
FPGA hardware.

6. Resource Utilization:
Since the project runs in a purely software environment, it may require fewer
system resources compared to FPGA-based solutions, making it suitable for a
broader range of computing platforms.

7. Quick Prototyping:
Development and prototyping are expedited as the project relies solely on
software tools, allowing for rapid iterations and testing.

8. Adaptability:
The software-driven approach ensures adaptability to diverse computing
environments, making it suitable for scenarios where dedicated FPGA
hardware might not be practical or available.
9. Reduced Development Time:
The absence of hardware constraints simplifies the development process,
potentially reducing the overall time required for project completion.

10. Scalability:
The project can be scaled easily to accommodate varying computational
resources, making it adaptable to different platforms and specifications.

APPLICATIONS:

While the primary design of a digital dice roller in Vivado using Verilog code
typically involves FPGA technology, if we consider a software-only
implementation, the applications may be limited to computing platforms
capable of running Verilog simulations. Here are potential applications:

1. Educational Simulations:
Simulating dice rolls for educational purposes, teaching probability concepts
in computer science or mathematics classes.

2. Game Development Prototyping:

Prototyping and testing of dice-based game mechanics in software
environments before hardware implementation.

3. Desktop Applications:
Integration into desktop applications for board games, providing a digital
alternative to physical dice.

4. Programming and Algorithm Practice:

Educational tool for students learning Verilog or digital design, allowing them
to practice coding and algorithm development.
5. Online Gaming Platforms:
Integration into online gaming platforms or applications where randomization
is needed, such as virtual tabletop games.

6. Simulation Environments:
Inclusion in simulation environments for testing algorithms that involve
randomization without the need for physical dice.

7. Software Development Testing:

Testing software components that rely on random numbers, ensuring
robustness and accuracy in scenarios where true randomness is not critical.

8. Digital Learning Resources:

Integration into digital learning resources or apps aimed at teaching
probability and randomization concepts.

9. Mobile Applications:
Development of mobile applications that leverage Verilog-based dice rolling
for entertainment or educational purposes.

10. Algorithm Benchmarking:

Benchmarking algorithms that involve random number generation, comparing
performance and efficiency in a purely software-driven environment.
SIMULATION AND SIMULATOR USED:

Simulation Used: Xilinx Vivado

Simulator Used: VIVADO

IMPLEMENTATION OF DIGITAL DICE ROLLER:

The provided Verilog code represents a simple dice game logic implemented with
a finite state machine. The test bench is also included to simulate and test the
functionality. Below is a brief explanation of the code and suggestions for
improvement:

1. Code Explanation:
-The dice module represents the dice game logic, including states (s0 to s5),
inputs (rb, rst, sum), and outputs (roll, win, lose, next_state).
-The test bench, dice_tb, initializes the inputs, simulates a clock signal, and
monitors the outputs.

Dice Module:

Inputs:
- clk: Clock signal.
- rst: Reset signal.
- rb: Roll button signal.
- sum: 4-bit input representing the dice sum.

Outputs:
- roll: Output indicating a dice roll.
- win: Output indicating a win condition.
- lose: Output indicating a lose condition.
- next_state: 3-bit output representing the next state of the FSM.

Parameters:
- s0 to s5: Parameters defining the states of the FSM.

Registers:
- state: 3-bit register representing the current state of the FSM.
Initial Block:
- Initializes roll, win, lose to 0.
- Sets next_state to the initial state s0 based on conditions (rb, rst, sum,
state).

Always Block:
- On any change in rb, rst, sum, or state, updates the next_state based on
the current state.
- Utilizes a case statement to define behavior for each state:
- s0: Transitions to s1 on roll button press.
- s1: Rolls the dice (roll=1) and checks for win/lose conditions based on the
sum.
- s2: Win state. Resets to s0 on reset (rst).
- s3: Lose state. Resets to s0 on reset (rst).
- s4: Transitions to s5 on roll button press.
- s5: Rolls the dice and transitions to s3 or s4 based on the sum.

Always Block (Posedge CLK):

- Updates the state based on the calculated next_state on the positive edge
of the clock.

Dice_tb Module (Test Bench):

Inputs:
- clk: Clock signal.
- rb: Roll button signal.
- rst: Reset signal.
- sum: 4-bit input representing the dice sum.

Outputs:
- lose: Output indicating a lose condition.
- next_state: 3-bit output representing the next state of the FSM.
- roll: Output indicating a dice roll.
- win: Output indicating a win condition.

Initial Block:
- Initializes inputs (rb, rst, sum) to specific values.
- Displays simulation time, inputs, and outputs using $display.

Forever Loop:
- Simulates clock signal (clk) by toggling it every 10 time units.
Notes:

- The forever loop in the test bench simulates a clock signal, driving the
simulation.
- The test bench initializes inputs, triggers events, and displays simulation
results using $display.
- The actual functionality of the dice game is captured in the dice module's
state machine.

This code simulates a simple dice game state machine with win and lose
conditions based on the sum of the rolled dice. Adjustments can be made to the
test bench to cover various test cases and scenarios.