Digital Design and Embedded Systems

LAB – 04 – 3-bit Up/Down Counter

3-bit Up/Down Counter
The 3-bit up/down counter design has four inputs, Clk, Rst, LB, RB , and a 3-bit output Cnt, represented
by the three outputs Cnt2, Cnt1, Cnt0. If Rst is 1, the counter should reset its count value to zero (000).
Otherwise, if LB is 0, on every clock cycle the counter should count up by one number. If LB is 1, the
counter should count down on every clock cycle. Upon reaching the minimum (0) or maximum (8) count,
the counter value should wraparound. For example, when counTng up, the counter should wraparound
to 0 aUer 8, and when counTng down, the counter should wraparound to 8 aUer 0. Lastly, if RB is ever 1,
your counter should pause and conTnue displaying the current count value.
1. Write down the code for adder-subtractor circuit we discussed in the lecture. Modify it to work
as an up/down counter. (30 marks)
2. Draw the FSM to control the adder/subtractor described above. (10 marks)
 3. Implement the funcTonality described above using verilog. (40 marks)

1.
4. Develop a testbench.
a. Check that counter counts up then down correctly (5 points)

b. Check for correct wraparound funcTonality for counTng up and down (5 points)
c. Check for correct reset behavior from non-one count value (5 points)

d. Check for correct pause behavior (5 points)