King Mongkut’s University of Technology Thonburi

Department of Electronics and Telecommunication Engineering

ENE/EIE 434 Digital System Design and Implementation 1/2023

Name_________________________________ Student ID _____________________________
Module-level Design
Designer: Dr. Pinit Kumhom
Revision History:
Date Key changes Author
Dec 1, 2023 Problem statement is created. PK

Design the “Play_control” module, which is an FSM, to control the playout of music stored in the
“MusicRec” or “MusicRAM”

Fig. 1: Datapath (the white modules) which is control by the “Play_control” for playing out
music from MusicRec or MusicRAM (not showing in the figure)

Delivery: Upon the completion of the design, you should submit

1. ASM chart describing your design

2. VHDL code of the FSM described by the ASM in 1
3. VHDL testbench for simulation of the design for all cases of the start, repeat, and reverse input
4. Short report of your design explaining how you get your design and simulation results