-- (C)2017 Renesas Electronics Corporation. All rights reserved.

-- Generated by asrh2cxrh2.pl ver.1.22, 2017/09/26 14:40:49.

-----------------------------------------------------------------------------

#include "cxrh_cmn.s"

#include "cxrh_extmat_set.h"

#include "cxrh_extmat_data.s"

#include "cxrh_handler.s"

.section "SAREA_OPE_WORK", "aw"

ope_work_begin:
sram_test_area:
.space (4)
ope_work_end:

.section "SAREA_OPE_INIT", "ax"

ope_init_begin:
.word 0x12345678
ope_init_end:

.section "SAREA_INST", "ax"

.extern _main

_main:
init_proc_begin:
init_proc_end:
point_test_start:
sysc_proc_begin:
sysc_proc_end:
port_proc_begin:
port_proc_end:
csc_proc_begin:
csc_proc_end:
intc_proc_begin:
intc_proc_end:
flash_proc_begin:
flash_proc_end:
test_proc_begin:

--; For CPU subsystem clock gear up

--;#include "cpu_clock_gear_up.s"
--; write_sfr32 A_MSR_ISO_MSR_ETHER,0x00000000

test_id_set 0x00000001

write_sfr32 A_MSR_ISO_MSRKCPROT,0xa5a5a501

--;clock supply for ether

write_sfr32 A_MSR_ISO_MSR_ETHER,0x80000000

addreg_loopwait 200
--;;;---- trigger force by stimulus
//for ETH0_PHY_INT P14_8 ALT_IN5 v103//

write_sfr32 A_PORT_PKCPROT,0xA5A5A501 --;--; enable access PWE register

write_sfr32 A_PORT_PWE,0xFFFFFFFF --;--; enable access port

write_sfr32 A_PORT_PCR14_8,0x00000054 --;--; ETH0_PHY_INT P14_8 ALT_IN5
Bit[31:6] are covered in the test items of PORT team.
Refer this document to see how to assign bit number to bit[5:0] and calculate the register's value.

write_sfr32 A_PORT_PWE,0x00000000 --;--; disable access port group

write_sfr32 A_PORT_PKCPROT,0xA5A5A500 --;--; disable access PWE register

test_id_set 0x00010000
addreg_loopwait 50
test_id_set 0x00010001
addreg_loopwait 50
test_id_set 0x00010010
addreg_loopwait 50
test_id_set 0x00010011
addreg_loopwait 50
test_id_set 0x00010020
addreg_loopwait 50
test_id_set 0x00010021
addreg_loopwait 50
test_id_set 0x00010030
addreg_loopwait 50
test_id_set 0x00010031
addreg_loopwait 50
//release signals.
test_id_set 0x00010099
addreg_loopwait 50

--;;;---- trigger force by stimulus

//for ETH0_TAS_GATE v103//

write_sfr32 A_PORT_PKCPROT,0xA5A5A501 --;--; enable access PWE register

write_sfr32 A_PORT_PWE,0xFFFFFFFF --;--; enable access port

write_sfr32 A_PORT_PCR34_2,0x0000004E --;--; ETH0_TAS_GATE0 P34_2 ALT_OUT15

write_sfr32 A_PORT_PCR33_3,0x0000004F --;--; ETH0_TAS_GATE1 P33_3 ALT_OUT16
write_sfr32 A_PORT_PCR23_6,0x0000004B --;--; ETH0_TAS_GATE2 P23_6 ALT_OUT12
write_sfr32 A_PORT_PCR23_7,0x00000046 --;--; ETH0_TAS_GATE3 P23_7 ALT_OUT7
write_sfr32 A_PORT_PCR32_7,0x00000047 --;--; ETH0_TAS_GATE4 P32_7 ALT_OUT8
write_sfr32 A_PORT_PCR32_6,0x00000046 --;--; ETH0_TAS_GATE5 P32_6 ALT_OUT7
write_sfr32 A_PORT_PCR32_5,0x0000004D --;--; ETH0_TAS_GATE6 P32_5 ALT_OUT14
write_sfr32 A_PORT_PCR32_2,0x00000048 --;--; ETH0_TAS_GATE7 P32_2 ALT_OUT9
write_sfr32 A_PORT_PCR33_15,0x00000045 --;--; ETH0_TAS_GATE8 P33_15 ALT_OUT6

write_sfr32 A_PORT_PWE,0x00000000 --;--; disable access port group

write_sfr32 A_PORT_PKCPROT,0xA5A5A500 --;--; disable access PWE register

test_id_set 0x10010000
addreg_loopwait 50
test_id_set 0x10010001
addreg_loopwait 50
test_id_set 0x10010002
addreg_loopwait 50
test_id_set 0x10010003
addreg_loopwait 50
test_id_set 0x10010010
addreg_loopwait 50
test_id_set 0x10010011
addreg_loopwait 50
test_id_set 0x10010012
addreg_loopwait 50
test_id_set 0x10010013
addreg_loopwait 50
test_id_set 0x10010020
addreg_loopwait 50
test_id_set 0x10010021
addreg_loopwait 50
test_id_set 0x10010022
addreg_loopwait 50
test_id_set 0x10010023
addreg_loopwait 50
test_id_set 0x10010030
addreg_loopwait 50
test_id_set 0x10010031
addreg_loopwait 50
test_id_set 0x10010032
addreg_loopwait 50
test_id_set 0x10010033
addreg_loopwait 50
//release signals.
test_id_set 0x10010099
addreg_loopwait 50
-----------------------------------------------------
test_id_set 0x99999999
test_proc_end:
pushsp r10-r12
cmp_proc_begin:
cmp_mem32 ope_init_begin,0x12345678,0xffffffff
cmp_proc_end:
point_test_end:
jmp_test_end_seq

inst_end:

.section "ICUM_SAREA_INST", "ax"

.extern _icum_main

_icum_main:
jmp_error_end_seq
Header file

This line includes the contents of the file "cxrh_cmn.s"

The content of "cxrh_cmn.s" file contains:
+ #include "cxrh_reg_label.h": register's address.
+ #include "cxrh_macro.s": registers which will be read/write in CPU operation.

This includes the contents of the file "cxrh_extmat_set.h"

This file probably contains some configuration settings for external matrices: set or configure certain parameters.

This includes the contents of the file "cxrh_extmat_data.s"

This file likely contains data related to external matrices (which store register's value in the section location of memory).
This line includes the contents of the file "cxrh_handler.s" The content of this file likely contains interrupt handlers or other re

This declares a section named "SAREA_OPE_WORK" with attributes "aw" (allocatable and writable).
"SAREA_OPE_WORK": this operation work section area to write and store variables, buffers, or other data structures that are

allocatable: This means that the section is allocatable, and space will be reserved for it in the memory during the linking proce
writable: This means that the contents of the section can be modified during the program's execution. Data and variables ofte
executable: This means that the contents of the section can be executed as code. Instructions and executable code typically fa
only.

Mark the beginning of the operation work section.

Start section area of sram test.
Reserves 4 bytes of space in this section.
Mark the end of the operation work section.

This declares a section named "SAREA_OPE_INIT" with attributes "ax" (allocatable and executable).
"SAREA_OPE_INIT": this operation initialization section area used to store data or variables that are specifically used during t
settings, default values, or parameters will be set at the beginning of the program execution.
This marks the beginning of the operation initialization section.
Initializes a 32-bit word with the value `0x12345678` (a check to ensure that the initialization was successful - which means ini
This marks the end of the operation initialization section.

This declares a section named "SAREA_INST" with attributes "ax" (allocatable and executable).
"SAREA_INST": this instruction section area used as a section of memory where executable code resides. This could include th
program.
This declares an external section named "_main."

This is the entry point for the program. The code following this label initializes various processes, sets configurations, and trigg
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of point_test process.
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of the initialization process.
These labels mark the end of the initialization process.
These labels mark the beginning of test_proc process.

Comments explaining the purpose of the following code. (thiết lập hệ thống clock cho CPU)

Redundancy.

Trigger test case using test ID 0x00000001.

write_sfr32: a macro that writes a 32-bit value to a Special Function Register (SFR).
A_MSR_ISO_MSRKCPROT: This is the identifier of the Special Function Register (SFR) where the value 0xa5a5a501 will be writt
Section 17.2.4.1: This register is used to control the clock supplied/stopped modes of the target module.

This setting is used to enable the access to write to PWE register.

Section 2.5.34: PWE — Port Write Enable register (FFFF_FFFF means enable write access to all ports)

This part is used to setting port alternative function for pointed signal by writing value to the Port Control Register.
2.5.25 PCRn_m/JPCR0,1_m — Port Control Register
Use PCR register to setting a port's function.

2.5.14 PINVn/JPINV0,1 — Port Output value Inversion Register

2.5.19 PODCn/JPODC0,1 — Port Open-drain Control Register

Push-Pull:
- Use push-pull when the output signal needs to actively drive both high and low states.
- Suitable for scenarios where the device needs to actively control the voltage level on the line.
Open-Drain:
- Use open-drain when multiple devices share the same bus or line.
- Allows multiple devices to pull the line low, but leaves it floating when high
2.5.20 PODCEn/JPODCE0,1 — Port Open-drain Control Expansion Register
The emulated N-channel open-drain configuration is often used in situations where the standard open-drain output is not dire
desired, besides, it provides a way to share a signal line among multiple devices, allowing any of them to pull the line low (acti
The emulated P-channel open-drain configuration is often used in situations where the standard open-drain output is not dire
desired.

2.5.22 PUCCn/JPUCC0,1 — Port Universal Characteristic Control Register

2.5.17 PUn/JPU0,1 — Pull-up Option Register

2.5.18 PDn/JPD0,1 — Pull-down Option Register

register_value_calcu
lation.xlsx

after writing, disable access to prevent invalid write into these registers.
after writing, disable access to prevent invalid write into these registers.

test_id_set is used to create the timeline of testbench (specify the points in which the force events are occurred.
wait an amount of time to finish port setting (completely force value to signal - prevent glitch).
test_id_set is used to create the timeline of testbench (specify the points in which the force events are occurred.
wait an amount of time to finish port setting (completely force value to signal - prevent glitch).

This part is iterative to setting port alternative function for others pointed signals.

These labels mark the end of test_proc process.

These labels mark the end of point_test process.