> digital design basics (mux , decoder,endcoder, sequentila , FSM (moore , miley)

> verilog system verlilog

> cdc , upf changes -clp runs rtl updates
> ahb , or axi basics
> basics on fifos async fifo , reset , pipelining , memories
> timing sta

work
all design updates , how issues were tackeled , design debug on the same '
fixes done
flow updates and any implemetation done

timing :

mon , tue - evening 8-9, 10:30-11:30

wed , thur , fri - morning 7-9, eveving 8-9:30
sat , sun - all day