Specification

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 VI Specification v 2.2

Revison History

Date Revision Author Description

02/02/1999 0.1 Patrick Law  Initial draft
02/11/1999 0.2 Dan Shimizu  Changed Line Count to Dot Clock Count, Added Dot Clock
Latch Registers for Lightgun, Added GUNTRG[1:0] on
interface.
02/23/1999 0.3 Patrick Law  Added Nintendo proposed timing.
03/06/1999 0.4 Patrick Law  Correction.
3/11/1999 0.5 Ken Moll  Added YCrCb and Gamma
 Change name from DU to VI
4/14/1999 0.6 Patrick Law  Added new gun trigger modes.
 Added equations for RGB to YCrCb conversion.
 Added gamma correction.
 Added 4:4:4 to 4:2:2 conversion.
 Updated horizontal timing diagram.
4/26/1999 0.7 Patrick Law  Added vertical timing diagram.
 Extended register update time to the beginning of vertical back
porch. This gives more time to update VI.
 Changed VSync in the interface to Vphase to avoid confusion.
 Added PI and MEM interfaces.
07/01/1999 0.8 Patrick Law  Deleted section describing YCrCb to RGB conversion.
 Correction.
08/02/1999 1.0 Patrick Law  Delete section describing gamma correction.
 Added horizontal scaling filter.
08/05/1999 1.1 Patrick Law  Added test plan.
08/11/1999 1.2 Patrick Law  Fixed tables and diagrams.
08/17/1999 1.3 Patrick Law  Fixed non-interlace video timing diagrams.
08/20/1999 1.4 Sal Dasgupta  Added Bottom Base Address registers.
 Added Horizontal Scaler Enable Bit
08/23/1999 1.5 Patrick Law  Added more description to VI/Rohm interface control flags.
 Changed definition in the VI register to match the meaning of
bit 0 and bit 1 of the VI/Rohm interface.
08/24/1999 1.6 Sal Dasgupta  Added Output Polarity Register
 Changed ACV from 10 bits to 9 bits
 Changed EQU from 4 bits to 3 bits
09/06/1999 1.7 Patrick Law  Changed ACV back to 10 bits for progressive display.
 ACV, PRB, and PSB are double buffered for screen blanking.
 Added progressive display mode.
09/12/1999 1.8 Patrick Law  BS and BE are specified relative to vsync.
 Added non-interlace and debug mode vertical timing tables.

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 VI Specification v 2.2

 Changed horizontal display count from 11 bits to 10 bits.

09/16/1999 1.9 Patrick Law  Added VI registers’ values after power up.
09/30/99 2.0 Sal Dasgupta Changed definition of hcount & vcount for interrupt, gun trigger,
and display position registers
11/30/99 2.1 Sal Dasgupta  Added Clock Select, DTV Status, Border HBS, Border HBE,
Scaling Width Registers
 Added Nishumi-san’s Vertical timing diagrams
 Added Nishumi-san’s Timing diagrams
 Added explaination about odd/even HBE
8/10/00 2.2 Sal Dasgupta  Added High Addr register
 Updated explanation of HCOUNT & VCOUNT counting
scheme

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 VI Specification v 2.2

1 VI Overview
VI (Video Interface) has the following functions:

 Interfaces with the Rohm video encoder using a 10 pins (8 data + 1 clock + 1 phase) interface @ 27MHz.
 Interfaces with external video connector @54Mhz to produce progressive 720x480 image.
 Generates NTSC, PAL, or M-PAL timing.
 Requests pixels from the external frame buffer for displaying.
 Allows panning and windowing of a display region.
 Video timing counter (resetable on field or frame basis)
 Interrupts the CPU using four programmable timing registers.
 Captures raster position using two lightgun latches.
 Optionally, horizontaly scales frame buffer image
 Interfaces to 3D LCD display.

A high level diagram of VI is shown below:

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2 VI Interfaces
The following diagram shows the interfaces of VI.

2.1 PI/VI Interface

This interface allows Processor Interface (PI) reads and writes to control registers in the VI.
pi_viAddr(8:1) : All registers are 16 bits. They are addressed on short boundaries.
pi_viData (15:0) : 16 bit write data bus
vi_piData(15:0) : 16 bit read data bus
pi_viRd: 0 is a write; 1 is a read
pi_viReq: asserted for one cycle. pi_viAddr and pi_viRd valid for the cycle. If pi_viRd is not asserted, then
pi_viData is also valid for the cycle.
vi_piAck: when a read request is issued, VI will assert this signal for one cycle and put the register data onto
vi_piData bus. During a write cycle, this signals that write is done.
vi_piIntr: asserted by VI to interrupt the CPU.
resetb: hardware reset

All interface control signals should be registered to avoid timing problem due to long wire. For example, VI
should register the PIreq signal before use, and the generated VIack signal should also be registered on both sides.

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 VI Specification v 2.2

That’s why there is a minimum of one clock delay between PIreq and VIack, and between VIack and the next
PIreq.

32-bit read/write word ordering. The Gecko CPU can do 32-bit read and write operations to the VI through the
VI / PI interface. The PI will translate the 32-bit read/write operation into two separate 16-bit operations across
the PI/VI interface. The internal architecture of Flipper is uniformly big-endian, so the 32-bit data is transferred in
the order: hi-word (bits [31:16], address n) first, followed by lo-word (bits[15:0], address n+1).

2.2

2.3 VI/EN Interface

This interface connects the display output with an external video encoder. It consists of three sets of signals: vclk
(video clock), vphase (video clock phase), and vdata (video data).
Pin Description Width

vclk Video clock. 27 MHz. 1

vphase Video phase. This signal indicates YCb (low) or YCr (high) set. 1

vdata Video data. This bus contains YCrCb data during active display and video timing 8
signal during blanking.

A timing diagram is shown as follow:

Since Y is clamped to 0x10 during active display, Y is set to 0x00 during blanking interval. During that time, Cb and
Cr are used for outputting video timing signals:
U/V Data Flag Description

Bit 7 C Composite Sync Flag (active low). Refer to the timing diagrams.

Bit 6 F Field Flag. F = "0" for odd-number fields (Fields 1, 3, …), F = "1" for even-number
fields (Fields 2, 4, …).

Bit 5 V Vertical Sync Flag (active low). Refer to timing diagrams.

Bit 4 H Horizontal Sync Flag (active low). Refer to timing diagrams.

Bit 3 B Burst Flag (active low). This signal indicates the location of the color burst. It is

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 VI Specification v 2.2

active once every line.

Bit 2 K Burst Blank Flag (active low). When active, color burst of a line should be blanked
out.

Bit 1 N NTSC/PAL and M-PAL Mode Flag. N = "0" for NTSC mode, N = "1" for PAL or M-
PAL mode.

Bit 0 I Interlace/Non-Interface Mode Flag. I = "0" for interlace mode, I = "1" for non-
interlace mode.

It is important to note that since the timing signals are output in the Cb and Cr data only, they should be expanded
back to 13.5 MHz inside the video encoder. As a result, hsync and burst may be shifted by one pixel. A timing
diagram is shown below:

There are two cases of operation that should be noted:

- Blanking ends on an even pixel (HBE is even)
- Blanking ends on an odd pixel (HBE is odd)
In cases where HBE is even, the first chroma sample will be Cb followed by Cr, etc. In cases where HBE is odd,
the first chroma sample will be Cr followed by Cb, etc. The diagram below illustrates this fact.

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 VI Specification v 2.2

TEST MODE

A test mode is added to this interface for bring-up and debug purposes. During test mode, vclk and vdata behave as a
standard CCIR656 interface. This allows easy integration with off-the-shelf video encoders.

2.4

2.5 VI/MEM Interface

This interface allows reads from main memory from the video interface. All reads are cache-line sized (32 bytes) and
are transferred over a 64-bit bus. The interface signals are shown in the following diagram:

signal description
vi_mem_addr[25:5] Address of cache-line for read.
vi_mem_req Asserted for one cycle to issue a cache-line read request. Pi_mem_addr is valid
for that cycle..
mem_ vi_ack Asserted for one cycle to signal return of data from memory. Bytes 7 to 0 of the
cache-line are sent in that cycle. Bytes 15-8 , 23-16 and 31-24 are sent in the
following cycles on the mem_pi_data bus. All read requests are processed in-
order
mem_ vi _data[63:0] 8 byte bus to transfer data from memory. A cache-line is transferred on this bus in
4 back-to-back clocks.

This interface supports single outstanding read requests. A new read request can be issued After the acknowledge
for the last one is received

All interface control signals should be registered to avoid timing problem due to long wire. For example, memory
controller should register the vi_mem_req signal first, and the generated mem_vi_ack signal should also be
registered on both the memory controller side and the Module side

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 VI Specification v 2.2

Byte ordering of data on the read and write buses is shown below

2.6

2.7 Gun Trigger/VI Interface

This interface is the gun trigger input of DU. It consists of two pins, each pin detects the instance of the screen flash
when the trigger is pulled. A latch circuitry is used to mark the value of a screen timer when a screen flash is
registered.
Pin Description Width

gt0 Gun trigger of gun #0. 1

gt1 Gun trigger for gun #1. 1

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 VI Specification v 2.2

4 Theory of Operation
4.1 Video Timing
In order to simplify the design of the external encoder, VI generates most of the video timing required by the encoder.
It supports the timing of NTSC, PAL, and M-PAL. In addition, it displays the top-field only in non-interlace mode.

4.1.1 Vertical Timing

4.1.1.1 NTSC Vertical Timing

Symbol Description NTSC Non-interlace Debug Mode Progressive
NTSC
(525)

EQU* Equalization pulse 6 6 6 12

ACV** Active video 241 241 241 480

PRB (odd/even) Preblanking 24/25 24/24 24/25 44/44

PSB (odd/even) Postblanking 1/0 2/2 1/0 10/10

BS1/2/3/4 Color burst starts 12/13/12/13 12/12/12/12 - 24/24/24/24

BE1/2/3/4 Color burst ends 520/519/520/519 520/520/520/520 - 1038/1038/1038/1038

* During non-interlace mode, an equalization pulse is displayed only on the first half of a full line while a serration
pulse is displayed only on the second half of full line.
** With the exception of ACV, all the counts are in half lines. ACV is measured in full lines.

4.1.1.2 PAL Vertical Timing

Symbol Description PAL Non-interlace Debug Mode Progressive
PAL
(625)

EQU* Equalization pulse 5 5 5 10

ACV** Active video 287 287 287 576

PRB (odd/even) Preblanking 35/36 35/35 35/36 58/58

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PSB (odd/even) Postblanking 1/0 2/2 1/0 10/10

BS1/2/3/4 Color burst starts 13/12/11/10 13/11/13/11 - 20/20/20/20

BE1/2/3/4 Color burst ends 619/618/617/620 619/621/619/621 - 1240/1240/1240/1240

* During non-interlace mode, an equalization pulse is displayed only on the first half of a full line while a serration
pulse is displayed only on the second half of full line.
** With the exception of ACV, all the counts are in half lines. ACV is measured in full lines.

4.1.1.3 M-PAL Vertical Timing

Symbol Description M-PAL Non-interlace M- Debug Mode
PAL

EQU* Equalization pulse 6 6 6

ACV** Active video 241 241 241

PRB (odd/even) Preblanking 24/25 24/24 24/25

PSB (odd/even) Postblanking 1/0 2/2 1/0

BS1/2/3/4 Color burst starts 16/15/14/13 16/14/16/14 -

BE1/2/3/4 Color burst ends 518/517/516/519 518/520/518/520 -

* During non-interlace mode, an equalization pulse is displayed only on the first half of a full line while a serration
pulse is displayed only on the second half of full line.
** With the exception of ACV, all the counts are in half lines. ACV is measured in full lines.

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4.1.2 Horizontal Timing

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 VI Specification v 2.2

Symbol Description NTSC PAL M-PAL

HLW Half line width 429 432 429

HSY H sync width 64 64 64

HCS Color burst start 71 75 78

HCE Color burst end 105 106 112

HBE Horizontal blank end 162* 172* 162*

HBS Horizontal blank start 373* 380* 373*

* To center a 640-pixel line on the screen. For a line of different width, adjust HBE and increase HBS
symmetrically.

4.1.3 NTSC Interlace Mode

The above diagram only shows the first two fields of a 4-field NTSC signal. Since VI doesn’t distinguish burst phase,
the last two fields are the same as the first two fields.

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 VI Specification v 2.2

4.1.4 NTSC Non-Interlace Mode

In non-interlace mode, only the odd fields are displayed. The field rate is slightly lower than 60 fps as there are 263
lines per field instead of 262.5.

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 VI Specification v 2.2

4.1.5 PAL Interlace Mode

The above diagram only shows the first four fields of a 8-field PAL signal. Since VI doesn’t distinguish burst
phase, the last four fields are the same as the first four fields.

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4.1.6 PAL Non-Interlace Mode

In non-interlace mode, only the odd fields are displayed. The field rate is slight lower than 50 fps as there are 313 lines
per field instead of 312.5 lines.

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 VI Specification v 2.2

4.1.7 M-PAL Interlace Mode

With the exception of the burst flag, MPAL has timing similar to NTSC. The above diagram shows the first four fields
of a 8-field M-PAL signal. Since VI doesn’t distinguish burst phase, the last four fields are similar to the first four
fields.

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 VI Specification v 2.2

4.1.8 M-PAL Non-Interlace Mode

In non-interlace mode, only the odd fields are displayed. The field rate is slightly lower than 60 fps as there are 263
lines per field instead of 262.5.

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 VI Specification v 2.2

4.1.9 525 line progressive mode (480p)

This mode is for displaying progressively on a LCD monitor. It can be mmed to have the same frame and line rates
as NTSC (525 lines) or PAL (625 lines).

4.1.10 625 line progressive mode (480p)

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 VI Specification v 2.2

4.2 Timing Generator

The heart of VI is the timing generator. It is responsible for generating video timing, control signals, and interrupts.
Basically it consists of two counters: a vertical line counter and a horizontal pixel counter. Once enabled, they run
continuously at the pixel clock rate (27 MHz). Their outputs are decoded by a programmable decoder. The decoder
operates in four modes: NTSC, PAL, M-PAL, and a debug mode. The debug mode is used for testing and simulation
only. It reduces simulation time by using a smaller display size.

4.3 Address Generation

VI generates the address required to access pixel data from the external frame buffer. It supports various addressing
features: programmable picture size, windowing, and pixel resolution pan and scan.

4.4 Horizontal Scaling

VI supports horizontal scaling such that a smaller frame buffer can be stretched horizontally to the desired display
size. This is achieved by using a 6-tap resampling filter. Each filter tap has eight phases and a zero tap is added to have
a total of 49 taps. An output pixel is sampled to an 1/256 sub-pixel grid and is rounded to the nearest 1/8 sub-pixel. In
another word, a scan line is up sampled eight times before it is being down sampled to the target frequency.

The Y, Cr, and Cb components are buffered in three separate shift registers. Each register is responsible to replicate
the first and last pixels for filtering at the boundaries. To ease implementation, Cb and Cr pixels are averaged to 4:4:4
before filtering. This prevents chroma words from reading ahead of luma words. It also allows luma and chroma to
share the same control logic.
The new sampling position is controlled by an internal stepper. The stepper is incremented by a step size every output
pixel. The lowest eight bits of the stepper are rounded to three bits for determining the phase of the filter. Only one bit
to the left of the binary point is kept. If that bit is toggled, a new pixel is shifted into the pixel registers. The step size
of the stepper is determined by:

step_size = floor (256 * destination_size/source_size) / 256

The following is a diagram showing the shifters and the filter datapath. As the video clock rate is twice the pixel rate
(27 vs 13.5), the datapath is time shared between the three components. The datapath consists of six multipliers, an
adder, and a set of lookup table.

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The step size and the filter coefficients are set up through the VI’s register interface. The filter can be programmed to
have different cutoff frequency, pass band ripple, and stop band attenuation. As the filter is symmetrical, only half of it
is programmed. To conserve hardware in the filter, the filter coefficients are “enveloped”: The center 16 coefficients
are in the range [0, 2.0). The outter 32 coefficients are in the range [-0.125, 0.125). To achieve 8 times up sampling, it
is equivalent to design a 0.5Hz low pass filter at 8Hz sampling rate. A typical window sinc filter is shown in the
following diagrams.

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 VI Specification v 2.2

4.5 3D LCD Output

VI can support a 3D LCD by merging two frame buffer images (left and right) into a single stream of video. The
output interleaves between the left and right pictures every two pixels. A timing diagram is shown below:

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4.6 Gun Trigger Control

The gun trigger control in VI supports three sampling modes: one-field (gun triggeris sampled for one field), two-field
(gun trigger is sampled for two fields), and continuous.
In one/two-field mode, the detection mechanism consists of the following sequence of events:

Latch enable (LE0/1) in the display configuration register is programmed.

A new field occurs and updates the double buffered latch enable field. Trigger detection is turned on.
If a trigger occurs within the specified duration, the display counters are latched into the display latch register.
The latch enable control resets itself to the disable state when a trigger is detected or at the end of the specified
duration.

In continuous mode, the trigger is sampled continuously until it is disabled.

The first gun trigger in a field latches the value of the display counters. Gun triggers occur in the remaining of the field
are ignored.

4.7 Test Mode

The test mode is used for system-bring-up and debugging. It replaces the regular video output with a CCIR656
interface. As a result, a wide range of video encoder can be used.

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5 VI Registers
The following is a list of VI’s registers. Each register is 32bits. It is programmed by writing to the upper and lower 16-
bit words separately. The fourth column in each table shows the power-up reset values.

5.1 Display Configuration Register (R/W)

This register set ups and enables VI. It is in general a good idea to reset VI before enabling it. This resets the states
into some known values.
ENB 0 This bit enables the video timing generation and data request. 0
RST 1 This bit clears all data request and puts VI into its idle state. 0
NIN 2 To select interlace or non-interlace mode. NIN=0: interlace, NIN=1: non-interlace. In 0
non-interlace mode, the top field is drawn at field rate while the bottom field is not
displayed.
DLR 3 This bit select the 3D display mode. 0
LE0 5:4 Gun trigger mode. It enables the Display Latch Register 0. When the mode is 1 or 2, 0
it will clear itself (off) automatically when a gun trigger is detected or at time out.
This field is double buffered.
0 off
1 on for 1 field
2 on for 2 fields
3 always on
LE1 7:6 To enable Display Latch Register 1. See the description of LE0. 0
FMT 9:8 Indicates current video format: 0
0 NTSC
1 PAL
2 MPAL
3 Debug (CCIR656)

5.2 Horizontal Timing 0 Register (R/W)

This register setups the horizontal timing.
HLW 9:0 Half line width. -
HCE 22:16 Horizontal sync start to color burst end. -
HCS 30:24 Horizontal sync start to color burst start. -

5.3 Horizontal Timing 1 Register (R/W)

This register setups the horizontal timing.
HSY 6:0 Horizontal sync width. -
HBE 16:7 Horizontal sync start to horizontal blanking end. -
HBS 26:17 Half line to horizontal blanking start. -

5.4 Vertical Timing Register (R/W)

This register setups the vertical timing. The value ACV is double buffered
EQU 3:0 Equalization pulse in half lines. -
ACV 13:4 Active video in full lines. -

5.5 Odd Field Vertical Timing Register (R/W)

This register sets up the pre-blanking and post-blanking intervals of odd fields. The values PRB and PSB are double
buffered.
PRB 9:0 Pre-blanking in half lines. -

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PSB 25:16 Post-blanking in half lines. -

5.6 Even Field Vertical Timing Register (R/W)

This register setups the pre-blanking and post-blanking intervals of even fields. The values PRB and PSB are double
buffered.
PRB 9:0 Pre-blanking in half lines. -
PSB 25:16 Post-blanking in half lines. -

5.7 Odd Field Burst Blanking Interval Register (R/W)

This register sets up the burst blanking interval of odd fields.
BS1 4:0 Field 1 start to burst blanking start in half lines. -
BE1 15:5 Field 1 start to burst blanking end in half lines. -
BS3 20:16 Field 3 start to burst blanking start in half lines. -
BE3 31:21 Field 3 start to burst blanking end in half lines. -

5.8 Even Field Burst Blanking Interval Register (R/W)

This register setups the burst blanking interval of even fields.
BS2 4:0 Field 2 start to burst blanking start in half lines. -
BE2 15:5 Field 2 start to burst blanking end in half lines. -
BS4 20:16 Field 4 start to burst blanking start in half lines. -
BE4 31:21 Field 4 start to burst blanking end in half lines. -

5.9 Top Field Base Register L (R/W)

This register specifies the display origin of the top field of a picture in 2D display mode or for the left picture in 3D
display mode.
FBB 23:0 External memory address of the frame buffer image. -
XOF 27:24 Horizontal offset, in pixels, of the left most pixel within the first word of the fetched
picture.
HIGH 28 If High=0: -
Frame buffer addresses will be used as ADDR[23:0] (this limits the VI to use only
the lower 24MB of space)
If High=1:
Frame buffer addresses will be used as ADDR[25:5] (this allows the VI to use all
48MB of space)

5.10 Top Field Base Register R (R/W)

This register specifies the base address of the top field for the right picture in the 3D display mode. It is not used in 2D
display mode.
FBB 23:0 External memory address of the frame buffer image. -

5.11 Bottom Field Base Register L (R/W)

This register specifies the display origin of the bottom field of a picture in 2D display mode or for the left picture in
3D display mode.
FBB 23:0 External memory address of the frame buffer image. -

5.12 Bottom Field Base Register R (R/W)

This register specifies the base address of the bottom field for the right picture in the 3D display mode. It is not used in
2D display mode..

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FBB 23:0 External memory address of the frame buffer image. --

5.13 Picture Configuration Register (R/W)

This register specifies the picture configuration.
STD 7:0 Stride per line in words. -
WPL 14:8 Number of reads per line in words. -

5.14 Display Position Register (R)

This register contains the current raster position.
The Horizontal Count is in pixels and runs from 1 to # pixels per line. It is reset to 1 at the beginning of every line.
The Vertical Count is in lines (on a frame basis) and runs from 1 to # lines per frame. It is 1 at the beginning of pre-
equalization. Note: This is a frame line count, so for example: for NTSC vcount= 264 is the first (full) line in the 2 nd
field and vcount =525 is the last line in the frame (fields being numbered 1-4) . The vcount in non interlaced modes
still operates on a frame basis (1-525), even though there are no odd/even fields .
This counting scheme applies the Display Postion, Display Interrupt, and Display Latch registers.
HCT 10:0 Horizontal count. -
VCT 26:16 Vertical count. -

5.15 Display Interrupt Register 0 (R/W)

There are a total of four display interrupt registers (0-3). They are used to generate interrupts to the CPU at different
positions within a field. Each register has a separate enable bit. The interrupt is cleared by writing a zero to the status
flag (INT).
HCT 10:0 Horizontal count to generate interrupt. -
VCT 26:16 Vertical count to generate interrupt. -
ENB 28 Interrupt is enabled if this bit is set. 0
INT 31 Interrupt status. An “1” indicates that an interrupt is active. 0

5.16 Display Interrupt Register 1 (R/W)

See the description of Display Interrupt Register 0.

5.17 Display Interrupt Register 2 (R/W)

See the description of Display Interrupt Register 0.

5.18 Display Interrupt Register 3 (R/W)

See the description of Display Interrupt Register 0.

5.19 Display Latch Register 0 (R/W)

The Display Latch Register 0 latches the value of the Display Position Register at the rising edge of the gun0 trigger
signal. The trigger flag is set if a gun trigger is detected. Writing a zero to the register clear the trigger flag.
HCT 10:0 Horizontal count. 0
VCT 26:16 Vertical count. 0
TRG 31 Trigger flag. 0

5.20 Display Latch Register 1 (R/W)

See the description of Display Latch Register 0. This register is latched on the rising edge of the gun1 trigger signal.

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5.21 Ouput Polarity Register (R/W)

This register sets up the polarity of the out going control signals

I_POL 0 Inverts Interlace Flag 0

N_PO 1 Inverts NTSC Flag 0
L
K_PO 2 Inverts Burst Blank Flag 0
L
B_PO 3 Inverts Burst Flag 0
L
H_PO 4 Inverts HSyncb Flag 0
L
V_PO 5 Inverts VSyncb Flag 0
L
F_POL 6 Inverts Field Flag 0
C_PO 7 Inverts CSyncb Flag 0
L

5.22 Horizontal Scale Register (R/W)

This register sets up the step size of the horizontal stepper.
STP 8:0 Horizontal stepping size (U1.8). 256
HS_EN 12 Horizontal Scaler Enable 0

5.23 Scaling Width Register (R/W)

This register is the number of source pixels to be scaled. This is only used when the Horizontal Scaler is enabled. For
example, if the image is to be scaled from 320x240 to 640x240, 320 would be written into this register.
SRCWIDT 9:0 Horizontal stepping size 0
H

5.24 Border HBE (R/W)

This register (in conjunction with the border HBS) sets up a black border around the actual active pixels in debug
mode. This was done in order to accommodate certain encoders which only support 720 active pixels. The border HBE
and HBS can be programmed for 720 active pixels while the regular HBE and HBS can be programmed to the actual
active width. This allows the frame buffer to be of any width without having to manually set up a border in memory.
These registers will only take effect if enabled and in debug mode.
HBE656 9:0 Border Horizontal Blank End 0
BRDR_EN 15 Border Enable 0

5.25 Border HBS (R/W)

HBS656 9:0 Border Horizontal Blank Start 0

5.26 Filter Coefficient Table 0 (R/W)

This register sets up part of the low pass filter. Taps 0 to 9 are in the range [0.0, 2.0).
T0 9:0 Tap 0 (U1.9). -
T1 19:10 Tap 1. -
T2 29:20 Tap 2. -

5.27 Filter Coefficient Table 1 (R/W)

This register sets up part of the low pass filter.

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T3 9:0 Tap 3. -
T4 19:10 Tap 4. -
T5 29:20 Tap 5. -

5.28 Filter Coefficient Table 2 (R/W)

This register sets up part of the low pass filter.
T6 9:0 Tap 6. -
T7 19:10 Tap 7. -
T8 29:20 Tap 8. -

5.29 Filter Coefficient Table 3 (R/W)

This register sets up part of the low pass filter. Taps 9 to tap 24 are in the range [-0.125, 0.125).
T9 7:0 Tap 9 (S-2.9). -
T10 15:8 Tap 10. -
T11 23:16 Tap 11. -
T12 31:24 Tap 12. -

5.30 Filter Coefficient Table 4 (R/W)

This register sets up part of the low pass filter.
T13 7:0 Tap 13. -
T14 15:8 Tap 14. -
T15 23:16 Tap 15. -
T16 31:24 Tap 16. -

5.31 Filter Coefficient Table 5 (R/W)

This register sets up part of the low pass filter.
T17 7:0 Tap 17. -
T18 15:8 Tap 18. -
T19 23:16 Tap 19. -
T20 31:24 Tap 20. -

5.32 Filter Coefficient Table 6 (R/W)

This register sets up part of the low pass filter.
T21 7:0 Tap 21. -
T22 15:8 Tap 22. -
T23 23:16 Tap 23. -
T24 31:24 Hardwired to zero. -

5.33 VI Clock Select Register (R/W)

This register selects whether the VI will receive a 27 Mhz or a 54 Mhz clock. The 54 Mhz clock is used only with the
progressive display modes.
VICLKSEL 1 0 - 27 Mhz video clk 0
1 - 54 Mhz video clk

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5.34 VI DTV Status Register (R)

This register allows software to read the status of two I/O pins.
VISEL 2 TBD -

* We have to make sure there is enough time to program all the double buffered registers after the active display and
before the beginning of a back porch. There is about six display lines worth of time (40 usec).

5.35 Programming Example

The following diagram shows an interface field being fetched from a frame. Each memory word has 16 pixels (256
bits). All variables are in pixels with the exception of the picture origin and picture base, which are in words.
word_per_line = (picture_width + 15) / 16;

FBB = picture_origin + x_offset/16 + y_offset * word_per_line; // picture base

STD = 2 * word_per_line; // stride
XOF = x_offset % 16; // x offset within a word
WPL = (XOF + display_width + 15) / 16; // number of read per line

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6 Test Plan
6.1 Environment
Dolphin’s DV test environment is used for testing VI. Simpler tests such as display timing can be tested by using stubs
of processor interface and memory controller. Complicated tests such as gun trigger control should use live blocks
instead. Output pixels are checked by comparing against a C model. Display timing such as sync and blanking are
verified by using a CCIR656 model or a Rohm encoder model. Before a real API is available, a tiny API similar to the
one used in ArtX1 DU (du_test) verification can be used to generate all the register setup.

6.2 Tests
6.2.1 Display Format Test
All the display standards supported by VI are tested. The aim is to verify the range of the registers and counters, and
the coverage of the state machines. Each format is tested twice: Once in the debug mode and another time in
Nintendo’s encoder mode. A debug mode trace file will be checked by our CCIR656 encoder model while a Nintendo
mode trace file will be sent to Nintendo for verification (we are unable to obtain Rohm’s encoder model).

Format Refresh Active Active Scan

Rate Width Height Type

NTSC 50 640 240 I

PAL 60 288 I

M-PAL 50 240 I

6.2.2 Display Position Test

The screen position of the active region will be adjusted in both x and y directions. This is achieved by changing the
horizontal and vertical blanking intervals, respectively. In order to reduce simulation time, the test is divided into two
passes: The first pass uses a standard PAL width but a short height to test various x starting positions. The second pass
uses a standard PAL height but a narrow width to test various y starting positions. Special cases where an active
picture starts at an even pixel position or an active picture ends at an odd pixel position should be included.

6.2.3 Display Dimension Test

Horizontal and vertical blanking are adjusted such that different display sizes are tested.An approach similar to the last
time can be used to reduce simulation time. Horizontal display sizes from 480 to 720 pixels and vertical display sizes
less than 240 lines per field should be tested. In addition, special cases such as an odd picture width with even and odd
starting positions should be included.

6.2.4 Address Generator Test

This test verifies the address generation hardware inside VI. The following parameters are exercised: word per line, x
offset, and picture stride. The test should cover frame and field access, per pixel panning and windowing of frame
buffer, and even/odd number of words per line. Part of this test can be combined with other tests in order to reduce the
number of different simulations.

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6.2.5 Horizontal Scaler Test

This test verifies the horizontal scaler. The correctness of the datapath is checked against a C model. The visual
quality of the pictures produced is checked by human inspection. A number of pictures are selected for the test. They
include video test patterns, graphics screen shots, live images, and computer generated pictures.

Picture Source Display Height To Test

Width Width

random 640 720 480 Datapath correctness.

black 64 512 1 Clamping at 0.

gray 64 512 1 Uniform gain across filter phases.

white 64 512 1 Clamping at 1.

color bars 64 512 1 Purity of different colors.

color ramp 16 512 1 Rounding in stepper.

multiburst fcc 480 640 1 Filter gain at various frequencies.

7.5MHz sweep 480 640 1 Filter frequency response.

modulated 10 step 480 640 1 Display chroma levels at increments of 10%.

test pattern 640 720 480 Visual quality.

graphics/image 320 640 480 Visual quality.

graphics/image 384 640 480 Visual quality.

graphics/image 512 640 480 Visual quality

graphics/image 640 720 480 Visual quality.

6.2.6 3D Display Test

Tests 5.2.1 to 5.2.5 can be reused for testing the 3D display mode. A source picture should be splitted into its left and
right buffers before running the simulation. The output picture should look similar to the result from the original test
(the color may be slightly off if filtering is used).

6.2.7 Display Interrupt Test

Display interrupt is tested. It is set up by the four display interrupt registers. Interrupt timing is checked by monitoring
the interrupt signal. Clearing of an interrupt should also be tested.

6.2.8 Gun Trigger Test

All three gun trigger modes are tested on both gun trigger inputs. Trigger time is compared against the display position
latched into each display latch register.

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7 Timing for VI/EN interface

The following are the timing requirements for the VI/Encoder interface

7.1 Timing Chart for Video Interface signals

Timing Chart at 27 Mhz

Timing Chart at 54 Mhz

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7.2 AC Characteristics for Video Interface signals

Timing Chart at 27 Mhz

Timing Chart at 54 Mhz

(Load is 55pF.)
Symbol Parameter MIN MAX

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tCK27toD1 Delay time from rising of VICLK27 to invalid 0ns

DATA
tCK27toD2 Delay time from rising of VICLK27 to valid 13ns
DATA
tCK54toD1 Delay time from rising of VICLK54 to invalid 0ns
DATA
tCK54toD2 Delay time from rising of VICLK54 to valid ?ns
DATA

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