VLSI Circuits and Design I

MOS Device Scaling & CMOS Enhancement process

 MOS Device Scaling
Parameter Constant Field Constant voltage
Scaling (S>1) scaling (S>1)

Length: L 1/S 1/S

Width: W 1/S 1/S
Gate oxide thickness: tox 1/S 1/S
Supply voltage: VDD 1/S 1
Threshold voltage: Vtn, Vtp 1/S 1
Substrate doping: N S S
Device Characteristics
Current per device W  ox 1/S S
I  . .(V −V )2
ds
L tox DD t
Cg = ox WL
Gate Capacitance 1/S 1/S
tox
Transistor on resistance Rtr (VDS / I DS ) 1 1/S
Intrinsic gate delay  = Cg V / I avg = Rtr Cg 1/S 1/S2
Switching energy per gate E=CVDD2 1/S3 1/S
Power dissipation per gate P=IV 1/S2 S
Power delay product P 1//S3 1/S
Area/gate A= WL 1/S2 1/S2
Power dissipation density P/A 1 S3
Clock frequency f=1/ S S2

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 MOS Device Scaling (Cont.)
• The decrease in I may cause a decrease in speed.
• The decrease in C will compensate the decrease in I. Speed will not be affected that
much.
• Total energy dissipation: E=C(VDD)^2. Half dissipated in PMOS in charging and
half dissipated in NMOS in discharging. E~1/S3. If s=2 , E decreases by (1/8). It
is a huge benefit.
• Power-delay product ~ 1/S3. A great advantage in power dissipation as well.
• Area ~ 1/S2. (advantage)
• Power dissipation density — 1 (No change)
• Frequency can be increased — invention of high speed processor
• Problem: Voltage (Vdd) can not be reduced further. It creates problem in noise
margin.
 MOS Device Scaling (Cont.)
Constant Voltage Scaling ( Vdd constant, but the electric field is not )
Parameters Constant field scaling Constant voltage scaling

Switching energy per gate 1/S3​ 1/S​

Power dissipation per gate P=IV​ 1/S2​ S​

Power delay product 1/S3​ 1/S​

Area/gate 1/S2​ 1/S2​
Power dissipation density 1​ S3​

Current per device​ 1/S​ S​

S2
Clock frequency S
f=1/
Which one is the winning design ?
 Adverse Effect of Device Scaling
Channel length modulation
Velocity saturation and mobility degradation
Drain-Induced Barrier Lowering (DIBL)
Impact ionization
Hot Carrier Injection (HCI)
Surface scattering

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 Channel length modulation

1
I ds = ncox W (v gs − vt ) 2 (1 + Vds )
2 L

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 Hot Carrier Injection

n+ n+
Channel
p- Depletion layer

• Thickness of the oxide layer reduces due to scaling

• So, tunneling may occur through the oxide.
• Gate current (leakage) becomes nonzero.

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Technological Innovations To Keep Scaling Alive
Self-Aligned Gate MOSFET
Ion Implantation as Enabler of CMOS Scaling
Silicide and Salicide contact and Metal layer
Ultra Shallow Junction Formation. (USJ)
Apply Low-k interlayer dielectric
Use of Cu interconnect M3

C23
Via23
C22b C22a
M2  ox A
C12 =
tox
Insulator C12 tox Via12
(oxide)
Metal Line 1
M1

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 Self-Aligned Gate MOSFET
• At the very beginning, Aluminum was used as the gate metal.
• So, to avoid melting Aluminum was deposited after the creation of source
and drain.
• But later deposition of Aluminum causes the displacement of gate.
• To solve this problem, 'L' was kept too large, so that the displacement does
not cause malfunction, but it imposes a constraint to further scaling
• Then comes Polysilicon.

• Order of Fab. : Substrate > Oxide > Polysilicon > Deposition of Source
and Drain by masking > doping by diffusion/ion implantation
• So, dopant atoms will remain within the S-D region and will not come
under the poly / gate.
• Thus, Source and Drain automatically get aligned with the gate.
Ion Implantation as Enabler of CMOS Scaling
• Doping: Diffusion and Ion implantation.
• For doping, Activation of dopant atoms is required, which is done by Annealing.
Process of Out diffusion
G G
S D S D

Before Doping and Annealing After Doping (Diffusion)

G
S D

After Annealing
 Ion Implantation as Enabler of CMOS Scaling

• For, Ion implantation, out diffusion does not occur.

• L does not decrease, due to out diffusion.
• So, further scaling is possible, and Moore's law is
still valid.
Silicide and Salicide contact and Metal layer

Contact Resistance is very much high

Al Al
R (contact) Drain current Speed
S D
Severe in short devices

Contact Resistance reduces due to the

formation of Silicide

Al Al
W / Pt W / Pt Pt + Si = Platinum Silicide
S D
 Apply Low-k interlayer dielectric
Material K
Material value
Classification

Inorganic Fluorinated glass 2.8

(SiOF)
Si-O- 2.0
C polymers
(e.g
Inorganic/Organic MSQ)
Hybrid Poly Aylene Ether 2.6
(PAE)
Polymides / 2.9 /
Flourinated 2.3
B-stage Polymers 2.6
Amorphous C 2.0
PTFE (Teflon) 1.9
Porous MSQ 1.8
Porous Porous PAE 1.8
• To reduce RC delay, R and C is to be reduced. Porous SiO2 1.1
Air gaps / bridges 1.0
• R can be reduced by using Silicide.
• To reduce C, t can be increased or € (epsilon) can be decreased.
• But, t can not be increased due to scaling.
• So, use low k dielectrics in between metal layers
Use of Cu interconnect
Leakage current
 Reduce Leakage: High-k gate dielectric

SiO2  r = 3.9 Same

Capacitance

Higher thickness àReduced gate leakage

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Technological Innovations To Keep Scaling Alive
Mobility Enhancement by Strain

• Mobility of electron increases

due to compressive stress.
• It results in increment in drain
current
• That increases the speed

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 Double Gate, Triple Gate and GAA FET

• Multiple gate increases the current driving capabilities

• Current control becomes better
• I (off) reduces

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Ultra Shallow Junction Formation (USJ)
 Device Isolation

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 Device Isolation

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 Physical Limits

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 Scaling

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 New Structures

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 New Structures

Magnetic Tunnel Junction

Device (MTJ)

Memristor Device

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 Interconnect Scaling
Local interconnect and global interconnect

Local Interconnect
Number of Interconnect, n

Wsp Wint
Global Interconnect Hint

lloc

tox

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Interconnect length lint/Dc
Local interconnect scaling dimension

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 Local Interconnect Scaling
Parameter Ideal Quasi Constant-
scaling ideal R scaling
scaling
Lateral: Interconnect Width (Wint) 1/S 1/S 1/S
Lateral: Interconnect Separation (Wsp) 1/S 1/S 1/S
Vertical: Interconnect Thickness (Hint) 1/S 1/S 1/S
Vertical: Insulator Thickness (tox) 1/S 1/S 1/S
Local interconnect length : lloc 1/S 1/S 1/S
Local Interconnect Characteristics
Resistance/Unit length: Rint=l/A,
S2 S3/2 S
Rint / l =  / A = int / (W intH int)
Local Resistance, R int = int  (lloc / Wint H int ) S S 1
Capacitance to substrate per unit length
Cint = ox (A / tox ) = ox (Wintlloc ) / tox C int / lloc = ox (Wint / tox ) 1 1/S 1

Capacitance to substrate Cint =  ox (Wintlloc / tox ) 1/S 1/S3/2 1/S

RC delay per unit length (46) Rint Cint
 S2 S S
l l
RC delay(local interconnect RC dealy) = Rint  Cint 1 1/S 1/S

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 Global Interconnect Scaling

Parameter Ideal Const Constant-

scaling Dimen Delay
1 Lateral: Interconnect Width (Wint) 1/S 1 SC
2 Lateral: Interconnect Separation (Wsp) 1/S 1 SC
3 Vertical: Interconnect Thickness (Hint) 1/S 1 SC
4 Vertical: Insulator Thickness (tox) 1/S 1 SC
5 Global interconnect length : lglob SC SC SC
Global Interconnect Performance
6 Resistance (Rint) S2 SC SC 1/SC
7 Capacitance (Cint) SC SC SC
8 RC delay S2 SC2 SC2 1

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 Global Interconnect Scaling

Interconnect delay and gate delay compared with

respect to different technology generations.

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 Interconnects

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 Interconnects

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 Global Interconnect Scaling

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 New Inteconnects

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 Summary

Feature size

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