EEE, Amrita School of Engineering, Bangalore

Simulation Of Phase Lock Loop (PLL) for single phase

grid connected inverter
Amrita Vishwa Vidyapeetham

Amal Dev S

Jan 07, 2024

1|Page
 EEE, Amrita School of Engineering, Bangalore

Contents
List of figures…………………………………………………………………………………… 3
List of Table..……………………………………………………………………………………. 4
Chapter 1 INTRODUCTION………………………………………………………………….. 7
1.1 Phase Loop Lock……………………………………………………………. 7
1.1.1 Structure and Functions of PLL……………………………………. 8
1.1.2 Variations of PLL ………………………………………………….. 8
1.1.2.1 Analog or linear PLL(APLL)…………………………….. 8
1.1.2.2 Digital PLL (DPLL)……………………………………… 8
1.1.2.3 All digital PLL (ADPLL)………………………………… 8
1.1.2.4 Neuronal PLL (NPLL)…………………………………… 8
1.1.2.5 Software PLL (SPLL)……………………………………. 8
1.2 Grid Connected inverter systems…………………………………………… 9
1.2.1 Current control of Grid Connected inverter systems………………... 10
Chapter 2 DESIGN OF PHASE LOOP LOCK FOR 1-PHASE INVERTER……………… 11
2.1 Single Phase Alpha Beta signal generation using LPF Filter……………….. 11
2.2 Phase Lock Loop- Design for Single phase Inverter………………………... 12
Chapter 3 LITERATURE REVIEW………………………………………………………….. 13
3.1 Focus Search approach………………………………………………………. 13
Chapter 4 MATLAB SIMULATION OF PLL CIRCUIT FOR 1- PHASE INVERTER….. 14
4.1 Simulation Circuit of PLL Circuit for single phase Inverter………………… 14
Chapter 5 CONCLUSION……………………………………………………………………... 17

2|Page
 EEE, Amrita School of Engineering, Bangalore

List of Figures
1.1 PLL circuit 7

1.2 Grid-tied inverter system 9

1.3 Current feed to Grid 10

1.4 Reference signal for Active and reactive current control 10

2.1 2 stage LPF Filter for α, β generation 11

2.2 PLL Block for single phase inverter current controller 12

4.1 Simulation circuit for PLL Block 14

4.2 V beta, V alpha with 90 deg Phase shift 14

4.3 Vd and Vq Plot 15

4.4 16
Sinwt , costwt and Vbeta Plot

3|Page
 EEE, Amrita School of Engineering, Bangalore

List of Tables
3.1 literature review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4|Page
 EEE, Amrita School of Engineering, Bangalore

ABSTRACT

In grid connected applications the synchronization of output signals of the converters to be

connected with grid parameters - frequency and phase is of great importance. Different methods
based on Fourier transforms, zero-crossing detection, Kalman filters, phase-locked loops (PLL) and
others are used for this synchronization. This paper presents a new PLL for synchronization of the
output current of single-phase grid connected inverters with the utility grid voltage. It is based on
trigonometric transformations - sine and cosine functions in a phase detector block. The proposed
method’s simplicity and efficiency are proved by means of computer simulations and experimental
analysis. The practical realization of the PLL is based on analog and digital programmable devices.
Simulation and experimental results show good agreement with the results obtained by the
theoretical analysis. Advantage of the proposed PLL is its insensibility to changes of the amplitude
of the input signal after the synchronization has been achieved with its frequency and phase.

5|Page
 EEE, Amrita School of Engineering, Bangalore

PREFACE

In Project described about the Simulation of Phase lock loop with LPF Filter and synchronously
rotating frame with PI controller for Lock the reference signal with input signal to export active and
reactive current into the grid.

The chapter presented in report about the concept of PLL for single phase grid connected inverter
in following chapter
1. Introduction
2. Design of PLL for Single phase grid connected inverter
3. Simulation of PLL for single phase grid connected inverter

6|Page
 EEE, Amrita School of Engineering, Bangalore

Chapter 1
INTRODUCTION
1.1 Phase loop Lock (PLL)
A phase-locked loop (PLL) is a control system that produces an output signal whose phase is
proportional to the phase of an input signal. There are various types, the simplest being an electrical
circuit with a variable frequency oscillator and a phase detector in a feedback loop. An applied voltage
controls the frequency and phase of the oscillator correspondingly, giving rise to the name voltage-
controlled oscillator (VCO). The oscillator creates a periodic signal with a certain frequency, and the
phase detector compares the phase of that signal to the phase of the input periodic signal to adjust the
oscillator such that the phases match.

Keeping the input and output phase in lockstep involves keeping the input and output frequencies the
same a result, in addition to synchronizing signals, a phase-locked loop may follow an input frequency
or create a frequency that is a multiple of that input frequency. These features are used to synchronize
computer clocks, demodulate signals, and synthesize frequencies.

Phase-locked loops are used extensively in radio, telecommunications, computers, and other electronic
applications. They can be used to demodulate a signal, recover a signal from a noisy communication
channel, produce a stable frequency that is multiples of the input frequency (frequency synthesis), or
distribute precisely scheduled clock pulses in digital logic circuits like microprocessors. Since a single
integrated circuit can now supply a complete phase-locked-loop building block, the approach is
commonly utilized in current electronic devices, with output frequencies starting at a fraction of a hertz
up to many gigahertz. They are also employed in grid-tied inverters, which are electronic power
converters that integrate DC renewable resources and storage devices like photovoltaics and batteries
into the power grid.

Figure-1.1- PLL circuit

7|Page
 EEE, Amrita School of Engineering, Bangalore

1.1.1 Structure and Function of Phase Lock Loop

Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both
implementations use the same basic structure. Analog PLL circuits include four basic elements:

• Phase detector
• Low-pass filter
• Voltage controlled oscillator
• Feedback path, which may include a frequency divider

1.1.2 Variations
There are several variations of PLLs. Some terms that are used are "analog phase-locked loop"
(APLL), also referred to as a linear phase-locked loop" (LPLL), "digital phase-locked loop"
(DPLL), "all digital phase-locked loop" (ADPLL), and "software phase-locked loop" (SPLL)

1.1.2.1 Analog or linear PLL (APLL)

Phase detector is an analog multiplier. Loop filter is active or passive. Uses a voltage-controlled
oscillator (VCO). APLL is said to be a type II if its loop filter has transfer function with exactly
one pole at the origin (see also Egan's conjecture on the pull-in range of type II APLL)

1.1.2.1 Digital PLL (DPLL)

An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency
detector). May have digital divider in the loop

1.1.2.2 All digital PLL (ADPLL)

Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO)

1.1.2.3 Neuronal PLL (NPLL)

Phase detector is implemented by neuronal non-linearity, oscillator by rate-controlled oscillating

neurons

1.1.2.4 Software PLL (SPLL)

Functional blocks are implemented by software rather than specialized hardware.

1.1.2.5 Charge-pump PLL (CP-PLL)

CP-PLL is a modification of phase-locked loops with phase-frequency detector and square

waveform signals. See also Gardner's conjecture on CP-PLL.

8|Page
 EEE, Amrita School of Engineering, Bangalore

1.2 Grid Connected inverter systems

Grid-tied inverters convert direct current (DC) electrical power into alternating current (AC) electricity
that may be injected into the electric utility company grid. The grid tie inverter (GTI) must match the
phase of the grid and keep the output voltage slightly higher than the grid voltage at all times. A high-
quality contemporary grid-tie inverter has a fixed unity power factor, which means the output voltage
and current are properly matched, and the phase angle is within 1° of the AC power grids. The inverter
has an inbuilt computer that detects the current AC grid waveform and outputs a voltage that
corresponds to the grid. However, delivering reactive electricity to the grid may be required to keep
the voltage in the local grid within the allowable limits. Otherwise, in a grid section with a significant
amount of electricity from renewable sources, voltage levels may climb excessively during periods of
strong output, such as around noon with solar panels.

Grid-tie inverters are also intended to immediately disengage from the grid if the utility grid fails. In
the United States, there is a NEC requirement that assures that, in the case of a blackout, the grid tie
inverter shuts off to protect the energy it transmits from hurting any line workers dispatched to repair
the electrical system.

A grid tie inverter, when properly constructed, allows a homeowner to use an alternative power
generating source such as solar or wind power without substantial rewiring or the need for batteries. If
the alternative power being generated is inadequate, the deficit is sourced from the electricity grid.

Figure : 1.2 – Grid-tied inverter system

9|Page
 EEE, Amrita School of Engineering, Bangalore

1.2.1 Current control of Grid Connected inverter

systems

A Grid tie inverter connected (1.2) to the grid requires a current controller to feeding the active and
reactive current into the grid based on the requirement

Figure-1.3 Current feed to Grid

A Grid to send an active current to grid inverter needed a reference signal in phase with input
Voltage, the reference voltage will be a unit signal (-1,1) and for send an active current to the
grid controller needed a reference signal 90 Deg out of phase with the input signal.

Figure : 1.4 – Reference signal for Active and reactive current control

10 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Chapter-2
Design of Phase Loop Lock for Single-phase
inverter

2.1 Single Phase Alpha Beta signal generation using LPF

Filter

A PLL circuit needed an α, β signal for the implementation of PLL, by using 2 stage Low Pass filter
can be achieved.

Fig 2.1 – 2 stage LPF Filter for α, β generation

Below is the transfer function

ωc =Corner Frequency

When a signal passed through 2 stage first order LPF Multiplied by 2 (Since output magnitude

11 | P a g e
 EEE, Amrita School of Engineering, Bangalore

of LPF is half of the original signal) and will get another signal which is 90 out of phase with
the input signal.

2.2 Phase Lock Loop- Design for Single phase Inverter

To implement PLL, first convert alpha-beta signals into α, β,0 to DQ0 Simulink Block. Then,
set up a control system at the Q output to find the error between Q and zero reference and set it
to zero. The error is then fed to the PI controller, which gives the angle information and
integrates it to get ωT. The ωT is then fed to the alpha-beta-to-DQ transformation block. The
PI controller ensures that the output angle ωT is always aligned with the input signal

Figure 2.2 – PLL Block for single phase inverter current controller

Cos(wt) will be used as Active Current reference and Sin(wt) will be used as Reactive current
reference.

12 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Chapter 3
Literature Review

3.1 Focus Search approach

The following search strategy has been used and the literature are still under the
review. So, the collection of data includes the following pattern: Identified journals
and conference papers like. IEEE (PWM, Power electronics), Springer, Elsevier. Range:
2017-2021 Founded conferences 4k, journals 2k related to research problem.

Sl No Tittle Publication Conventional Proposal

Comparative study of
single-phase phase-
locked loops for grid- PPLL ,OSG-PLL
1 connected inverters
IEEECSE Comparative study of all 3 PLL
,AF-PLL
under non-ideal grid
conditions
Active and reactive
power control of
single-phase inverter
Synchronous frame reference
2 with seamless transfer IEEE2018 PLL
between grid- model-PLL
connected and
islanded mode

Table 3.1 Literature Review

13 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Chapter 4

MATLAB Simulation of PLL Circuit for

Single phase inverter
By Using MATLAB Simulink software, assigned the PLL circuit for single phase grid connected
inverter

4.1 Simulation Circuit of PLL Circuit for single phase

Inverter
For generating a PLL circuit for an input signal (Sin wave) used 2 stage First order Low pass Filter
and Obtained V Alpha signal which 90 degree phase shift with original input signal (Vbeta)

Figure 4.1 – Simulation circuit for PLL Block

14 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Figure 4.2 – V beta, V alpha with 90 deg Phase shift

Figure 4.3 – Vd and Vq Plot

Obtained Zero Vq When Vq locked with input signal and at Zero Q Reference

15 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Figure 4.3 – Sinwt , costwt and Vbeta Plot

Final output got 2 reference signal Sinwt and Coswt in sink with input voltage signal

16 | P a g e
 EEE, Amrita School of Engineering, Bangalore

Chapter 4
Conclusion
In this report concluded that by using 2 Stage 1st order LPF and Alpha beta to DQ conversation
with a PI control can be used to generate a active and reactive current reference signal with a
phase lock loop for a single phase grid connected inverter, the output signal can be multiplied
with Sawtooth wave form to generate a PWM signal to turn the switch. By using digital signal
processing techniques provide the precise control and flexibility over the filter characteristics.

Since using the 2 Stage LPF filter could able generate a perfect sinusoidal wave as reference
signal as compared as other techniques.

The future work is focused on the application of this method for three-phase grid connected
inverters.

17 | P a g e
 EEE, Amrita School of Engineering, Bangalore

REFERENCES
1. Simulation of phase locked loop (PLL) for single phase grid connected inverter using
MTALAB.- https://www.youtube.com/watch?v=3Q-pIKNLvUE

2. A single phase photovoltaic inverter control for grid connected system

https://www.ias.ac.in/article/fulltext/sadh/041/01/0015-0030

3. PLL FOR SINGLE PHASE GRID CONNECTED INVERTERS - er (2013), pp. 56-77
© IAEME: www.iaeme.com/ijeet.asp

4. Phase Locked Loop – Wikipedia -https://en.wikipedia.org/wiki/Phase-locked_loop

18 | P a g e