Topics Covered in this file

Bus
Bus Architecture
Types of buses
Bus Architecture based NUMERICAL
System Bus Design
Bus and Memory Transfer
Multiplexer
Implementation of MUX and Logics Gates using Multiplexers

What Is Bus

 A bus is a set of electrical wires (lines) that connects the various hardware components of a
computer system.

 It works as a communication pathway through which information flows from one hardware
component to the other hardware component.

What Is System Bus?

A bus that connects major components (CPU, memory and I/O devices) of a computer system is
called as a System Bus.
 Why Do We Need Bus?

 A computer system is made of different components such as memory, ALU, registers etc.
 Each component should be able to communicate with other for proper execution of instructions
and information flow.
 If we try to implement a mesh topology among different components, it would be really
expensive.
 So, we use a common component to connect each necessary component i.e. BUS.

Components Of A System Bus- [Bus Types]

The system bus consists of three major components-

1. Data Bus
2. Address Bus
3. Control Bus

Bus Architecture Diagram

1) Data Bus-

 As the name suggests, data bus is used for transmitting the data / instruction from CPU to
memory/IO and vice-versa.
 It is bi-directional.
 Data Bus Width

 The width of a data bus refers to the number of bits (electrical wires) that the bus can
carry at a time.
 Each line carries 1 bit at a time. So, the number of lines in data bus determine how
many bits can be transferred parallely.
 The width of data bus is an important parameter because it determines how much data
can be transmitted at one time.
 The wider the bus width, faster would be the data flow on the data bus and thus better
would be the system performance.

Examples-
 A 32-bit bus has thirty-two (32) wires and thus can transmit 32 bits of data at a time.
 A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at a time.

2) Control Bus-

 As the name suggests, control bus is used to transfer the control and timing signals from one
component to the other component.
 The CPU uses control bus to communicate with the devices that are connected to the computer
system.
 The CPU transmits different types of control signals to the system components.
 It is bi-directional.

What Are Control & Timing Signals?

Control signals are generated in the control unit of CPU.

Timing signals are used to synchronize the memory and I/O operations with a CPU clock.

Typical control signals hold by control bus-

 Memory read – Data from memory address location to be placed on data bus.
 Memory write – Data from data bus to be placed on memory address location.
 I/O Read – Data from I/O address location to be placed on data bus.
 I/O Write – Data from data bus to be placed on I/O address location.
 Other control signals hold by control bus are interrupt, interrupt acknowledge, bus request, bus
grant and several others.
The type of action taking place on the system bus is indicated by these control signals.
Example-

When CPU wants to read or write data, it sends the memory read or memory write control signal
on the control bus to perform the memory read or write operation from the main memory.
Similarly, when the processor wants to read from an I/O device, it generates the I/O read signal.

3) Address Bus-

 As the name suggests, address bus is used to carry address from CPU to memory/IO devices.
 It is used to identify the particular location in memory.
 It carries the source or destination address of data i.e. where to store or from where to retrieve
the data.
 It is uni-directional.

Example-

When CPU wants to read or write data, it sends the memory read or memory write control signal
on the control bus to perform the memory read or write operation from the main memory and the
address of the memory location is sent on the address bus.
If CPU wants to read data stored at the memory location (address) 4, the CPU send the value 4 in
binary on the address bus.
 Address Bus Width

 The width of address bus determines the amount of physical memory

addressable by the processor.
 In other words, it determines the size of the memory that the computer can
use.
 The wider is the address bus, the more memory a computer will be able to
use.
 The addressing capacity of the system can be increased by adding more
address lines.

Examples-
16
 An address bus that consists of 16 wires can convey 2 (= 64K) different
addresses.
32
 An address bus that consists of 32 wires can convey 2 (= 4G) different
addresses.

PRACTICE PROBLEMS BASED ON SYSTEM BUS-

Problem-01:

Which of the following system bus is used to designate the source or destination of the data on the
bus itself?
1. Control bus
2. Data bus
3. Address bus
4. System bus

Solution-

The correct option is (C) Address bus.

 Address bus carries the source or destination address of data i.e. where to store or from where to
retrieve the data.

Problem-02:

The bus which is used to transfer data from main memory to peripheral device is-
1. Data bus
2. Input bus
3. DMA bus
4. Output bus

Solution-

The correct option is (A) Data bus.

Data bus carries data / instruction from CPU to memory/IO and vice-versa.

Problem-03:

How many memory locations a system with a 32-bit address bus can address?
1. 28
2. 216
3. 232
4. 264

Solution-

The correct option is (C) 232.

232 memory locations can be addressed by a 32-bit address bus.

Problem-04:

How many bits can be transmitted at a time using a bus with 32 data lines?
1. 8 bits
2. 16 bits
3. 32 bits
4. 1024 bits

Solution-

Each line carries one bit. So, a bus with 32 data lines can transmit 32 bits at a time.

Problem-05:

A microprocessor has a data bus with 64 lines and an address bus with 32 lines. The maximum
number of bits that can be stored in memory is-
1. 32 x 212
2. 32 x 264
3. 64 x 232
4. 64 x 264

Solution-

The correct option is (C) 64 x 232.

The amount of blocks that could be located is 232. Now, since data bus has 64 lines, so each block
is 64 bits. Thus, maximum number of bits stored in memory is 232 x 64 bits.

Problem-06:

The address bus with a ROM of size 1024 x 8 bits is-

1. 8 bits
2. 10 bits
3. 12 bits
4. 16 bits

Solution-

The correct option is (B) 10 bits.

 The size of the ROM is 1024 x 8 = 210 x 8. Here, 10 indicates the address bus and 8 indicates the
data bus width.

Problem-07:

The data bus width of a ROM of size 2048 x 8 bits is-

1. 8
2. 10
3. 12
4. 16

Solution-

The correct option is (A) 8.

The size of the ROM is 2048 x 8 = 211 x 8. Here, 11 indicates the address bus and 8 indicates the
data bus width.

System Bus Design

The electrically conducting path along which data is transmitted inside any digital electronic
device. A Computer bus consists of a set of parallel conductors, which may be conventional
wires, copper tracks on a PRINTED CIRCUIT BOARD, or microscopic aluminum trails on the
surface of a silicon chip. Each wire carries just one bit, so the number of wires determines the
most significant data WORD the bus can transmit: a bus with eight wires can carry only 8-bit
data words and hence defines the device as an 8-bit device.
 The bus is a communication channel.
 The characteristic of the bus is shared transmission media.
 The limitation of a bus is only one transmission at a time.
 A bus used to communicate between the major components of a computer is called a System
bus.
System bus contains 3 categories of lines used to provide the communication between the CPU,
memory and IO named as:
1. Address lines (AL)
2. Data lines (DL)
3. Control lines (CL)
1. Address Lines:
 Used to carry the address to memory and IO.
 Unidirectional.
 Based on the width of an address bus we can determine the capacity of a main memory
Example:
2. Data Lines:
 Used to carry the binary data between the CPU, memory and IO.
 Bidirectional.
 Based on the width of a data bus we can determine the word length of a CPU.
 Based on the word length we can determine the performance of a CPU.
Example:
3. Control Lines:

 Used to carry the control signals and timing signals

 Control signals indicate the type of operation.
 Timing Signals are used to synchronize the memory and IO operations with a CPU clock.
 Typical Control Lines may include Memory Read/Write, IO Read/Write, Bus Request/Grant,
etc.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be excessive
if separate lines are used between each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring information between registers
in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by the
bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with the help
of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1
and S2).

We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line common
bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the bus
lines to receive the content of register A since the outputs of this register are connected to the 0
data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.

The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits in
each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For
instance, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for
each line in the bus. Each multiplexer must have eight data input lines and three selection lines
to multiplex one significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are
signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a
high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of
time.

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated below.

o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]
 o The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).

Ques 7 What is a memory transfer? What are different registers associated for memory
transfer? Discuss.
Memory Transfer:
The transfer of information from a memory word to the outside environment is called a read
operation. The transfer of new information to be stored into the memory is called a write
operation.
Different Registers Associated for Memory Transfer:
The address register (AR) is used to select a memory address, and the data register (DR) is used to
send and receive data. Both these registers are connected to the internal bus.
DR← M[AR]: This is the read operation.
M[AR]<--R1: This is the write operation.

Multiplexers
A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information is
received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of
2N possible combinations of inputs. A multiplexer is also treated as Mux. Multiplexers are also
known as “Data n selector, parallel to serial convertor, many to one circuit, universal logic
circuit”

Multiplexers are mainly used to increase amount of the data that can be sent over the network
within certain amount of time and bandwidth.

2×1 Multiplexer:
Block Diagram of 2 x 1 Mux:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line S0,
one of these 2 inputs will be connected to the output. The block diagram and the truth table of the
2×1 multiplexer are given below.
 4×1 Multiplexer:

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the output. The block diagram and
the truth table of the 4×1 multiplexer are given below.
8 to 1 Multiplexer
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S

1.S3.A7
Logical circuit of the above expression is given below:

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected to the
output. The block diagram and the truth table of the 8×1 multiplexer are given below.

16 to 1 Multiplexer
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.S1.S2'.

S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+
A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

16×1 multiplexer using 8×1 and 2×1 multiplexer
a) Implementation of NOT gate using 2 : 1 Mux

We can analyze it
Y = x’.1 + x.0 = x’
It is NOT Gate using 2:1 MUX.
The implementation of NOT gate is done using “n” selection lines. It cannot be implemented
using “n-1” selection lines. Only NOT gate cannot be implemented using “n-1” selection lines.
b) Implementation of AND gate using 2 : 1 Mux

This implementation is done using “n-1” selection lines.

c) Implementation of OR gate using 2 : 1 Mux using “n-1” selection lines.

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First multiplexer
will act as NOT gate which will provide complemented input to the second multiplexer.
d) Implementation of NAND gate using 2 : 1 Mux
e) Implementation of NOR gate using 2 : 1 Mux

f) Implementation of EX-OR gate using 2 : 1 Mux

g) Implementation of EX-NOR gate using 2 : 1 Mux

 Implementation of Higher order MUX using lower order MUX
a) 4 : 1 MUX using 2 : 1 MUX
Three(3) 2 : 1 MUX are required to implement 4 : 1 MUX.

Similarly,
While 8 : 1 MUX require seven(7) 2 : 1 MUX, 16 : 1 MUX require fifteen(15) 2 :1 MUX, 64 : 1
MUX requires sixty three(63) 2 : 1 MUX.
Hence, we can draw a conclusion,
2n : 1 MUX requires (2^n – 1) 2 : 1 MUX.

b) 16 : 1 MUX using 4 : 1 MUX

In general, to implement B : 1 MUX using A : 1 MUX , one formula is used to implement the
same.
B / A = K1,
K1/ A = K2,
K2/ A = K3
………………
KN-1 / A = KN = 1 (till we obtain 1 count of MUX).
And then add all the numbers of MUXes = K1 + K2 + K3 + …. + KN.
For example : To implement 64 : 1 MUX using 4 : 1 MUX
Using the above formula, we can obtain the same.
64 / 4 = 16
16 / 4 = 4
4 / 4 = 1 (till we obtain 1 count of MUX)
Hence, total number of 4 : 1 MUX are required to implement 64 : 1 MUX = 16 + 4 + 1 = 21.
An example to implement a boolean function if minimal and don’t care terms are given
using MUX.
f ( A, B, C) = Σ ( 1, 2, 3, 5, 6 ) with don’t care (7) using 4 : 1 MUX using as
a) AB as select : Expanding the minterms to its boolean form and will see its 0 or 1 value in Cth
place so that they can be placed in that manner.

b) AC as select : Expanding the minterms to its boolean form and will see its 0 or 1 value in Bth
place so that they can be place in that manner.
c) BC as select : Expanding the minterms to its boolean form and will see its 0 or 1 value in
Ath place so that they can be place in that manner.
8 ×1 multiplexer using 4×1 and 2×1 multiplexer
We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1 multiplexer has 2
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of 8×1
multiplexer using 4×1 and 2×1 multiplexer is given below.

Decoder
The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for simplicity. The produced
2N-bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4-line decoder:

In the 2 to 4-line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these
four outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given
below.
Block Diagram:

Truth Table:

The logical expression of the term Y0, Y1, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there
is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and
A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one
of these four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are
given below.

Block Diagram:
Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

4 to 16-line Decoder

In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,…, Y16 and four inputs,
i.e., A0, A1, A2, and A3. The 3 to 16-line decoder can be constructed using either 2 to 4 decoder or
3 to 8 decoder. There is the following formula used to find the required number of lower-order
decoders.

Required number of lower order decoders=m2/m1

m1 is the number of outputs of lower order decoder.

m2 is the number of outputs of higher order decoder.

Here, m1 = 8 and m2 = 16. Substitute, these two values in the above formula.

Required number of 3to8 decoders= 16/8 = 2

Block Diagram:
Truth Table:

The logical expression of the term A0, A1, A2,…, A15 are as follows:

Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

Advantages of using Binary Decoders in Digital Logic:

1. Increased flexibility: Binary decoders provide a flexible way to select one of multiple outputs
based on a binary code, allowing for a wide range of applications.
2. Improved performance: By converting a serial code into a parallel set of outputs, binary
decoders can improve the performance of a digital system by reducing the amount of time
required to transmit information from a single input to multiple outputs.
3. Improved reliability: By reducing the number of lines required to transmit information from a
single input to multiple outputs, binary decoders can reduce the possibility of errors in the
transmission of information.
Application of Binary Decoder in Digital Logic:
1.Memory tending to: In computerized frameworks, paired decoders are generally used to
choose a particular memory area from a variety of memory areas. The location inputs are applied
to the double decoder, and the comparing memory area is chosen.
2.Control circuits: Parallel decoders are utilized in charge circuits to produce control signals for
various tasks. For instance, in a microchip, a double decoder is utilized to translate the guidance
opcode and produce control signals for the comparing activity.
3.Display drivers: In computerized frameworks that utilization show gadgets, for example,
Drove shows, parallel decoders are utilized to drive the presentation. The double data sources are
applied to the decoder, and the relating Drove is enlightened.
4.Address unraveling: Parallel decoders are utilized in address disentangling circuits to create
the chip select sign for a particular memory or fringe gadget.
5.Digital correspondence: Twofold decoders are utilized in advanced correspondence
frameworks to unravel the computerized information got over the correspondence channel.
6.Error rectification: Double decoders are utilized in mistake amendment circuits to recognize
and address blunders in computerized information.
References –
Here are a few books that you can refer to for further information on digital logic and binary
decoders:
1. “Digital Systems Design Using VHDL” by Charles H. Roth Jr. and Lizy Kurian John
2. “Digital Design and Computer Architecture” by David Harris and Sarah Harris
3. “Principles of Digital Design” by Daniel D. Gajski, Frank Vahid and Tony Givargis
4. “Digital Circuit Design: An Introduction” by Thomas L. Floyd and David Money Harris
5. “Digital Fundamentals” by Thomas L. Floyd

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line
decoder without using any other logic gates?
(A) 7
(B) 8
(C) 9
(D) 10

Answer: (C)
Explanation:
So total signals in=a, b, c, x, y, z i.e. 6
And total output =8*8=64
hence required decoders (from fig.) = 9 so ans is ( C) part.

This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Bus Arbitration”.

1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
View Answer
Answer: b
Explanation: The BUS arbitrator is used to allow a device to access the BUS based on certain
parameters.
2. The device which is allowed to initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
View Answer
Answer: a
Explanation: The device which is currently accessing the BUS is called as the BUS master.
3. ______ BUS arbitration approach uses the involvement of the processor.
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned
View Answer
Answer: a
Explanation: In this approach, the processor takes into account the various parameters and assigns
the BUS to that device.
4. The circuit used for the request line is a _________
a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
View Answer
Answer: c
Explanation: None.
5. The Centralised BUS arbitration is similar to ______ interrupt circuit.
a) Priority
b) Parallel
c) Single
d) Daisy chain
View Answer
Answer: d
Explanation: None.
6. When the processor receives the request from a device, it responds by sending _____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
View Answer
Answer: b
Explanation: The Grant signal is passed from one device to the other until the device that has
requested is found.
7. In Centralised Arbitration ______ is/are is the BUS master.
a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller
View Answer
Answer: d
Explanation: The BUS master is the one that decides which will get the BUS.
8. Once the BUS is granted to a device ___________
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
View Answer
Answer: a
Explanation: The BUS busy activated indicates that the BUS is already allocated to a device and is
being used.
9. The BUS busy line is made of ________
a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
View Answer
Answer: b
Explanation: None.
10. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
d) None of the mentioned
View Answer
Answer: b
Explanation: After the device completes the operation it releases the BUS and the processor takes
over it.
11. The BUS busy line is used __________
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indicate the BUS is already allocated
d) None of the mentioned
View Answer
Answer: c
Explanation: None.
12. Distributed arbitration makes use of ______
a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
View Answer
Answer: d
Explanation: The device uses a 4bit ID number and based on this the BUS is allocated.
13. In Distributed arbitration, the device requesting the BUS ______
a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the mentioned
View Answer
Answer: a
Explanation: None.
14. How is a device selected in Distributed arbitration?
a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned
View Answer
Answer: c
Explanation: The OR output of all the 4 lines is obtained and the device with the larger value is
assigned the BUS.
15. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device
gets the BUS based on the Distributed arbitration.
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned
View Answer
Answer: b
Explanation: The device Id’s of both the devices are passed on the lines and since the value of B is
greater after the Or operation it gets the BUS.
1. The primary function of the BUS is __________
a) To connect the various devices to the cpu
b) To provide a path for communication between the processor and other devices
c) To facilitate data transfer between various devices
d) All of the mentioned
View Answer
Answer: a
Explanation: The BUS is used to allow the passage of commands and data between cpu and
devices.
2. The classification of BUSes into synchronous and asynchronous is based on __________
a) The devices connected to them
b) The type of data transfer
c) The Timing of data transfers
d) None of the mentioned
View Answer
Answer: c
Explanation: The BUS is classified into different types for the convenience of use and depending
on the device.
3. The device which starts data transfer is called __________
a) Master
b) Transactor
c) Distributor
d) Initiator
View Answer
Answer: d
Explanation: The device which starts the data transfer is called an initiator.
4. The device which interacts with the initiator is __________
a) Slave
b) Master
c) Responder
d) Friend
View Answer
Answer: a
Explanation: The device which receives the commands from the initiator for data transfer.
5. In synchronous BUS, the devices get the timing signals from __________
a) Timing generator in the device
b) A common clock line
c) Timing signals are not used at all
d) None of the mentioned
View Answer
Answer: b
Explanation: The devices receive their timing signals from the clock line of the BUS.
6. The delays caused in the switching of the timing signals is due to __________
a) Memory access time
b) WMFC
c) Propagation delay
d) Processor delay
View Answer
Answer: c
Explanation: The time taken for the signal to reach the BUS from the device or the circuit accounts
for this delay.
7. The time for which the data is to be on the BUS is affected by __________
a) Propagation delay of the circuit
b) Setup time of the device
c) Memory access time
d) Propagation delay of the circuit & Setup time of the device
View Answer
Answer: d
Explanation: The time for which the data is held is larger than the time taken for propagation delay
and setup time.
8. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
b) False
View Answer
Answer: a
Explanation: None.
9. Which is fed into the BUS first by the initiator?
a) Data
b) Address
c) Commands or controls
d) Address, Commands or controls
View Answer
Answer: d
Explanation: None.
10. _____________ signal is used as an acknowledgement signal by the slave in Multiple cycle
transfers.
a) Ack signal
b) Slave ready signal
c) Master ready signal
d) Slave received signal
View Answer
Answer: b
Explanation: The slave once it receives the commands and address from the master strobes the
ready line indicating to the master that the commands are received.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Asynchronous BUS”.

1. The master indicates that the address is loaded onto the BUS, by activating _____ signal.
a) MSYN
b) SSYN
c) WMFC
d) INTR
View Answer
Answer: a
Explanation: The signal activated by the master in the asynchronous mode of transmission is used
to intimate the slave the required data is on the BUS.
2. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
b) False
View Answer
Answer: a
Explanation: The devices with variable speeds are connected using asynchronous BUS, as the
devices share a master-slave relationship.
3. The MSYN signal is initiated __________
a) Soon after the address and commands are loaded
b) Soon after the decoding of the address
c) After the slave gets the commands
d) None of the mentioned
View Answer
Answer: b
Explanation: This signal is activated by the master to tell the slave that the required commands are
on the BUS.
4. In IBM’s S360/370 systems _____ lines are used to select the I/O devices.
a) SCAN in and out
b) Connect
c) Search
d) Peripheral
View Answer
Answer: a
Explanation: The signal is used to scan and connect to input or output devices.
5. The meter in and out lines are used for __________
a) Monitoring the usage of devices
b) Monitoring the amount of data transferred
c) Measure the CPU usage
d) None of the mentioned
View Answer
Answer: a
Explanation: The line is used to monitor the usage of the device for a process.
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6. MRDC stands for _______
a) Memory Read Enable
b) Memory Ready Command
c) Memory Re-direct Command
d) None of the mentioned
View Answer
Answer: b
Explanation: The command is used to initiate a read from memory operation.
7. The BUS that allows I/O, memory and Processor to coexist is _______
a) Attributed BUS
b) Processor BUS
c) Backplane BUS
d) External BUS
View Answer
Answer: c
Explanation: None.
8. The transmission on the asynchronous BUS is also called _____
a) Switch mode transmission
b) Variable transfer
c) Bulk transfer
d) Hand-Shake transmission
View Answer
Answer: d
Explanation: The asynchronous transmission is termed as Hand-Shake transfer because the master
intimates the slave after each step of the transfer.
9. Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.
a) True
b) False
View Answer
Answer: a
Explanation: This mode of transmission is suitable for multiple device situation as it supports
variable speed transfer.
10. The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
a) True
b) False
View Answer
Answer: b
Explanation: None.