Computer Structure & Funct Structure : way in which components relate to each other ¢ Function is the operation of individual components as part of the structure Basic Structure Basic function 1. processor A. Data processing 2. Main memory a) B. Data movement 3. Control unit Ut C. Control mechanism D. Data storage 4. V/O peripherals Facility 1.Central processing unit (CPU): forms data processing. A. Control unit: Controls operation of CPU and computer. B. Arithmetic and logic unit (ALU): Performs the computer’s data processing functions (add, sub, ..) C. Registers: Provides storage internal to the CPU. D. interconnection: mechanism for communication among the control unit, ALU, and registers. 2.Main memory: Stores data. 3.UQO: move data between computer and external environment 4,System interconnection: provide communication method among CPU, main memory, and I/O by number of conducting wires to all sa TE eeCentral processing unit (CPU): fetches and executes instructions and consists of ALU, control unit, and registers called processor in a single ship Multi core computer structure: when multiple processors reside on single chip, where each processing unit is called core Core: individual processing unit on processor chip consisting of control unit, ALU, registers, and perhaps cache. A core equivalent to CPU on a single-CPU system in functionality. Other specialized processing units, such as one optimized for vector and matrix operations, are also referred to as cores. Processor: It is computer component interprets and executes instructions placed on physical piece of silicon if containing more than one called multiple cores. Multi core computer structure: cee motherboard contains slot COO or socket for processor chipPerformance calculations Example!: Consider the execution of a program with 2 million instructions on 400 MH processor, program consists of four major types ALU with 60 of instructions, Load with 18, memory reference 10 , and branch with 12 in which each has number of cycles respectively 1,2,8,4 find the performance Base Machine (Reg / Reg) Op Frea, (%Time) Cycles — cpi(i) AW 60 | (0.6) 1 1x.6=0.6 load 18 | (0.18) 2 2x0.18=.36 Store 10 | (0.1) 8 8x0.1=0.8 Branch 22 | (0.12) a 4x0.12=0.48 ape 100 | weight=1 YePl=2.24 DCPI= (1*0.6)+(2*0.18)+(8*0.1) +(4*0.12)=0.6+0.36+0.8+0.48=2.24 Performance= (400*10° )/( 2.24xg98)= 178 MIPS Detail Structure of IAS instruction architecture set ‘Two steps: Fetch Execute 1- PC to MAR and increment PC next instruction, Unless otherwise Aritimetic ogi wit | 2- Processor fetches instruction | to from memory to MBR 3- load Instruction to IR 4- CU interprets instruction and performs actions 5- data processed from memory _| ecuipment nT Man Memery 6- data processed to execute 7- operand store in memory or IOInterrupts + Mechanism by other modules (e.g. I/O) as emergency call * types of normal interrupts: 1. Program ,e.g. overflow, division by zero 2. Timer, internal processor timer or multi-tasking 3. VO, from I/O controller for service 4. Hardware failure, e.g. memory parity error «Processor checks interrupt signal, otherwise fetch next instruction + If interrupt pending and process the following: 1. Suspend execution of current program 2. Save context 3. Set PC to start address of interrupt handler routine 4. Process interrupt routine 5. Restore context and continue program BUS set of wires for communication pathway connecting two or more devices 32 bit separate single bit channels *There are a number of possible interconnection systems *Single BUS structures are most common [Unibus] *Multiple BUS [Control/Address/Data bus (PC)] “Bus Types *Dedicated: Separate data & address lines *Multiplexed: Shared lines for data and address “Bus Arbitration But problems of unibus is the propagation delay that uses “Arbitration method” to overcame delay 1. Centralised Arbitration ~ Single hardware device controlling bus access "Bus Controller and Arbiter . Distributed Arbitration ~ Each module may claim the busWrite ‘Memory Type Category Erasure ren Volatility aedemmercee Read-write | Electrically, byte- memory (RAND) Read Electrically: byte | yctricatly | Volatile ‘To: Dynamic and static ad Read-only Masks memory (ROM) Read-only | Not possible Programmable meee ROM (PROM) Erasable PROM ui (EPROM) wane Nonvolutile Electrically Electrically Erasable Read-mostly | Electrically, byte- PROM (EEPROM) memory al Flash memory ee DRAM =Dynamic RAM Dynamic RAM via Static RAM SRAM=Static RAM. 1 | Bits stored as charge in Bits stored as on/off switches capacitors with charges leakage | with no charges to leak 2 | Need refresh even when power | No refresh needed when power 3. | Essentially analogue Digital 4 | Simpler construction More complex construction. 5 | Smaller per bit Larger per bit 6 | Less expensive More expensive 7 |Slower Faster 8 | Main memory Cache 9 | DDRAM=increase data transfer SDRAM [stHow to measure Capacity of Main Memory * Capacity measured in bits, or Byte (8 bits), or word to be accessed + Total number of location per word = number of words per memory + words grouped into block to facilitate addressing. + Capacity= number of blocks “size of block per word “size of word Example 1_if the Main memory has 512 block number with each 512 word. If each word is 1 Byte (8 bit ), Find capacity of memory? Capacity=number of blocks per word* number of words*size of word*= = 512 block *512 word*8 bits word size= = (2?) x (2°)x (23) = 271-2. x 270=2 M bits = 28 *2!° bits= 256KB byte 23 K (2!0 3FF 512 blocks Mega 220 FFFFF Each Block= $12 ward= 2? B Giga 230 FFFFFF Address to block= 000 to 1FF = Tera 24 Address to memory=00000-3FFFF aera Example 1. What is the capacity and address size of main memory with word size 16 bits and each block 128 words, if the total number of blocks in the memory is 32 ? If address bus 28 bit find maximum capacity? CAPACITY=32block x128w x16 bit = 25x2’x 2+ =2!¢= K x 2° =64Kbit Address bus size = 5 bit to block + 7 bit w = 12 bit Address to each word=7bits Capacity if bus has 28 bit=2?8= 28 Mbit= 32MB 2. How many blocks in memory if memory capacity is 32 Kbit for 8 bit word and each block has 512 words? Capacity= 32 x 2!0 =2!5=# block x 512word x 8 bits = =2!5 = # blocks x 2'* — number of block= 2 = 8 block Total number of words = total capacity/size of word= 32 Kbit / 8 bit = 2!5/23= 2" words in all memory Total number of blocks = capacity of memory in word/number of words in each block= 2!? word / 512 words = 2? / 2? = 2? =8 blocksInterleaved Memory * Used to increase memory speed and enhance error correction + Collection of DRAM chips Grouped into memory bank + Banks independently service read or write requests ° K banks can service k requests simultaneously ¢ Organize memory chips in modules/banks to be sold Module 0 Module 1 Module 2 Module 3 , “ . oe 8 1 u ° ° Memory size=16 4 5 6 7 | Divide for 4 modul ° 1 A 3 | Fach module has address 2 bits=2? nbits wordin the bank/module | bankimodule address] Address Format (a-m) bits ambits address of module = number of bits address of hole memory- number of bits address of each module =n-m Example address of module = number of bits address of hole memory- number of bits address of each module ==n-m If Memory capacity = 64 word so 25> number of address bit = 6 Ifnumber of module/bank=4 so 2?> 2 bits to address module/bank Number of bits for word in module/bank = 6 — 2 = 4 > module/bank module capacity =24=16 [Gatmietakimde | Tabane altos = as his glo] m@[s | mg nig fs 00100] 4 ooioi | 5 ooo |g | ooorit | 7 00000| 9 1 oo00i0 [2 o0011 [3 02) vv o oo) ! ‘These bits are same in all 4 modules.Example :Main memory 32 M word, with16 memory banks (module) draw modular memory address format if implemented with interleaving Solution Main memory has 32 MW= 2° x27° =2?5w—> number of address bits=25 For 16 memory module/ bank number 2* —_ m(module address)=4 address of module=n-m=25-4=21—+module capacity= 27! = 2?°x2=2MW address of the module = address bits of hole memory- address of each module=n-m. 111 1111 006 LLL Lb OFF [= Ter Te =) 3RF 3100) a0) 1200) ws.) 000 [—« 1 2 3! 003 0000 0000 00b 0000 0000 11b Example 2 » Given a memory address as 29C (10 bits) and there are 4 memory banks/modules. Determine the memory bank address and the address of the word in the bank. * Memory address = 29C=10 1001 1100, « Exists 4 memory banks> 2? > 2 bit for the banks/modules addess 1010 O11 00, No of bits for word in module/bank = 10-2=8, module/bank capacity is 2° = 256 Memory bank/module address = 00 Address of the word in the bank/module = 1010 0111 = 0A7 TILL 1111 00b 111 1111 1b 3Fc| = 1a ry us| 3FF Moo) Mion 2.00) acy 0A7 000 L_» L 003 0000 0000 00! 000.0000 11h