CEN 261 - Midterm Exam - Group B

International Burch University

22/11/2021

SOLUTIONS
Question Points Score
1 30
2 10
3 30
4 30
Total 100

Question 1: Cache Memory

[30 pts] Explain the advantages and disadvantages (in couple of sentences or a bullet-ed list)
of using a direct mapped cache instead of an 8-way set associative cache.

As there is only one block where the data for a physical address can be mapped to, a
direct mapped cache has a faster hit time than the set associative cache. But this is also a
disadvantage in the case where two separate addresses map to the same cache block, because
a cache hit will never happen in that case. This affects performance. In the case of 8-way
associative cache, where we have 8 blocks within one set, a block from main memory can map
to any of the 8 blocks within a set. This gives flexibility, but also in case of 2 main memory
blocks that map to the same cache block (direct-mapped case), here in set-associative cache,
both references will be a cache hit, so no misses. The disavantage of a set-associative cache,
compared to a direct-mapped cache, is that it takes a long time to search (all the TAG
registers, for all the blocks).

(a) Consider a direct-mapped cache design with a 32-bit address. Memory is byte-addressable.
A scheme for the address bits used to access the cache is shown below:
Tag Index Offset
31-11 10-7 6-0
31-11 10-5 4-0

For each of these designs, determine: 1. What is the cache block size, in words? and 2.
How many cache blocks the cache has?

design 1: offset is 7 bits, which means there are 128 bytes/block = 32 words/block.
design 2: offset is 5 bits, which means there are 32 bytes/block = 8 words/block.
design 1: index is 4 bits, which means there are 16 blocks in the cache.

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 design 2: index is 6 bits, which means there are 64 blocks in the cache.

(b) Assume you have a 4-way set associative cache. Words are 4 bytes. Addresses are to the
byte. Each block holds 256 bytes. There are 512 blocks in the cache. If you reference
a 32-bit physical address D A B 1 5 3 2 1 (in hex) (and the cache is initially empty):
1. How many data words are brought into the cache with this reference? 2. Which set
does the data (that is brought in) go to with the given physical address supplied to the
cache?

1. The entire block will be  filled. Words are 4 bytes long, each block holds 256 bytes,
28 bytes/block
so there are 22 bytes/word = 26 words/block = 64words/block.
Offset bits = 6 + 2 = 8 bits (byte-addressable cache);
2. As the question asks ”which set does the data go to?” we need to determine what
the index bits are. As we know the offset is 8 bits, because data is byte addressable.
If we write the hex address in binary, we have: 1101 1010 1011 0001 0101 0011 1000
1001
Offset is: 1000 1001
   
512blocks 29
Number of sets: 4blocks/set
= 22
sets = 27 sets = 128sets,
so 7 bits of index are required. These are 101 0011 which implies the address is mapped
to 83th set.

Question 2: Number Systems

[10 pts] Perform the following conversions:

(a) Write the hexadecimal numbers 19A and 28 in binary.

0001 1001 1010; 0010 1000;

(b) Convert the hexadecimal number B14E16 to octal number, via binary.

d754247026

(c) Convert the (binary) number 111010001 to decimal. Convert the (decimal) number 145
to binary.

465; 10010001;

(d) Convert the (hexadecimal) number 13C to decimal. Convert the (decimal) number 19
to hexadecimal.

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 316; 13;

(e) Convert the (binary) number 111010001 to decimal. Convert the (decimal) number 145
to binary.

same as (c)

(f) Convert the octal number 345 to hexadecimal, via binary.

E5;

(g) Convert the hexadecimal number AEC3 to octal, via binary.

127303

Question 3: Memory System

[30 pts] What is the main design issue of a memory system? Identify the challenges and
explain possible solutions.

The main design issue is how to bridge the CPU-memory speed gap. i.e. How to make
memory system work faster? How to increase data transfer rate between CPU and memory?
How to address the ever increasing storage needs of applications? Possible solutions: cache
memory and virtual memory. CACHE: fast memory, organized possibly in several levels,
that sits between CPU and MM. Faster than MM and small. Frequently accessed data and
instructions stored here. Uses SRAM technology. VIRTUAL MEMORY: technique used by
the OS to provide an illusion of very large memory to the CPU. Program and data actually
stored on secondary memory that is much larger. Transfer parts of program and data from
secondary memory to main memory only when needed. +illustrations.

(a) Use the example of a 4K x 16 memory system to: (1) explain the organization of
memory cells, and (2) calculate the total number of external connections to the memory
system.

2n × m;
n is a number of address lines, m is a number of data lines - maximum number of
memory locations 2n
will be represented through m bits of data in each storage location.
For this example, 212 ,

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 means there are n=12 bits for address lines; m = 16, 16 bits for data lines, 2 power
and ground signals, 2 control signals RD/W and CS. Total 32 external connections.

(b) Consider a word-addressable computer with 128KB of memory and a 32-bit word size.
Its memory is built out of 4K x 4 chips. How many chips make up memory? How many
bits make up an address?

128K×32
4K×4
) = 256chips;

128K×8bit
32bit/words
) = 32Kwords = 215 words;
15 bits make up an address.

Question 4: Instruction Formats Basics & Registers

[30 pts] Describe the instruction format and the types of instruction formats, and provide
examples. What is the purpose of the MAR, MDR (MBR), IR, PC and ACC registers?

Instruction format: an instruction consists of 2 parts: opcode or operation code and operand(s).
There are various categories of instructions: data transfer (MOVE R1, R2), arithmetic and
logical (ADD R1, R2), control, I/O and special machine control instructions. Opcode speci-
fies the operation to be performed by an instruction, depending on the category of instruction.
Operands specify source(s) and destination of the operation. Source operand can be spec-
ified by an immediate data, by naming register, or specifying address of memory location.
Destination can be specified by a register or memory address. The number of operands may
vary, so we can have 0-address instruction (opcode ), 1-address (opcode memory address),
2-address (opcode memory addr memory addr), 3-address instructions (opcode reg reg reg).
Also while specifying operands we need to know various addressing modes (addressing mode
is a way by which the location of the operand is specified in the instruction).
Registers: MAR holds the memory address of the data needing to be accessed by the CPU.
MDR holds the data being transferred to or from the memory location by the CPU. IR
holds the encoded instruction that is currently being executed or decoded. PC holds the
memory address of the next instruction to be executed. ACC holds the result of a calculation
performed by the arithmetic/logic unit.

(a) An instruction ADD R1, A is stored at memory location 2002H. R1 is processor register,
and A is a memory location with address 200CH. Each instruction is 32-bit long. What
will be the values of PC, IR, and MAR during execution of the instruction?

2006H; ADD R1, A; 200CH

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(b) Assume that we want to implement a simple, 8-instruction processor. The processor
will have 16 user programmable registers. All 8 instructions are given in table below.
1. Write the resulting register transfer language for the instruction types given in table,
and explain what the instructions do ( refer to column: Example Syntax). 2. How
many bits is required for instruction encoding to support all instruction types given in
table?

Instruction Class Instructions Example Syntax

ALU (all data in registers) ADD, SUB, AND, OR, NAND, NOR SUB R1, R2, R3
Load LOAD LOAD R1, R2
Store STORE STORE R1, R2

R1¡-R2-R3, this instruction subtracts R3 from R2 and puts the result in R1; R1¡-
Mem[R2], this instruction loads data from memory location of R2 and puts it in R1;
mem[R2]¡-R1 this instruction stores value from R1 into mem location of R2.
ALU: 3 bits for opcode, 4 bits for destination register, 4 bits for source register 1, 4 bits
for source register 2. In total 15 bits.
Load or Store: 3 bits for opcode, 4 bits for dest/source register, 4 bits for address
register. In total 11 bits.
To support all instruction types here we need max(15,11) = 15 bits.