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NTD24N06L 1G
NTD24N06L 1G
Power MOSFET
24 Amps, 60 Volts
Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in http://onsemi.com
power supplies, converters and power motor controls and bridge
circuits.
24 AMPERES, 60 VOLTS
Features RDS(on) = 0.036 W (Typ)
• Pb−Free Packages are Available
N−Channel
Typical Applications D
• Power Supplies
• Converters
• Power Motor Controls
G
• Bridge Circuits
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
MARKING DIAGRAMS
Drain−to−Source Voltage VDSS 60 Vdc & PIN ASSIGNMENTS
Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc
4
Gate−to−Source Voltage Vdc Drain
− Continuous VGS "15
− Non−repetitive (tpv10 ms) VGS "20
4 DPAK
N6LG
YWW
Drain Current CASE 369C
24
− Continuous @ TA = 25°C ID 24 Adc (Surface Mount)
− Continuous @ TA = 100°C ID 10 1 2
3 STYLE 2
− Single Pulse (tpv10 ms) IDM 72 Apk
2
Total Power Dissipation @ TA = 25°C PD 62.5 W 1 3
Drain
Derate above 25°C 0.42 W/°C Gate Source
Total Power Dissipation @ TA = 25°C (Note 1) 1.88 W
Total Power Dissipation @ TA = 25°C (Note 2) 1.36 W
4
Operating and Storage Temperature Range TJ, Tstg −55 to °C Drain
+175 4
ORDERING INFORMATION
Device Package Shipping †
NTD24N06L DPAK 75 Units / Rail
NTD24N06LG DPAK 75 Units / Rail
(Pb−Free)
NTD24N06L−1 DPAK (Straight Lead) 75 Units / Rail
NTD24N06L−1G DPAK (Straight Lead) 75 Units / Rail
(Pb−Free)
NTD24N06LT4 DPAK 2500 Units / Tape & Reel
NTD24N06LT4G DPAK 2500 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NTD24N06L
50 50
VGS = 10 V 5V VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)
30 6V 4V 30 TJ = −55°C
20 3.5 V 20 TJ = 100°C
10 10
3V
0 0
0 1 2 3 4 1.6 2.4 3.2 4 4.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 100°C
0.06 0.06
TJ = 100°C
TJ = 25°C
0.04 0.04
TJ = 25°C
TJ = −55°C
0.02 0.02
TJ = −55°C
0 0
0 10 20 30 40 50 0 10 20 30 40 50
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current
Gate−to−Source Voltage and Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE
2 10000
ID = 12 A VGS = 0 V
1.8 VGS = 5 V
TJ = 150°C
IDSS, LEAKAGE (nA)
1.6
1000
(NORMALIZED)
1.4
1.2
100
1
TJ = 100°C
0.8
0.6 1
−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
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NTD24N06L
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on−state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load;
voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2800
VDS = 0 V VGS = 0 V
TJ = 25°C
2400
C, CAPACITANCE (pF)
Ciss
2000
1600
1200 Crss
Ciss
800
400 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
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NTD24N06L
6 1000
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
5 QT
Q1 Q2 VGS
4 100 tr
t, TIME (ns)
tf
3
td(off)
2 10 td(on)
VDS = 30 V
1 ID = 24 A ID = 24 A
TJ = 25°C VGS = 5 V
0 1
0 4 8 12 16 20 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
20 TJ = 25°C
16
12
0
0.6 0.68 0.76 0.84 0.92 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non−linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance − temperature.
General Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry custom.
transition time (tr,tf) do not exceed 10 ms. In addition the total The energy rating must be derated for temperature as shown
power averaged over a complete switching cycle must not in the accompanying graph (Figure 12). Maximum energy at
exceed (TJ(MAX) − TC)/(RqJC). currents below rated continuous ID can safely be assumed to
A Power MOSFET designated E−FET can be safely used equal the values indicated.
in switching circuits with unclamped inductive loads. For
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NTD24N06L
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
(NORMALIZED)
0.2
0.1
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
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NTD24N06L
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
NOTES:
−T− SEATING
PLANE 1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
B C 2. CONTROLLING DIMENSION: INCH.
V R E
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
4 B 0.250 0.265 6.35 6.73
Z C 0.086 0.094 2.19 2.38
A D 0.027 0.035 0.69 0.88
S E 0.018 0.023 0.46 0.58
1 2 3
U F 0.037 0.045 0.94 1.14
K G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
F K 0.102 0.114 2.60 2.89
J L 0.090 BSC 2.29 BSC
L H R 0.180 0.215 4.57 5.45
S 0.025 0.040 0.63 1.01
D 2 PL U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
G 0.13 (0.005) M T Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20 3.0
0.244 0.118
2.58
0.101
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NTD24N06L
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
C NOTES:
B 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
V R E 2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3 D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
−T− F 0.037 0.045 0.94 1.14
G 0.090 BSC 2.29 BSC
SEATING
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
J
F V 0.035 0.050 0.89 1.27
H Z 0.155 −−− 3.93 −−−
D 3 PL
STYLE 2:
G 0.13 (0.005) M T PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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