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Veda Coa
Veda Coa
ARCHITECTURE
COMPLETE PROCESSOR
Presented by :
VEDA J S
4GM22EC123
3rd ‘B’
PROCESSOR
• Instruction unit
• Integer unit
• Floating point unit
• Instruction cache
• Data cache
• Bus interface
STRUCTURE OF COMPLETE PROCESSOR
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Processor contains a instruction unit that fetches instruction from the cache or main memory
when the desired instructions are not present in the memory ,it has separate units to deal with
integer data and floating point data.
A data cache is inserted between these units and the main memory.using separate caches for
instructions and data is commom practice now but other processors can use single cache that
stores both instructions and data.
The processor is connected to the system bus and hence to rest of the computer by means of
bus interface.
Not only one integer and floating point unit processor,we may include sveral integer and floating
units to increase the rate of instruction execution.
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