Comparative Analysis of Digital Circuits Using

16 nm FinFET and HKMG PTM Models

Satish Masthenahally Nachappa1(&), A. S. Jeevitha2,

and K. S. Vasundara Patel2
1
Department of Electronics and Communication,
Middle East College, Muscat, Oman
satish@mec.edu.om
2
Department of ECE, BMS College of Engineering, Bengaluru, India
jeevithagowda12@gmail.com, vasu.ece@bmsce.ac.in

Abstract. Low Power VLSI design has become the most important challenge
of present chip designs. Advances in chip fabrication have made possible to
design chips at high integration and fast performance. Reducing power con-
sumption and increasing noise margin have become two major concerns in every
stage of SRAM designs. In this paper the 6T and 8T SRAM cells are constructed
using High-K Metal Gate and FinFET for low power embedded memory
applications. These SRAM cells’ performance are analyzed and compared in
terms of basic parameters, such as power consumption and static noise margin
(SNM).

Keywords: SRAM
High-K Metal Gate
FinFET
Low power

Leakage current
Static noise margin

1 Introduction

As the technology node scales beyond 50 nm, there is need for inventive method-
ologies to ignore the hurdles due to the basic physics that bounds conventional
MOSFETs. Design of digital circuits finds the prominent applications in storing data in
the recent days. Since SRAMs are faster than DRAM, as it is faster to access SRAMs
finds more applications in Cache memory. The simplest static random access memory
cell consists of 6 transistors.
New demanding technologies have started emerging under the experiment and
research to overcome the limitations of conventional MOSFETs. On an account of
scaling philosophy, the conventional device bulk silicon (Si) technology airs the
explosion of the chip due to higher leakage powers, whereas the upcoming devices like
Silicon On Insulator, High K Metal Gate as shown in Fig. 1, FinFET, are emerged
guaranteeing the low power resolution for the IC implementation. This proposed work
shows the design of low power memory cells and also optimization of its performance
is derived from the basic level of design.

© Springer Nature Switzerland AG 2019

K. Arai et al. (Eds.): FICC 2018, AISC 886, pp. 81–90, 2019.
https://doi.org/10.1007/978-3-030-03402-3_7
82 S. M. Nachappa et al.

Fig. 1. Schematic diagram of High-K and Metal Gate MOSFET.

1.1 Static Random Access Memory

Static RAM or SRAM is a type of semi-conductor memory [7] which comprises of flip-
flop or the bi-stable latching circuit to store data bits (0 or 1). Static Random Access
Memory (SRAM) demonstrates data stability, but this is volatile in nature i.e., data is in
time lost when the circuit or memory is powered off. The word static distinguishes
SRAM by DRAM which needs to be refreshed at particular intervals. Static RAM is
more expensive and faster than Dynamic RAM, Static RAM is usually in use for CPU
cache memory while the DRAM finds its applications in the main memory of com-
puters [9]. The power consumption of static random access memory (SRAM) varies
extensively, which depends on how frequently the memory is accessed.

1.2 High-K Metal Gate

To tolerate the scaling of the device beyond 45 nm, manufacturers of semiconductor
device have initiated that the High K and Metal Gate (HKMG) stacks within the
MOSFET which used in the digital CMOS, which creates basis for the logic circuits
inside the SoC (System on Chip) and microprocessors and used in cell phones, tablets,
computers, etc. As well, architecture of memory such as DRAM also drifted to High K
dielectrics. An insulator class with the metal oxide which has a relative dielectric
constant which is greater than or equal to 9 and also which involves metals which
belongs to the group 3–5, Al and lanthanides forms a High-K dielectrics. Equation (1)
describes the dielectric constant K, where Dielectric permittivity = ed and free space
permittivity = e0

K = 2d =2o ð1Þ

Some of the examples of High K dielectrics are Lu2O3, Ta2O5, La2O3, Sc2O3,
Nb2O5, Y2O3, ZrO2, TiO2, HfZrO4, HfO2, Al2O3 and the mixtures of these.

1.3 FinFET
Scaling of traditional planar MOSFETs is been facing issues such as variations in
device parameters, significant DIBL, leakage and subthreshold swing degradation. In
order to solve these problems, three-dimensional (3-D) device structures as shown in
 Comparative Analysis of Digital Circuits 83

Fig. 2 possibly would be the solution and have been worked on. FinFETs are built on
SOI wafers or bulk silicon. FinFETs among the 3-D devices are very promising
competitor for the future nanoscale technology and memory applications with high-
density. In recent days, FinFET technology has been seeing a huge increase in the
implementation within the ICs.

Fig. 2. Structure of FinFET

FinFET is primarily a multi-gate FET (Field Effect Transistor) which had been
scaled further of MOSFET. The FinFET is a transistor design, first developed by
Chenming Hu and colleagues at the University of California at Berkeley. These device
structures have all the properties similar to a typical transistor, and also have few
benefits on the CMOS. MOSFET has some practical issues like short channel effects,
DIBL, power dissipation, performance degradation. Hence to avoid the difficulties
faced by conventional MOSFETs, FinFET structure came into existence to build the
transistors further efficient.
Different modes of operation of FinFET
• Shorted-gate mode [SG]: Two gates that are joined together as shown in Fig. 3(a).
• Independent gate mode [IG]: The gate is driven by independent signals as shown in
Fig. 3(b).
• Low power mode [LP]: In this mode of operation one gate is connected to reverse
bias, this reduces leakage current.

Fig. 3. (a) Shorted gate (b) Independent gate.

84 S. M. Nachappa et al.

1.4 Conventional 6T SRAM Cell

The six transistors SRAM (static random access memory) cell configuration is
implemented by connecting two inverters back to back as shown in Fig. 4. The four
transistors at the center are modeled to create two cross coupled inverters [8]. The
transistors are designed very tiny to save the area of chip. A ‘0’ (low) input on the
inverter1 will generate a ‘1’ (high) value on the inverter2 which is because of the
feedback structure, which amplifies the ‘0’ value on inverter2. Similarly, the first
inverter that is having a ‘1’ (high) input value will results a ‘0’ input value on inverter2,
so the ‘0’ (low) input value is given as feedback onto the first inverter. Hence, its
logical value i.e., 0/1 is stored by the inverters.

Fig. 4. CMOS SRAM cell.

1.5 Predictive Technology Models (PTM) for Multi-gate Transistors

A new generation of PTM for multi-gate transistor and metal-gate transistors, specif-
ically FinFET and High-K Metal Gate for 16 nm technology nodes is developed. These
model parameters are developed using BSIM model. It is a surface-potential-based
skimmed model which can model double-gate, tri-gate and gate-all-around different
multi gate models. The new PTMs for 16 nm multi-gate transistors have been designed
in two specific application versions, high performance (HP) and low-standby power
(LSTP).
This retains the standard framework of BSIM4 and BSIM-SOI models to incor-
porate the effect of 3D structure and QME (quantum mechanical effects) on device
characteristics and short channel effects. The model for real-device effects velocity
saturation, series resistance, mobility degradation, parasitic capacitance, etc. This
allows ease in efficient extraction of model parameters. FinFET device behavior is most
sensitive to the technology specifications, primary parameters and physical parameters.
 Comparative Analysis of Digital Circuits 85

1.6 Static Noise Margin (SNM)

SNM is measure of how strong the system is against the noise. More the SNM better
will be the system. It is defined as the maximum quantity of noise voltage which can be
introduced at the two inverters output, so the data is retained by the cell. By using a
butterfly curve method, SNM can be calculated. In Fig. 5, we can see SNM which is
graphically represented for the bit cells which is holding data. The resulting two-lobed
curve is called as “butterfly curve” used to determine SNM. The largest side of the
square diagonal length that can be embedded inside the lobes of the butterfly curve is
known as SNM. From the plot shown in the figure, it causes the Inverter1 to move
downwards and VTC of Inverter2 to move to the right. When both the NM value
moved, then the curves will meet at only two points.
(1) SNM calculation
The SNM calculation with respect to the plot in Fig. 5 is explained here.
Butterfly curve = Maximum side of the square.
SNM = Maximum side of the Square = Maximum length of the diagonal of
Square/√2.

Fig. 5. Measuring SNM using butterfly curve.

2 Single Ended 8T SRAM Cell

An eight transistor, single ended S-RAM design as shown in Fig. 6 which by

improving the read SNM, improves the data stability and also Power dissipation is
reduced [1]. As per proposed design, the circuit which is used for read purpose is
transmission gate. The inversion of the read word-line signal (RWL) is the additional
signal, RWLB [4]. It regulates the M7 transistor of the transmission gate. Though the
RWLB and RWL are asserted and when the transmission gate is ON, the data stored
node gets linked with RBL. Hence the stored data at point Q is read through or moved
to RBL.
86 S. M. Nachappa et al.

Fig. 6. Single-ended 8T SRAM cell.

The major advantage of the proposed circuit is that this is not essential to arrange a
precharge circuit and the sense amplifier as essential in the prior six transistor
Static RAM cell, since the saved data/value is straight away moved through the
transmission gate [6]. The charging/discharging power of RBL is used up only after
RBL is altered. [2] Accordingly, there will be zero power dissipation on RBL if an
impending data is similar to earlier state. This proposal reduces the bit-line power in
two cases, they are the successive 1’s and successive 0’s.
The simulations have been performed on HSPICE tool version [10] Z-2007 using
16 nm technology with input voltage of range 0.9 V. The two parameters total power
dissipation and SNM are used for the simulation to verify SRAM performance. The
performance of FinFET [11], HKMG and MOSFET are compared for each parameter
[5]. The SNM of SRAM cell is demonstrated as the maximum noise magnitude that
does not disturb the stored bit of the SRAM cell.

3 Simulation Results

HSPICE simulations are done using 16 nm FinFET technology. The 6T and the 8T
cells are compared for several SRAM metrics. The widths of all the transistors were
chosen to obtain optimal curves with least distortions in read-write and hold modes for
the HSPICE simulations. To get the read failure analysis, a ramp voltage is given at one
of the bit or bit lines and the output is read at the other and vice versa. On overlaying
both the curves, a similar graph is obtained as to the one in Fig. 5, which is termed as
the butterfly curve. SNM [3] is the side of the prime square that fits in the butterfly. By
decreasing Vdd step by step, SNM can be tabulated. When the two curves flip, read
failure is said to have occurred as shown in Fig. 7.
The SNM [3] was presented for both 6T SRAM and 8T SRAM as indicated by
Tables 1 and 2 and it was found that read stability of the 8T SRAM is improved as
compared to 6T SRAM.
 Comparative Analysis of Digital Circuits 87

Table 1. SNM for 6T and 8T SRAM cell using LP-HKMG

VDD (V) SNM 6T SRAM (V) SNM 8T SRAM (V)
0.9 0.3 0.2
0.8 0.2 0.16
0.7 0.17 0.14
0.6 0.17 0.12
0.5 0.14 0.09
0.4 0.1 0.06
0.3 0.07 0.05
0.2 Read failure 0.012
0.1 0.0037

Table 2. SNM for 6T and 8T SRAM cell using FINFET.

VDD (V) SNM 6T SRAM (V) SNM 8T SRAM (V)
0.85 0.29 0.38
0.7 0.26 0.28
0.6 0.24 0.23
0.5 0.21 0.18
0.4 0.19 0.14
0.3 0.14 0.1
0.2 0.07 0.07
0.1 Read failure 0.02

The below figures (Figs. 7, 8, 9 and 10) depict the read SNM and the read failure
for the 6T and 8T SRAM cells respectively. The read-failure occurs when the two
curves flips as shown in Figs. 8 and 10 for both LP-HKMG and LP-MultiGate PTM
models.
SNM is tabulated for both 6T SRAM and 8T SRAM which is shown in Tables 1
and 2 and it is seen that read stability for both LP-HKMG and LP-MultiGate PTM
models is improved compared to 6T SRAM cell.

Fig. 7. LP HKMG 8T SRAM cell butterfly curve.

88 S. M. Nachappa et al.

Fig. 8. Read failure in LP HKMG 8T SRAM cell.

Fig. 9. FinFET 8T SRAM cell butterfly curve.

Fig. 10. Read failure in FinFET 8T SRAM cell.

Table 3. Delay and power dissipation for 6T SRAM cell.

Model Write delay Read delay Power dissipated
CMOS 30.293 ps 3.884 ps 4.45753 mw
LP HKMG 39.45 ps 37.158 ps 46.5259 nw
FinFET 132.31 ps 3.125 ns 149.2712 nw
 Comparative Analysis of Digital Circuits 89

Table 4. Delay and power dissipation for 8T SRAM cell

Model Write delay Read delay Power dissipated
CMOS 5.9663 ns 10.077 ps 4.45753 mw
LP HKMG 4.0052 ns 22.767 ps 46.5259 nw
FinFET 6.0061 ns 1.344 ps 149.2712 nw

Tables 3 and 4 show the simulation results for delay and power dissipation of 6T
SRAM and 8T SRAM, respectively. The reduction in dissipated power and read-failure
probability has been achieved better by using both models when compared to CMOS
technology. Butterfly curve and read-failure representation for both models are dis-
played graphically.

4 Conclusion

In this paper 6T SRAM and 8T SRAM cells are designed and analyzed using 16 nm
Low Power High-K Metal Gate and Low Power Multi-gate (FinFET) PTM models and
their read-write operations were performed successfully. The reduction in access time
and read-failure probability has been achieved better by using both models when
compared to CMOS technology. Butterfly curve and read-failure representation for
both models are displayed graphically.

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