1.

準備需要的資料
在做APR之前,首先我們必須準備以下三個檔案
(在此我們以一個反矩陣的範例程式來為大家做講解, Top Module Name : MATRIXINV)

檔名 說明
MATRIXINV_PAD.v 這個.v檔就是跑完Synthesis之後得到的Gate Level Netlist的Verilog檔，但是
還要再加入一個定義IO的module(MATRIXINV_PAD)。
MATRIXINV_PAD.sdc 在跑Synthesis的時候用到的.tcl檔案中加入以下這行指令
write_sdc “MATRIXINV_SYN.sdc”
(MATRIXINV請自行改成你的TOP Module名稱)
即可產生產生出Time Constraints檔案(MATRIXINV_SYN.sdc)
但是其中還需要再修改一些內容。
(請參考 MATRIXINV_SYN.sdc 與 MATRIXINV_PAD.sdc的不同)
MATRIXINV.io PAD的配置檔

在MATRIXINV_PAD所加入的module中

input pad : PDIDGZ

output pad : PDO02CDG
Core power pad : PVDD1DGZ
Core ground pad : PVSS1DGZ
IO power pad : PVDD2DGZ
IO ground pad : PVSS2DGZ
Corner pad : PCORNERDG

.io檔內容
Version: 1
Pad: CORNER0 SW
Pad: pCLK W
Pad: pIOVDD0 W
Pad: pIN_VALID W
Pad: pIN0 W
Pad: pCoreVDD0 W
Pad: pOUT0 W
Pad: pCoreVSS0 W
Pad: pIN1 W
Pad: pIOVSS0 W
Pad: pIN2 W

…
…
…
2.讀取檔案 , 並設定一些Library與相關檔案
需要的檔案都準備好之後，在執行SOC Encounter之前，
先從助教的資料夾裡複製環境設定檔
>cp /usr1/ce21/student/u95/u9512587/soce.csh . (後面的.表示現在的目錄)
還要再複製相關的Library檔案
>cp /usr1/ce21/student/u95/u9512587/ASIC_APR.tar .
再鍵入以下指令將它解壓縮
>tar xvf ASIC_APR.tar
再鍵入以下的指令即可進入SOC Encounter
>source soce.csh
>encounter (記得後面不要加& , 不能跑背景模式 , 原本的terminal將會在
使用Encounter的過程中顯示一些資訊。)

在encounter的工具列按[Design]
[Design Import…]
注意:在選擇檔案或是Library的時候，若可用Browser瀏覽點選的，請用滑鼠點選，盡量避免自行打上
檔名，可以降低檔名打錯找不到檔案，或是資料夾不正確之類的問題。

在[Basic]
a. Netlist
Files: MATRIXINV_PAD.v
Top Cell: ◆ By User : MATRIXINV_PAD
b. Timing Libaries
Max Timing Libraries: lib/slow.lib lib/tpz973gwc.lib
Min Timing Libraries: lib/fast.lib lib/tpz973gbc.lib
Common Timing Library: lib/typical.lib lib/tpz973gtc.lib c.
Physical Libraries ( 請按照順序加入)
LEF Files: lef/tsmc18_6lm_cic.lef
lef/tpz973g_5lm_cic.lef
lef/tsmc18_6lm_antenna_cic.lef
lef/antenna_6_cic.lef
d. Timing Constraint
Timing Constraint File:MATRIXINV_PAD.sdc
e. IO Assignment
IO Assignment Files: MATRIXINV.io
切換到[Advance]

IPO/CTS
f. IPO
Buffer Name/Footprint: buf
Delay Name/Footprint: dly2
Inverter Name/Footprint: inv

Power
g. Power Nets: VDD
Ground Nets: VSS

RC Extraction
h. RC Extraction
Capacitance Table File: library/TSMC018.capTbl
i. QX (Sign-Off RC Extraction)
QX Tech File: library/icecaps_5lm.tch

SI Analysis
j. CeltIC Libraries
Common cdB File: celtic/tsmc18.cdB

k.按[Save…]存檔，以後以上這些繁雜的步驟都可以直接按[Load…]讀進已經設定好的.conf 檔即可
l.按[OK]
經過一段時間的讀取之後，便會得到下面這樣的初始圖形

請仔細觀察在讀取timing constraint時有沒有被skip掉的指令 ,
由於timing constraint是合成電路的重要條件 , 所以請仔細檢查。

encounter.logX (X 是某個數字，數字越大表示越新)裡面紀錄著所有
執行encounter時的記錄檔。

在做Encounter的任何時刻 , 都可以按[Design]
[Save Design…]來將你的檔

案存檔 , 之後只要Encounter重新開啟後 , 再直接按[Design]
[Restore Design…]即可
讀取檔案 , 繼續編輯。

3. Connect/Define Global Net

在encounter的工具列，按[Floorplan]
[Connections Global Net…]
1. Add all VDD pins to Connection List:
a. Connect ◆ Pins: VDD
b. Scope ◆ Apply All
c. To Global Nets: VDD
d. Click Add to List button
2. Add all VDD nets to Connection List:
a. Connect ◆ Net Basename: VDD
b. Scope ◆ Apply All
c. To Global Nets: VDD
d. Click Add to List button
3. Add all Tie High pins to Connection List:
a. Connect ◆ Tie High
b. Scope ◆ Apply All
c. To Global Nets: VDD
d. Click Add to List button
4. Add all GND pins to Connection List:
a. Connect ◆ Pins: VSS
b. Scope ◆ Apply All
c. To Global Nets: VSS
d. Click Add to List button
5. Add all GND nets to Connection List:
a. Connect ◆ Net Basename: VSS
b. Scope ◆ Apply All
c. To Global Nets: VSS
d. Click Add to List button
6. Add all Tie Low pins to Connection List:
a. Connect ◆ Tie Low
b. Scope ◆ Apply All
c. To Global Nets: VSS
d. Click Add to List button

7. Apply the connection list and check:

a. Click Apply button
b. Click Check button
c. Click Close button
4. Define Chip Floorplan
進行Floorplan的一開始我們必須決定晶片約需要多少的面積 , 而在之前的Synthesis
之後 , 我們可以在AREA Report中找到所要用到的Standard Cell占多少面積(Total
cell area) , 而Core Size便可用下列工式計算出來

Total Cell Area

Core Size =
Core Utilization
Total Cell Area
Core Height = Core Width =
Core Utilization

(Usually the core utilization is high than 85%)

接下來還要決定擺放Power Ring的面積(Core Margin)

–Experience
•Gate count = 70 k
•4000 Flip-Flops
•80% FF with dynamic gated clock
•Current needed = 0.2mA/MHz
Note: the value should multiply with 1.8~2 for no gated design

–Example:
•Gate count = 200 k
•No gated clock
•Clock frequency = 20 MHz
•Current needed = (200/70) * 0.2 * 20 * 2 = 22.86 mA
•Current density < 1mA/μm
•The Width of P/G Ring > 22.86μm
•If the largest width is 20 μm (process dependent)
Use two set P/G ring for this case
•Core Margin needed at least 20*2*2=80μm
 在encounter的工具列 , 按 [Floorplan] -> [Specify Floorplan…]

1. Specify core size:

a. Specify Dimensions by
◆ Core Size by:
◆ Width and Height:
Core Height: 250
Core Width: 250
2. Specify core margin:
b. ◆ Core to IO Boundary
Core to Left: 80
Core to Right: 80
Core to Top: 80
Core to Bottom: 80
3. Apply the specification:
c. Click OK button
5. Power Planning (Add Power Rings)
在encounter的工具列 , 按 [Power] -> [Power Planning] -> [Add Rings…]

1. In the Basic tab, fill the following field:

a. Specify metal layers and width
Top Layer: metal3 H Width: 9
Bottom Layer: metal3 H Width: 9
Left Layer: metal2 V Width: 9
Right Layer: metal2 V Width: 9
b. Click Update button
c. Specify offset
◆ Center in channel
2. 切換到[Advanced]
d. Configure wire group
◆ Use wire group
◆ Interleaving
Number of bits: 2
3. Apply the specification:
e. Click Apply button
Check if the ring is correctly created. If not, click undo button (in encounter toolbar) and
repeat step 1~3 again.
f. Click Cancel button
6. Power Planning (Add Stripes)
在encounter的工具列 , 按 [Power] -> [Power Planning] -> [Add Stripes…]

1. a. Specify metal layer, width, direction and spacing

Layer: metal2
Direction: ◆ Vertical
Width: 2
Click Update Button
b. Specify set number
Number of sets: 3

◆ Absolute locations
c. Specify locations by

(利用旁邊的Point…的按鈕直接在Layout上點選確切的位置,
但記得不要覆蓋到有Core Power Pad的地方 , 否則之後將無法連接Core Power PAD
到Power Ring上面)
d. Click Apply button
Check if the stripes are correctly created. If not, click undo button (in encounter
toolbar) and repeat step a~d again.
1. a. Specify metal layer, width, direction and spacing
Layer: metal5
Direction: ◆ Horizontal
Width: 8
Click Update Button
b. Specify set number
Number of sets: 2

◆ Absolute locations
c. Specify locations by
(利用旁邊的Point…的按鈕直接在Layout上點選確切的位置,
但記得不要覆蓋到有Core Power Pad的地方 , 否則之後將無法連接Core Power PAD
到Power Ring上面)
d. Click Apply button
Check if the stripes are correctly created. If not, click undo button (in encounter
toolbar) and repeat step a~d again.
加入Stripe之後 , 結果如下

7. Connect Core Power Pin

在encounter的工具列 , 按 [Route] -> [Special Route…]

Connect core power:

a. Set the following configuration
◇ Block pins
◆ Pad pins
◇ Pad rings
◇ Standard cell pins
◇ Stripes (unconnected)
b. Click OK button
8. Place Standard Cells
1. 在encounter的工具列 ,按 [Place] -> [Specify] -> [Placement Blockage]

2. Specify placement blockage for stripes

a. Specify placement blockage under metal2 and metal3
◆ M2
◆ M3
◇ M4
◇ M5
b. Click OK button

3. 在encounter的工具列 , 按 [Place] -> [Standard Cells And Blocks…]

 4. Configure place options:
a. Mode ◆ Full
b. Options
◆ Run Timing Driven Placement
◇ Reorder Scan Connection
c. Optimization Options
◇ Include Pre-Place Optimization
◇ Include In-Place Optimization
d. Click OK button

選擇[Physical View]
9. In-Place Optimization (IPO)
- Before Clock Tree Synthesis
1. 在encounter的工具列 , 按 [Timing] -> [Timing Analysis…]

2. Perform First Encounter trial route to model the interconnection RC effects

a. Design Stage
◆ pre-CTS
b. Analysis Type
◆ Setup
c. Click OK button

3. See timing reports in timingReports/ directory, MATRIXINV_PAD_preCTS.slk shows the timing

analysis results. All slack values must be positive value in this file. Moreover, for detail path report, see
MATRIXINV_PAD_preCTS_reg2reg.tarpt. DRVs report files: *.cap, *.fanout, and *.tran.
4. If the timing slack is negative, or there are DRVs, open Timing -> Optimization in encounter menu

5. Perform pre-CTS IPO

a. Design Stage ◆ pre-CTS
b. Optimization Type
◆ Setup
◆ Design Rule Violations ◆ Max Cap ◆ Max Tran ◆ Max Fanout
c. Click OK button
10. Clock Tree Synthesis (CTS)
1. In encounter menu, open Clock -> Create Clock Tree Spec…
2. a. Specify footprint
Buffer Footprint: clkbuf
Inverter Footprint: clkinv
b. Save Spec To: MATRIXINV_PAD.ctstch

3. In encounter menu, open Clock -> Specify Clock Tree

4. Choose clock tree spec file

a. Clock Tree File: MATRIXINV_PAD.ctstch
b. Click OK button
5. In encounter menu, open Clock -> Synthesize Clock Tree

6. Configure CTS options

a. Synthesize a clock with self-reconvergence or clocks with crossover points
◆ Handle Clock Crossover and Reconvergenc
b. Click OK button
 7. In encounter menu, open Clock -> Display -> Display Clock Tree
8. Display phase delay of clock tree in the core area
a. Display Selection
◆ Display Clock Phase Delay
b. Click OK button

Colors at the red end of the spectrum indicate the greatest phase delay. Colors
at the blue end of the spectrum indicate the smallest phase delay.

9. In encounter menu, open Clock -> Display -> Display Clock Tree

10. Display entire clock tree

a. Display Selection
◆ Display Clock Tree
◆ All Level
b. Click OK button

11. In encounter menu, open Clock -> Display -> Clear Clock Tree Display
 11. In-Place Optimization (IPO)
- After Clock Tree Synthesis
1. In encounter menu, open Timing -> Timing Analysis
2. Perform First Encounter trial route to model the interconnection RC effects
a. Design Stage ◆ post-CTS
b. Analysis Type ◆ Setup
c. Click OK button
3. After CTS, further timing optimization is performed to meet timing constraints if there is negative timing
slack or DRVs. Open Timing -> Optimization in encounter menu
4. Perform post-CTS IPO
a. Design Stage ◆ post-CTS
b. Optimization Type
◆ Setup
◆ Design Rule Violations
◆ Max Cap
◆ Max Tran
◆ Max Fanout
c. Click OK button

5. Verify if the hold time constraint is satisfied or not. Open

Timing -> Timing Analysis in encounter menu
a. Design Stage ◆ post-CTS
b. Analysis Type ◆ Hold
c. Click OK button

6. If hold time slack is negative, open Timing -> Optimization in encounter menu
7. Perform post-CTS IPO for hold time fixing
a. Design Stage ◆ post-CTS
b. Optimization Type
Setup ◆ Hold
c. Click OK button

See timing reports in timingReports/ directory, For detail path report, see MATRIXINV_PAD_postCTS_reg2reg.tarpt
(setup time check) and MATRIXINV_PAD_postCTS_reg2reg_hold.tarpt (hold time check). DRV violations report files:
*.cap, *.fanout, and *.tran.
12. Connect Standard Cell Power Line
1. In encounter menu, open [Route] -> [Special Route…]
2. Connect core power:
a. Set the following configuration
◇ Block pins
◇ Pad pins
◇ Pad rings
◆ Standard cell pins
◇ Stripes (unconnected)
b. Click OK button
13. Add PAD Filler
在encounter的terminal視窗裡鍵入
>source addIoFiller.cmd
14. SI-Prevention Detail Route (NanoRoute)
1. In encounter menu, open Route -> NanoRoute

2. Nanoroute can prevent cross talk effects and fix antenna rule violations, also it routes design to meet
timing constraints.
a. Configure routing features
◆ Fix Antenna
◆ Insert Diodes Diode Cell Name: ANTENNA
◆ Timing Driven Effort: 10
◆ SI Driven
b. Click OK button
3. In encounter menu, open Verify -> Connectivity
4. Check routing for LVS error
a. Click OK button
If you see any violations, routing result is not correct. (LVS error)
5. In encounter menu, open Verify -> Geometry
6. Check routing for DRC error
a.Allow ◆ Overlap of Pad Filler Cells
b. Click OK button
If you see any violations, routing result is not correct. (DRC error)
15. In-Place Optimization (IPO)
- After Detail Route
1. In encounter menu, open Timing -> Timing Analysis
2. Perform First Encounter RC extraction for timing calculation
a. Design Stage ◆ post-Route
b. Analysis Type ◆ Setup
c. Click OK button

3. Further timing optimization is performed to meet timing constraints if there is negative timing slack or
DRVs. Open Timing -> Optimization in encounter menu
4. Perform post-Route IPO
a. Design Stage ◆ post-Route
b. Optimization Type
◆ Setup
◆ Design Rule Violations
◆ Max Cap
◆ Max Tran
◆ Max Fanout
c. Click OK button
5. Verify if the hold time constraint is satisfied or not.
Open Timing -> Timing Analysis in encounter menu
a. Design Stage ◆ post-Route
b. Analysis Type ◆ Hold
c. Click OK button
6. If hold time slack is negative, open Timing -> Optimization in encounter menu
7. Perform post-Route IPO for hold time fixing
a. Design Stage ◆ post-Route
b. Optimization Type
◇ Setup ◆Hold
c. Click OK button
16. Add CORE Filler Cells
1. In encounter menu, open Place -> Filler -> Add…
2. Add core filler to improve electric effects of NWELL and PWELL:
a. Click Select button
b. Select all core filler cells
c. Click Add button d.
Click Close button e.
Click OK button
17. Stream Out and Write Netlist
1. Write the worst-case design timing file:
a. In encounter menu, open Timing -> Timing Analysis
Design Stage ◆ post-Route
Analysis Type ◆ Setup
Click OK button
b. In encounter menu, open Timing -> Calculate Delay
◇ Ideal Clock (取消這個選項) SDF
Output File: MATRIXINV_APR.sdf
Click OK button
2. Save design netlist CHIP.v for post-layout Gate-Level simulation:
a. In encounter menu, open Design -> Save -> Netlist
◆ Include Intermediate Cell Definition
◆ Include Leaf Cell Definition
Netlist File: MATRIXINV_APR.v
Click OK button

18. Post-Layout Gate-Level Simulation

在Post-Layout Gate-Level Simulation裡 , 我們需要 tsmc18.v 與 tpz973g.v 兩個
檔案 , tsmc18.v即之前Lab所給的檔案 , 而 tpz973g.v則是包含在ASIC_APR.tar這個
壓縮檔中 , 有了這兩個檔案之後 , 你就可以用做完APR得到的Verilog檔還有APR結
果得到的SDF檔做Gate Level Simulation了。