Accurate ZVS Boundary in High Switching
Frequency LLC Converter
Ren Ren1,2, Bo Liu2, Edward A. Jones2, Fred Wang2, Zheyu Zhang2, Daniel Costinett2
Jiangsu Key Laboratory of New Energy Generation and
Power Conversion
Nanjing University of Aeronautics and Astronautics
Nanjing, China
rren3@utk.edu
Abstract—Due to the realization of zero voltage switching
(ZVS) under the full load range, LLC resonant converter is
widely adopted in the telecom, battery charger and several
applications, characterized with high efficiency, high frequency
and high power density, to realize DC conversion. Recently, by
using Gallium Nitride (GaN) HFETS, switching frequency of
LLC converters is further increased. However, ZVS failure
cannot be predicted accurately in the high switching frequency
condition by only considering traditional constraints generally
applied in the low frequency design. The traditional constraints
result in a too optimistic estimation of the dead time to obtain
ZVS without considering the reverse resonance under the dead
time and the design of resonant parameters at high resonant
frequency and high load condition. The experiment shows the
LLC converter loses ZVS even through the converter satisfies the
ZVS constraints proposed by previous paper. In this paper, the
failure mode will be investigated in detail and an accurate ZVS
boundary is proposed for high frequency LLC converter design.
The proposed theory was verified on a 1 MHz, 1500 W LLC
prototype.
Keywords—ZVS Boundary; GaN HFETS; LLC Resonant
Converter; High Resonant frequency
I. INTRODUCTION
With the development of information technology and
power electronic technology, the higher demand of the power
management has been proposed. High efficiency, high
frequency and high power density are becoming a trend of the
isolated dc/dc converters. LLC converter is a very promising
topology with full load range ZVS for the primary side
switches and ZCS for the secondary side switches, which gains
much attention in industry and academia. A lot of research
works focus on the design and control of this topology because
it is very suitable for high switching frequency operation and it
can achieve the high power density potentially [1-4].
The dissertation [5] is first paper to systematically
introduce the design and operation principle of this converter.
The paper [6] and [7] propose an optimal method to design the
LLC converter and most people follow this design procedure.
The traditional constraints of ZVS realization proposed by
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paper [6] have two key factors. One principle is switching
frequency which renders the resonant tank impedance inductive
or capacitive, and the other one is the dead time which makes
the magnetizing current have enough time to discharge the
voltage of the output capacitance of device from the input
voltage to zero. However, the analysis does not consider some
non-ideal factors. The paper [8] considers the non-linear of the
output capacitance of device for ZVS realization and utilizes
the charge concept to calculate the needed dead time for ZVS.
The paper [9] supplements the dead time calculation based on
charge concept and adds the charge of secondary side’s
devices, stray capacitance of PCB and winding capacitance of
transformer into the total charge needed to be discharged by
magnetizing current. But all these analysis are not
comprehensive, and they do not consider some special issues
under both the high frequency and the high load condition that
dead time will play a more important role for ZVS realization.
The conventional constraints assume the larger dead time is,
more easily ZVS realization becomes. In fact, this is not the
correct conclusion for high resonant frequency and high load
condition in LLC converter. The paper [10] proposes a novel
method to predict the ZVS range, but it still does not take the
reverse resonance under the dead time and the influence of
resonant parameters into account for ZVS realization, and
essentially, the proposed method in paper [10] has same results
with the First Harmonic Approximation (FHA) method.
Fig.1. The equivalent circuits for ZVS
realization in LLC converter
 frequency, the magnetizing current can be treated as a current
source, which provides the constant current to discharge or
charge the output capacitance of devices. After discharging the
Lr iLr Cr nVo output capacitance voltage of S2 from input voltage to zero,
the body diode of switch S2 conducts and S2 will realize the
Vin Lm Rac zero voltage switching at the meantime.
The two key roles for realizing the ZVS are the frequency
im operation range and the dead time. The switching frequency
decides the resonant tank impedance’s property, capacitive or
Fig.2 The equivalent circuits for resonant tank inductive, which leads different load angle for the resonant
current and excitation voltage of the resonant tank. In order to
Table I. Abbreviations and normalizations realize the ZVS, the resonant tank must behavior as inductive
impedance with lagging resonant current to help discharge the
Normalized
Circuit Variable Symbol output capacitance of the switches. The Fig.2 displays the
Variable
equivalent circuits for resonant tank based on FHA. The table
Resonant 1 I. gives necessary abbreviations and normalizations of
fr = -
frequency 2π LC symbols for the following derivations.
The voltage gain K (the reflected output voltage over
Characteristic Ls input voltage) is derived as equation (1) using FHA method
Zo = - based on the equivalent circuit from fig 2.
impedance Cs
Rac ⋅ jω Lm
Turns ratio of n ⋅ Vo Rac + jω Lm
n - K= =
Transformer Vin 1 R ⋅ jω Lm (1)
+ jω Lr + ac
n ⋅ Vo jωCr Rac + jω Lm
Output voltage Vo K=
Vin m ⋅ x2
=
2 2
Switching f ª¬ (1 + m) ⋅ x 2 − 1º¼ + ª¬Q ⋅ m ⋅ x( x 2 − 1) º¼
fs x= s
frequency fr where m is the inductance ratio between magnetizing
inductance Lm and the resonant inductance Lr, x is the
Equivalent ac 8n 2 Z normalized the frequency ratio between the switching
Rac = RL Q= 2 o
load resistance π2 n Rac frequency fs and resonant frequency fr., Q is the quality factor
of resonant factor.
Lm
Inductance ratio m= - Also, the equation (2) can be obtained when the resonant
Lr tank behaviors as resistive, which the imaginary part of
resonant tank impedance equals zero.
II. ISSUES ON THE TRADITIONAL ZVS 1 R ⋅ jω Lm
Im( + jω Lr + ac )=0
CONSTRAINTS jωCr Rac + jω Lm (2)
The fig.1 shows the equivalent circuits for the mode of 1 1
ZVS realization in LLC converter. In the dead time, instead of →Q= −
k ⋅ (1 − x 2 ) x 2 ⋅ k 2
two component LC resonance including the resonant inductor Substitute (2) into (1), the frequency boundary function
and resonant capacitor, the magnetizing inductance joins in the (3) can be derived to distinguish whether the resonant tank is
resonance to form a three components LLC resonance. Due to capacitive or inductive.
the very low resonant frequency comparing as the LC resonant

2.5 2

K ( f , 7.5 , 0.4) n ⋅Vo K ( f , m, Q )

K ( f , m, Q ) =
K ( f , 10 , 0.4) 2 Vin Gb ( f , m)
K ( f , 10 , 0.01)
Gb ( f , m ) 1.5
K ( f , 20 , 0.4) fs
K ( f , 10 , 0.2) f =
Gb( f , 7.5) 2f fr
1.5 f = s K ( f , 10 , 0.585)
Gb( f , 10) fr Gb( f , 10)
Gb( f , 20) 1
1

0.5 0.5
0 0.5 1 1.5 2 0 0.5 1 1.5 2
f f
(a): ZVS realization frequency range vs. Inductance ratio m (b): ZVS realization frequency range vs. different Q value
Fig. 3. The ZVS boundary analysis with different resonant parameters
 mx 2 (3)
b x˅=
G˄
(mx 2 + x 2 -1)
The Fig.3 shows ZVS frequency range by using equation
(3). Fig. 3(a) shows the ZVS frequency range with different
ratio m of the magnetizing inductance to resonant inductance
with fixed Q factor and fig. 3(b) shows the impact of the
quality factor Q with fixed ratio m on ZVS frequency range.
From the Fig. 3 (a), it can be seen that the smaller ratio m is,
the wider ZVS frequency range becomes. Nonetheless, the
resonant inductance is very small under high resonant
frequency condition, and it is very hard to reduce the
magnetizing inductance to decrease the inductance ratio m due
to high root mean square (RMS) value of primary side current.
Also the conclusion from Fig. 3(b) the smaller Q value is, the
wider ZVS frequency range becomes, but the Q
( Q = 2π f r Lr / Rac ) value is very difficult to design to make it
small especially on the high switching and high current
application because high resonant frequency and high output
current mean a small resonant inductance and small load
resistance, which would lead to a large Q value easily. It
means the high frequency and high output current operation
will result in a much more narrow ZVS frequency range due to Fig.4. Simulation waveform for ZVS failure in LLC
the higher fr and smaller load resistance. This is one reason converter
why LLC converter is always designed as DC transformer in Vg Tr
⋅ Vg
the high switching frequency working at fixed frequency and 1 4 2
iLm _ pk (Vg ) = ⋅ =
with unregulated control. 2 Lm 16 Lm f r (6)
The second factor is the dead time. More precisely, ZVS
realization is related to the dead time and the parasitic where Lm is the magnetizing inductance and fr is the resonant
capacitance. Enough peak magnetizing current and dead time frequency. Combining (5) and (6), the needed dead time for
are demanded to satisfy that all the parasitic capacitance will ZVS realization can be derived as equation (7):
be discharged under the dead time interval, including the
output capacitance of the primary side devices, the output
16 Lm f r Qmag
Td _ need = (7)
capacitance of the synchronous rectifier devices and the Vin
transformer winding capacitance and some stray capacitance.
The above conditions for ZVS realization can be expressed by From the equation (7), the large dead time means more
(4): charge can be offered to realize ZVS. This is conventional view
1 in LLC converter, which larger dead time can realize ZVS
Qmag ≥2⋅Cpri_oss ⋅Vin +(Cstray +CW)⋅Vin + ⋅Csec_oss ⋅2Vo (4) more easily. However, this is not correct conclusion in the high
n frequency and high power condition. The Fig.4 shows the ZVS
failure mode in the high resonant frequency and high output
where Qmag is the charge provided by the magnetizing current, current case. The resonant frequency is 1 MHz and the output
Cpri_oss and Csec_oss are the primary side and secondary device’s power is 1.5 kW. From the waveform, we can see that in the
output capacitance respectively, Cstray and CW are the stray
capacitance of PCB layout and winding capacitance of the
transformer respectively, n is the transformer’s turns ratio.
The magnetizing current is treated as a constant current
source, so the charge provided by the magnetizing current is
derived as:
Qmag = iLm _ pk (v g ) ⋅ Td
(5)
where iLm_pk(vg) is peak value of magnetizing current which is a
function of input voltage vg, Td is the dead time. Also, iLm_pk(vg)
is expressed by the input voltage excitation:

Fig.5 Resonant current comparison in the dead time

dead time the drain to source voltage Vds is discharged to zero
but it was recharged to a positive value after a while. This
makes the devices cannot fully realize ZVS when turning on.
Vds
The reason for this is when Vds drops to zero, the secondary Vgs1
side diode will be on, which the voltage of magnetizing
inductance will be clamped by the reflected secondary side
voltage, so the magnetizing inductance cannot attend the
resonance with resonant inductor and capacitor. Therefore, LC
resonance will replace LLC resonance and resonant current
cannot keep a constant value and begin the opposite half cycle Isecondary
of resonance. When the resonant current becomes the reverse
value comparing as the value in the dead time, the output
capacitance will be recharged by resonant current and device
will loss ZVS opportunity with positive Vds. The Fig.5 shows
the resonant current under different resonant frequency and
power rating. If the resonant current changes to a reverse value Ir
in the dead time, high resonant frequency and high power Im
rating will cause higher resonant current drop which has larger
energy to recharge the voltage of output capacitance to a higher
value.

III. PROPOSED NEW ACCRUATE ZVS BOUNDARY
The proposed new accurate ZVS boundary supplements
the conventional ZVS constraints. There are two new
constraints adding to the ZVS boundary.
A. Constraint of Deisgn of Resonant Capacitance
The first is design rule for resonant capacitance to make sure
the magnetizing inductance will join in the resonance with LC
before Vds drops to zero. The dissertation [5] also gives some
ZVS failure cases under this constraint. The constraint is given
as following equation:
(Vsw − VCr )
⋅ Lm < n ⋅ VO (8)
Lm + Lr
where Vsw is voltage of mid-point of switch bridge, Vcr is the
voltage of the resonant capacitor, Vo is the output voltage.
Fig. 6 is equivalent circuits for resonance mode of three
components LLC including Lr, Cr and Lm when the converter
works below the resonant frequency under dead time interval.
Normally, when magnetizing current im reaches the value of
resonant current iLr, the secondary side diode will be off and
no energy will be transferred to the load from the primary side.
It must keep the voltage of magnetizing inductance is smaller
than the reflected output voltage in the primary side in LLC
resonance interval. This is very easy to satisfy under low
Vcr
Lr iLr Cr nVo
Vsw Lm
im
Fig.6 Equivalent Circuits for resonance interval with three
components LLC including Lr, Cr and Lm
Fig.7 Simulation waveform when equation (6) cannot be
satisfied
resonant frequency and low power condition due to a large
resonant capacitance and a small resonant current. However,
the resonant capacitance is going to be lower when resonant
frequency is becoming higher. In the same power rating, if you
do not design the resonant capacitor properly, the voltage
ripple of the resonant capacitor will let the voltage of
magnetizing inductance be higher than the reflected output
voltage, so the converter will break relationship shown by the
inequality (6) in the LLC resonance interval. This will shorten
the time of LLC resonance interval and begins the new LC
resonance in advance. The fig.7 shows simulation waveform
when the inequality (6) cannot be satisfied. After Lr current
resonates back to same level of Lm current, instead of clamped
by Lm current, it will resonant to the other direction. With this
mode, the switch turn off current will be less than the current
of magnetizing inductor Lm. The risk is that the charge is not
enough for ZVS comparing as the constant current.
In conclusion, once the inductance ratio is confirmed for
acquiring the suitable frequency operation range and the low
conduction loss, the value of resonant capacitance should be
paid special attention to. It needs make sure that the ripple
voltage of magnetizing inductance will not be higher than the
reflected voltage of secondary side. Otherwise, it will cause
possibility to lose ZVS.
B. Constraint of the Dead Time
 1000 Vs
Voltage in V, Current in A

Ir
500

-500

-1000
0 0.2 0.4 0.6 0.8 1
time in us
Fig.8 Load angle illustration Fig.9 3D diagram of Maximum dead time for ZVS realization

The second is the maximum dead time limitation for ZVS derived by the FHA method:
realization. From the analysis in the section II, even though 4G
the converter works below the resonant frequency in ZVS G vsw
region, the magnetizing current may not maintain a constant i = π (9)
current in whole dead time. From fig.4, the primary side r 1 R ⋅ jω Lm
+ jω Lr + ac
current in the dead time involves two intervals. In the first jωCr Rac + jω Lm
interval, magnetizing current acts as a constant current source
Based on equation (9), the load angle ș is derived as the
to discharge voltage of the output capacitance of switches, and G
it ends when the Vds drops to zero and the converter begins the lagging angle of vector ir of resonant current comparing as
LC resonance instead of LLC resonance. Then the second G
the vector vsw of excitation voltage of resonant tank:
interval begins, accompanied with reverse direction of
resonance of primary side current rather than keeping a (m + 1) ⋅ x 2 − 1 Q − Q ⋅ x 2
constant value, which may lead to a ZVS failure by recharge θ = arctan( − ) (10)
the Vds.
Q ⋅ k 2 ⋅ x3 x
The time of two intervals can be derived respectively. For In order to prevent the resonant current from going to the
the time of first interval has already been derived as equation reverse value to recharge Vds, the dead time must have the
(7). For the time of second interval is derived by using load maximum value which can be derived as:
angle concept. From the fig.8, load angle ș is phase difference
between the phase of resonant current and the phase of 16 Lm f r Qmag θ
excitation voltage applied in the resonant tank and can be Td_max = Td _ need + T falling = + (11)
Vin ωr
calculated under different load condition and switching
frequency. This load angle ș decides the time interval, starting where Td_need is the needed dead time to discharge the output
from when Vds drops to zero and ending at when the resonant capacitance based on (7), Tfalling is the time of resonant current
current go to a reverse value. In phasor domain, by setting the falling from the constant peak magnetizing current to the
excitation voltage of resonant tank as the reference vector reverse value, Ȧr is the angular frequency of the LC resonance.
whose phase is zero degree, the vector of resonant current is Assuming that x=0.95 and m=15, the fig.9 and fig.10 are
plotted for the illustration of the new constraint. The fig.9
−7
100 3×10
Unit:
degree 80
−7
2.25×10
60

θ ( Q) 40 Tfalling( Q) −7
1.5×10

20
−8
7.5×10
0

− 20 0
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
Q Q

Fig.10. Impact of Quality factor on: (a). load angle ș, (b). the time of resonant current falling to reverse value

t [100ns / div]
a. ZVS failure @ Td=90 ns
Fig.11 Waveform for ZVS realization under different dead time
shows the maximum dead time limitation with relation of
quality factor Q and input voltage Vin. It is demonstrated that
the maximum dead time decreased as the quality factor and
input voltage increased. It indicated that ZVS will be lost more for studying abroad from China Scholarship Council.
easily under high resonant frequency and high power
condition which leads to a high quality factor potentially. The
further verifications are shown in the fig.10. As the quality
factor increased, the load angle and falling time of resonant
current both becomes smaller, which means much smaller
margin is left for the dead time.
IV. EXPERIMENTAL RESULTS
The prototype is designed at 1 MHz and 1.5 kW. The
quality factor of resonant rank is designed as 0.4. From above
analysis, the maximum dead time for the prototype under
600V input is 80 ns. The fig.11 shows the waveform of the
ZVS realization under the two different dead times. Fig.11 (a)
displays the ZVS failure under 90 ns and the waveform is the
same with simulation that the reverse resonant current will
recharge the Vds before the switch turns on. Fig.11 (b) shows
the ZVS is realized under smaller dead time 70 ns before the
resonant current goes to the reverse value.
. design methodology for LLC resonant converter," in Applied Power
V. CONCLUSION
Overall, the conventional ZVS constraints neglect the
limitation of maximum dead time under high resonant
frequency and it’s not comprehensive consideration. The
proposed ZVS boundary can predict the ZVS realization
accurately under the high resonant frequency and high power
condition. The simulation and experiment all demonstrate the
new constraints.
ACKNOWLEDGMENT
This work was supported by Boeing Company. This work
also made use of Engineering Research Center Shared
Facilities supported by the Engineering Research Center
Program
s of the National Science Foundation and the
t [100ns / div]
b. ZVS succeed @ Td=70 ns
Department Of Energy under NSF Award Number EEC-
1041877 and the CURENT Industry Partnership Program. The
author Ren Ren gratefully acknowledges the financial support
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