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A Novel Method for Synthesizing an Automatic Matching Network and Its

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Article in IEEE Transactions on Circuits and Systems I Regular Papers · October 2011
DOI: 10.1109/TCSI.2011.2112830 · Source: IEEE Xplore

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011 2225

A Novel Method for Synthesizing an Automatic

Matching Network and Its Control Unit
F. Chan Wai Po, Member, IEEE, E. de Foucauld, D. Morche, P. Vincent, and E. Kerhervé, Senior Member, IEEE

Abstract—We present a novel method simplifying matching net-

work synthesis and design based on a tunable low-pass matching
network topology. This method exploits the Smith chart in a novel
way. Analytic expressions for calculating the optimal matching net-
work for automatically adapting the load to the source impedance
are derived. This work is applied to a new antenna tuning unit
concept able to calibrate the system in a single iteration process
reducing strongly both the speed and the overall consumption of
the antenna calibration module. The obtained matching network
nodal and load quality factors are analyzed and the matching net-
work efficiency is evaluated to highlight the impact of the imper-
fection in the design. The simulation and experimental results are
presented to validate the proposed method and to evaluate the ob-
tained matching efficiency. We perform reflection coefficients less
than 30 dB, high efficiency matching networks with only 258
s to calculate the proper state of the tunable matching network
under a processor delivering 40 MIPS of performance. Fig. 1. Architecture of the automatic matching system.

Index Terms—Antenna tuning units (ATU), impedance trans-

formers, matching network, control unit.
I. INTRODUCTION
ADIOCOMMUNICATION modules are widely inte-
R grated into handheld or portable devices to exchange data
like in mobile phones or in biomedical implants. The antennas
used in such modules are typically narrow bandwidth miniatur-
ized high-Q antennas [1] easily detuned by unpredictable near
field environmental factors [2]–[4]. Mismatch of the antenna
impedance significantly degraded the power efficiency of the
radio link.
Automatic matching networks are therefore developed to
match any change in antenna impedance to power source
impedance in many RF applications. Most of adaptive antenna
impedance tuning units were developed operating iteratively
[5]–[14] to match source and load impedances. This approach
matching time, approximately equal to several hundred mil-
liseconds, is strongly affected by the iterative process and is not
well suited to low power applications and is also an obstacle to
Manuscript received July 02, 2010; revised November 19, 2010; accepted
January 04, 2011. Date of publication March 10, 2011; date of current version
September 14, 2011. This work was supported by ELA Medical Sorin Group.
This paper was recommended by Associate Editor Y. Massoud.
F. Chan Wai Po was with CEA LETI MINATEC, 38054 Grenoble, France. He
is now with ISEP, 75006 Paris, France (e-mail: francis.chan-wai-po@isep.fr).
E. de Foucauld, D. Morche and P. Vincent are with CEA LETI MI-
NATEC, 38054 Grenoble, France (e-mail: emeric.defoucauld@cea.fr,
Dominique.morche@cea.fr, Pierre.vincent@cea.fr).
E. Kerhervé is with the IMS Laboratory, 33405 Talence, France (e-mail: eric.
kerherve@ims-bordeaux.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2011.2112830
1549-8328/$26.00 © 2011 IEEE
the high speed reconfigurability consideration for future radio
developments [15].
A fast and accurate way to automatically match a system
in a single step was developed in [16], [17]. The architecture
of the single step automatic matching network is illustrated in
Fig. 1 and its interest on an application was presented in [16].
A generic detector made of capacitor is inserted between the
power module and the tunable matching network. The sensed
signals and are attenuated for linearity, down converted
to a lower intermediate frequency and analyzed by a processor.
The benefit of the proposed architecture in Fig. 1 is that the
different modules used for the design of the antenna impedance
tuning units, in particular the down conversion module and
the baseband processor, are already included into common
radio transceiver architecture. Only minor extra hardware is
therefore required. In addition, the power consumption of radio
communication modules is dominated by the power consump-
tion of the power amplifier during the transmitting path and
by the power consumption of the low noise amplifier during
the receiving path. The extra power consumptions from the
computing unit and the extra hardware are very small compared
to the power consumption of the power amplifier. Since the
antenna impedance calibration is done during the transmitting
mode as described in Fig. 1, to achieve low power antenna
impedance tuning units, we reduce strongly the time required
for the calibration. We achieve therefore so fast calibration
that the extra power consumption from the extra modules is
completely neglected. At the end of the calibration, the extra
modules are switched to the idle mode.
As described by the flow chart in Fig. 2, the processor ex-
ploits the magnitude and the phase of the sensed signals to first
calculate the impedance and/or located in the left and the
right port of the detector, respectively. Finally, the extraction of
2226 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011
Fig. 2. Flow chart of the antenna impedance tuning processor.
the antenna input impedance exploits the well known deembed-
ding techniques to calculate from or . The obtained
antenna input impedance value is used to directly calculate the
parameters of the matching network to reach the proper state of
the system at a selected frequency. The success of the optimiza-
tion or the calibration with arbitrary source and load impedances
is achieved with a single iteration. Since iteration is avoided,
matching time is strongly reduced by more than several hun-
dred times compared to common iterative optimization method
[5]–[14] to achieve high speed reconfigurable system and low
power consumption. This concept is obviously well adapted for
the evolution of wireless communications towards cognitive or
software defined radio where the parameters, in particularly the
carrier frequency at a time, are dynamically chosen and con-
trolled by a flexible baseband processor [18].
However, the calculation of the parameters of the optimal
configuration of the network that matches the extracted antenna
input impedance to the optimal source impedance is difficult.
Indeed, classical methods based on the study of the transfer
function of the matching network were first investigated but
lead to heavy calculations that contribute to increase the pro-
cessing time limiting the reduction of the calibration speed and
the overall power consumption. To optimize the process, it was
necessary to develop a novel method for synthesizing an auto-
matic matching network quickly and easily.
Here, we propose a new approach to achieve the process with
simple analytical expressions. By reducing the complexity of
the algorithm, the number of instructions and the required time
to calculate the optimal configuration of the tunable matching
network strongly decrease when the algorithm is implemented
in a common embedded synchronous DSP, ASIC, or FPGA
with memory. This approach also lowers the required memory
size for the algorithm implementation into synchronous or asyn-
chronous control units.
Since the goal of the automatic matching network design is to
optimize the power efficiency of the radio transceiver, we also
propose in this paper to study the power efficiency of the de-
signed lossy network. Indeed, a well matched network can con-
tribute to generate high insertion loss in many RF applications.
It is therefore very important to highlight the parameters of the
Fig. 3. Matching network with complex source and load impedances.
matching network that impact on its power efficiency in order
to discuss how to improve our design. Based on the study of the
quality factors, the efficiency range of the automatic matching
network is therefore presented to evaluate the performance of
the obtained matching topology.
So, in this paper, we present the analysis of the automatic
matching network and its design method in Section II. The
quality factor and the efficiency of the automatic matching
network are then evaluated in Section III. In Section IV, the
analytical results are discussed and compared to the simu-
lations. The experimental results highlighting the achieved
performance of the algorithm and its application to adaptive
antenna impedance tuning unit demonstrator are presented and
discussed in Section V.
II. AUTOMATIC MATCHING NETWORK
We present in this section a new design method for auto-
matic matching network. This new method is meant to optimize
the overall performance of the control unit of the single step
automatic matching network presented previously in [16]. Our
study uses a low-pass tunable matching network to approach
the design. The design includes a network transformation, the
choice of the inductance value and the matching network de-
sign method.
A. Topology
In ATU applications, a tunable matching network is needed
for its ability to adapt a great number of load impedances or any
change of load impedance to the source impedance.
The generic low-pass tunable matching network shown in
Fig. 3 is chosen as the starting point of our study. As in many
impedance transformers or ATU applications operating from
400 MHz to 2.4 GHz frequency band, the inductor is not tun-
able. The tuning ability of the matching network is provided by
variable capacitors made of diode varactors or banks of switched
capacitors.
B. Matching Network Transformation
In RF applications, source and load impedances to be
matched are usually complex. The first step in the proposed
method is to transform the complex source and load imped-
ances into real source and load impedances. The rationale
behind such transformation from complex to real impedances
results in the fact that the best and the worst cases that affect
the system can not be identified easily while exploiting the
range variation of the complex load impedances. This analysis
becomes evident with transformed real load impedance range
where the minimum and the maximum real load impedances
are identified. Thus, such transformation simplifies strongly
the design of the optimum values of the matching network, the
CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT 2227

Fig. 4. Transformed matching network with real source and load impedances.

analysis of its quality factor and the study of its power transfer
efficiency. The transformed matching network topology is
illustrated in Fig. 4.
The transformation consists of three steps: i) extraction of se-
ries-leg quality factors; ii) extraction of the transformed source
Fig. 5. Dynamic range of the impedance tuner at 2.4 GHz depending on the
and load; iii) analysis of the equivalent shunt variable capaci- inductance. (a) L = 2:5 nH. (b) L = 1:7 nH.
tors.
We can define the series-leg quality factors and of
source and load respectively by area can be matched to the source impedance; whereas it is im-
possible to match to the source impedance any normalized com-
plex conjugate load impedance located in the forbidden region.
(1) To avoid this type of scenario, it is necessary to correctly set the
value of the inductance in order to obtain the configuration il-
(2) lustrated in Fig. 5(b) where the complete normalized complex
conjugate load impedance variation range is included into the
The transformed source is a resistance in parallel with impedance tuner dynamic range.
capacitor For our study, we first apply a matching network transforma-
tion as described previously to achieve the matching network
(3) topology illustrated in Fig. 4. It becomes therefore evident to
identify the maximum and the minimum load impedance that
(4) affect our system. The range of the transformed and normalized
real load impedance which varies between and
Similarly, the transformed load is a resistance in parallel is illustrated in Fig. 5 by the bold lines.
with a capacitor In general, at a given angular frequency and neglecting
the self-resonant frequency of the elements, the forbidden circle
where load impedance can not be matched depends on the in-
(5) ductance value and its diameter is given by
(6)
(9)
The equivalent shunt capacitances and are expressed
as follows:
The inductance value should be set carefully in order to match
any value that could affect the load impedance. Indeed, the for-
(7) bidden circle diameter should be smaller than

(8) (10)

Thus, for our single-end matching network topology, in order

C. Choice of the Inductance Value to have the ability to match the load variation, the value of the
chosen inductance should be smaller than the inductance max-
The dotted area located in the Smith charts in Fig. 5(a) and (b)
imum value which expression is derived from (9) and (10)
illustrates the dynamic range of the impedance tuner in Fig. 3
as
simulated at 2.4 GHz frequency with 50 source impedance
using respectively an inductance value of 2.5 nH and 1.7 nH.
The capacitors values vary from 0.2 pF to 10 pF with a 0.2 pF
(11)
resolution.
Let us consider an example of normalized complex conjugate
load impedance variation range represented in the Smith charts where , the transformed source real impedance, is constant.
in Fig. 5(a) by the semicircular shape. Any normalized load , the transformed load real impedance, can reach a value
impedance whose complex conjugate is located in the dotted between min and max .
2228 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

expressions of the curve 2 in the impedance domain and

in the admittance domain are

(14)
(15)

Step 3: The node belongs to the curve 2. Moreover, the

real part of the admittance of is equal to the real part of the
admittance of the normalized load . As a result, we obtain
the following equation:

(16)

When the inductance quality factor is high can

be neglected and (16) is reduced to the following second-order
Fig. 6. Transformation diagram of the impedances of the matching network. equation:

(17)
D. Matching Network Design Method Step 4: In general, the quadratic equation (17) has two roots:
and
We present a novel method strongly reducing the complexity
of the matching network design, providing a quick and easy
(18)
calculation. It exploits and approaches the Smith chart shown
in Fig. 6 in a novel way.
We simplify the analysis by using the transformed matching (19)
network shown in Fig. 4, where source and load impedance
values are real. The impedances are normalized assuming the The solutions depend on the normalized real load impedance
characteristic impedance to be defined in (3). The goal is to , on the normalized inductance value and on the angular
match the normalized impedance to the normalized source frequency . Since (19) can lead to negative optimum values of
equal to 1 and localized at the center of the Smith chart. the variable capacitors and shown in Fig. 3, only (18) is
The steps for matching the normalized load to the source selected as the unique solution.
are as follows: Step 5: The admittance of the node and are obtained
— Since is in shunt with the load , the normalized from (12), (15), and (18) as
real load impedance moves in the clockwise direction
(20)
on the admittance Smith chart until .
— The next element is a serial inductance . We rotate in (21)
the clockwise direction on the impedance Smith chart until
Step 6: The values of the capacitance and are given
.
in the admittance domain by the move from until and
— Finally, the shunted capacitor is designed to reach the
from until , respectively
final matching goal located at the center of the Smith
chart.
The steps and the analytical expressions to calculate the op- (22)
timum element values of the tunable matching network are pre-
sented below:
Step 1: The node is on the curve 1. In general, we can (23)
consider the capacitor quality factor is high . Therefore,
the parasitic resistance of the capacitor is neglected, the Step 7: Using (7), (8), (22), and (23), the capacitances and
analytical expressions of this curve in the admittance domain , giving the optimal configuration of the matching network,
and in the impedance domain are given by are calculated

(24)
(12)
(25)
(13)
Finally, after transforming the matching network and
Step 2: If is the normalized expression of the choosing the inductance value matching the desired load range
inductance and is its normalized parasitic resistance, the to the source, the matching network design algorithm can be
CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT 2229

Fig. 7. Multistage variable matching network.

implemented using only the analytical formulas given by (18), Thus, we get the intermediate real impedances of each stage
(20), (21), (24), and (25). These formulas can also be used to by exploiting the following equation:
calculate the necessary variation range of the capacitors and
suitable to adapt a variation range of load impedances to
the source.

E. Multistage Matching Network Design

(27)
A multistage matching network is sometimes preferred to a
single stage topology for efficiency consideration, especially
when the impedance transformation ratio between Similarly, as , we can write
the load and the source impedances is strong. It is demonstrated
in [19] that the optimum number of stage is equal or greater
than two for a resistance transformation ratio greater than nine.
Having nontunable stages before the tunable one in the mul-
tistage scheme presents the advantage to make the impedance
transformation process in several steps reducing the impedance
transformation ratio of each stage contributing therefore to im-
prove the matching network load quality factor and its overall (28)
efficiency that will be studied in Section III.
To design a tunable multistage matching network scheme,
we propose to insert first nontunable stages before the tunable And the intermediate impedances are obtained from (27) and
matching network as illustrated in Fig. 7. The nontunable stages (28) are given as follows:
transform the optimal source impedance to an intermediate
real source impedance as shown in Fig. 7, reducing (29)
therefore the resistance transformation ratio of each stage. The
(30)
tunable matching network topology, which is a low pass
structure as described previously in Fig. 3, is next designed to
match the variable load impedance range to the intermediate
real source impedance exploiting the matching network III. QUALITY FACTOR AND EFFICIENCY ANALYSIS
design methodology developed previously. Such methodology We analyze in this section the quality factors and the power
is used to convert the complex load to real load impedance (5), efficiency of the designed matching network. The goals of this
to set the inductance value of the tunable matching network work are to evaluate the lossy network performance and to high-
(11) and to find its proper state configuration (24), (25). light the parameters that contribute to degrade its power effi-
For stages network, the values of the intermediate imped- ciency in order to discuss how to improve our design.
ances are obtained by choosing the transformation quality fac-
tors of all stages as follows: A. Nodal and Load Quality Factors
Let us start with the matching node . At each node , the
equivalent impedance can be expressed in terms of a normalized
(26) series impedance or admittance

where and are the transformed real source and load (31)
impedances, respectively. (32)
2230 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

Fig. 8. Low pass  matching network with parasitic resistances divided into two sections: (a) a low pass L section and (b) a high pass L section. (c) demonstrates
the Smith chart with impedance transformation.

The nodal quality factor can be found as the ratio of Consider the low pass L section shown in Fig. 8(a). The ex-
the absolute value of the normalized reactance to the cor- pression of the powers and , entering the matching net-
responding normalized resistance [20] work from the left and from the right, respectively, are given by

(33)
(36)
Similarly, can be calculated as the ratio of the absolute
(37)
value of the normalized susceptance to the normalized con-
ductance
If the right port is connected to the load, the impedance of
the node shown in Fig. 8(a) is obtained from in addition
(34) with the impedance of the series inductance

By definition, the matching network load quality factor (38)

is given by the maximum nodal quality factor. For efficiency
consideration, it is better to keep the load quality factor of The nodal quality factor of the node is easily calcu-
a matching network as small as possible. Considering the lated from (33) and (38)
matching topology with two nodes and as illustrated in
Fig. 6, we can write the matching network load quality factor
as follows: (39)

If the left port is connected to the source, the admittance of the

(35)
node illustrated in Fig. 8(a) can be expressed as the admit-
tance minus the admittance of the shunted capacitance
where and are the nodal quality factors of and ,
respectively.

B. Matching Network Efficiency

In order to evaluate the losses in the matching network, the

initial network is divided into a low pass L section and a high
pass L section networks as illustrated in Fig. 8. The high pass
L matching network transforms the impedance into (40)
with a nodal quality factor . The low pass L section trans-
forms to with a nodal quality factor . The parasitic From (34) and (40), the nodal quality factor associated
resistances are included in Fig. 8(a) and (b). The normalized to the node is also given by
source and load impedances and , matching
node and impedance transformation are represented in
(41)
the Smith chart in Fig. 8(c).
CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT 2231

The parasitic resistances of the lossy components, like induc- With no approximation and no simplification, the expression of
tors or capacitors, used to design the matching network con- the low pass matching network efficiency is
tribute to generate the insertion loss. The losses that affect the
low pass L section represented in Fig. 8(a) are the loss
in the inductor and the loss in the capacitor

(47)

(42)
The initial matching network is divided into two L sec-
tions where the inductors have exactly the same ratio between
their reactance and their parasitic resistance, consequently they
have the same quality factor . Also, the
nodal quality factors are most of the time small compared to the
quality factors of the matching components to avoid high inser-
tion loss. In this condition and for simplicity, we can transform
(43)
(47) into

where is calcu- (48)

lated from (39),
is obtained from (41),
and . For the case of high efficiency, when
If the left port is connected to the source and the right port is , we can
connected to the load, we can write simplify (48) as

(44) (49)

From (42), (43), and (44), we obtain therefore the expression
of the low pass L section matching network power efficiency
as the ratio between the output power and the input power
as follows:
It is well known that the quality factor of capacitors is strong
compared to the quality factor of inductors. For
and , the capacitor loss can be neglected and the
only loss to be considered is the inductor loss. In this case, (49)
can be approximated as

(45) (50)

When the entire inductor quality factors are identical and

given by , the multistage matching network in Fig. 7 achieves
Similarly, we calculate the expression of the power efficiency an overall efficiency approximated by
expression of the high pass L matching network illustrated in
Fig. 8(b). If the left port is connected to the source and the right
port is connected to the load, the ratio between the output power
and the input power is given by

(51)
(46)

where to are the quality factors of L section nontun-

Finally, from Fig. 8 and (45) and (46), the low pass
matching network efficiency expression, with the left
port connected to the source and the right port connected
to the load, is given as function of the network nodal
quality factors and of the quality factors
of the network lossy components.
able matching networks and are the nodal quality
factors of the tunable matching network.
IV. CALCULATION AND SIMULATION RESULTS
The previous sections presented the design method of the au-
tomatic matching network and its efficiency analysis. In this
2232 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011
TABLE I
CALCULATED PARAMETERS OF THE OPTIMAL MATCHING NETWORK
Fig. 9. Flow chart of the matching network design algorithm.
section, we apply the analysis in order to match the load to
the source impedance. The calculations and the simulations are
done using the matching network topology illustrated in Fig. 3.
The results are compared and the efficiency of the designed
matching network is finally verified by calculations and simula-
tions.
A. Automatic Matching Network Design Results
Below, we elaborate three scenarios where complex load
impedance values of and
need to be matched to the source impedance
values of at 400 MHz, at 900
MHz and 100 at 2.4 GHz, respectively, using the automatic
matching network in Fig. 3. The matching network design
algorithm whose flow chart is illustrated in Fig. 9 is executed
by simulation and calculation to set the optimum values of the
network.
The transformed real source impedance and real load
impedance values are calculated using (3) and (5) respec-
tively. The maximum inductance Lmax is calculated from (11).
equal to 32.8 nH, 14.4 nH, and 6.63 nH are calculated
for a chosen minimum value of the transformed load impedance
of 100 at 400 MHz, 50 at 900 MHz, and 100 at
2.4 GHz, respectively. The chosen inductance values should be
smaller than Lmax as demonstrated in Section II. Thus, we se-
lect L equal to 30 nH, 10 nH, and 5 nH, respectively for the first,
the second and the third scenario. The values of are given by
(18), by (20), and by (21). The optimal values of the
capacitors and , allowing maximum power transfer from
the source to the load, are finally extracted using (24) and (25),
respectively. The numerical results are summarized in Table I.
Fig. 10. Simulated reflection coefficient.
The designed matching networks are simulated with ad-
vanced design system (ADS) tool in S-domain and the obtained
reflection coefficients are shown in Fig. 10. The simulations
show excellent results. In all cases, reflection coefficient values
are less than dB.
B. Evaluation of the Matching Network Efficiency
The matching network efficiency developed in Section III is
mainly used to estimate the losses of our design, but can be also
very useful to decide on the topology of the automatic matching
network, in particular its number of stages, to achieve a reason-
able load quality factor Q (35) for efficiency. Typically, the ef-
ficiency of a matching network is function of its nodal quality
factors (33), (34) and the quality factor of the components used
for its design. For high efficiency low-pass networks, where
the quality factor of the components are high compared to the
nodal quality factors of the network, the efficiency of the au-
tomatic matching network is estimated from (49). In addition,
assuming the quality factors of the selected matching network
capacitances are high compared to the inductor quality factors
; the formula (50) is preferred.
The design results obtained previously and summarized in
Table I are used below. The normalized nodal admittances
and are used to evaluate the nodal quality factors and
exploiting (34). The simulations and the calculations are
done using inductances quality factors of
and . As illustrated in Table II, the nodal quality
factors and are small compared to the quality factor
of the inductors. The matching network efficiencies can be
therefore evaluated from (50). However, it is important to men-
tion that the practicability of (50) is limited for high efficiency
matching network. In the case where the nodal quality factors
CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT
TABLE II
COMPARISON OF CALCULATED AND SIMULATED MATCHING NETWORK EFFICIENCY
Fig. 11. Efficiency range of the automatic matching network versus Re(Z
and Im(Z ).
are not small enough compared to the quality factors of the com-
ponents, it is better to exploit the formula (47). Finally, as ex-
pected, the computed efficiency results for
and are in good agreement with the simulations
as summarized in Table II. The maximum efficiency is 98% and
the minimum is 86%.
Next, for a given complex load impedance range to match
to a source impedance using a tunable matching network, we
can obviously predict the efficiency range of the well-matched
network. Exploiting the design methodology developed in
Section II, we evaluate first the node impedances or admit-
tances (20), (21) range of the network followed by the extraction
of the nodal quality factors range from (33) or (34). For high
efficiency network, the efficiency range is obtained applying
the nodal quality factors range in (50) for a given inductance
quality factor. We use this method to match a complex load
impedance range, whose real part can vary from 60 to
260 and imaginary part from 100 to 100 , to 100
source impedance at 2.4 GHz using the low-pass automatic
matching network in Fig. 3. The efficiency results calculated
for an inductance quality factor of are represented in
Fig. 11. We show that the automatic matching network reaches
efficiency values ranging from 90% up to 98%.
The efficiency of a high impedance transformation ratio
scenario has also been calculated and simulated using
respectively a single-stage matching network shown in Fig. 3
and a two stage network illustrated in Fig. 12 to match the
2233
Fig. 12. Two stage matching network with real source and load impedances.
load impedances to the source impedance as summarized in
Table III. In a single-stage topology, applying the design method
developed in Section II gives a chosen inductance nH
and the nodal quality factors and .
For , we achieve a simulated efficiency of 82.5%
and a calculated efficiency from (50) of 80%. For ,
) we obtained in both case a efficiency approximately equal to
94%. The two stage matching network illustrated in Fig. 12
aims to reduce the load quality factor (35) of the network in
order to improve its power efficiency. As illustrated in Fig. 12,
the load impedance is first matched to a desired intermediated
impedance , calculated from (30), using a tunable matching
network. The obtained impedance is next matched to the source
impedance with a nontunable matching network.
Two nodal quality factors and
are derived from the tunable matching network. The nodal
quality factor of the non tunable low pass L section matching
network is given by . For , the simulated
matching efficiency is 90.5% and the calculated efficiency from
(51) is 88.5%. For the efficiency is approximately
equal to 97%. Compared to the single stage network, we reduce
the load quality factor (35) from 11.523 to 3.594, and we
improve the efficiency of our design by more than 8% and 2%
for and , respectively. In general, in single
and two stage networks, the calculation and simulation fit well.
The difference is due to the approximation made in (50) and
(51) to calculate the efficiency.
V. EXPERIMENTAL RESULTS
The simplified block diagram of the automatic an-
tenna-impedance tuning unit presented in our previous work
[16] is illustrated in Fig. 13. The detector module allows the
system to extract phase/magnitude information. The data are
down converted to a low intermediate frequency and analyzed
by the control unit. As shown in the flow chart of the control
unit in Fig. 2, the processor analyses the information to extract
2234 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

TABLE III
COMPARISON OF THE ESTIMATED AND SIMULATED EFFICIENCY OF A SINGLE STAGE AND MULTISTAGE MATCHING NETWORK

Fig. 13. Automatic antenna impedance tuning unit (AATU) simplified block
diagram.
Fig. 16. Measured reflection coefficient: (a) before the calibration routine and
(b) after single iteration calibration process.

Fig. 14. AATU prototype including the matching control unit.

Fig. 17. Postcalibration measured reflection coefficient obtained for different

load scenarios.

matching network. With knowledge of the load impedance

and source optimal impedance, the developed matching network
Fig. 15. Simplified structure of the varactor.
design algorithm in Fig. 9 is executed to set the proper state of
the network. As illustrated in Fig. 16(b), we achieve a postcal-
the load complex impedance. The matching design algorithm
ibration reflection coefficient up to dB at the desired fre-
shown in Fig. 9 is executed to match the load impedance to the
quency of 403 MHz. Experimental postcalibration reflection co-
source impedance applying the developed matching network
efficient has been also measured for different load impedances
design method in Section II.
as illustrated in Fig. 17. We obtained a S11 up to dB at
A first prototype of the automatic antenna tuning unit that op-
403 MHz. Moreover, the synchronous processor spends no more
erates only at the MICS 402–405 MHz frequency band is shown
than 258 s to compute the matching network design algorithm
in Fig. 14. The control unit has been implemented as an Analog
under a processor speed of 40 MIPS as illustrated in Fig. 18 and
Devices microcontroller ADUC7026. The microcontroller core
requires only 2512 bytes of memory size for its implementation.
is an ARM7TDMI, 16/32 bits RISC processor, offering up to 40
The algorithm was implemented under Keil embedded develop-
MIPS peak performance. The tunable matching network con-
ment tools. It was coded in C language; compiled and down-
sists of a low pass matching network in Fig. 3 with an induc-
loaded into Flash EEPROM memory using JTAG interface.
tance and two variable capacitors made of varactors [21] which
simplified structure as shown in Fig. 15. 12-bit DACs control the
DC voltage of the varactors with a resolution of 750 V LSB. VI. DISCUSSION
Fig. 16 shows two experimental reflection coefficient mea- The study and results presented so far have left a few ques-
surements. The first one shown in Fig. 16(a) was done before the tions unanswered, while also opening up new avenues of re-
calibration process in the presence of a detuned tunable low-pass search. We address these points in this section.
CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT
application. The implemented matching network design algo-
rithm takes 258 s to calculate the optimal network and requires
2512 bytes Flash EEPROM memory space in the ADUC7026
microcontroller from Analog Devices.
for supporting this work. The authors would also like to thank
E. Isa for contributing to improve the quality level of this paper.
Fig. 18. Time to calculate the optimal network configuration.
We have shown a method that strongly reduces the automatic
matching network design. It is extremely efficient to match
any load impedance to the source using the matching topology
in Fig. 3. The impedance transformations are performed, the
choice of the inductance is discussed, and matching network
design is achieved with simple analytical expressions. The
expressions are exploited to implement the matching network
design algorithm of a novel ATU control unit [16] whose flow
chart is illustrated in Fig. 9. The resulting algorithm complexity
is low and hence reduces the tuning time. Matching the system
in a single step but with an algorithm of high complexity
has little interest. Therefore, this approach simplifying the
matching process can be considered as a key point of the single
step adaptive load impedance tuning units. This contributes
to reduce the matching time, the power consumption and the
required memory for its implementation.
The load impedance can be well matched to the source, but
the matching network can be also strongly affected by losses.
Thus, we developed the analytical expressions of the power
transfer efficiency to identify the impacts of the matching net-
work parameters, as nodal quality factors and the quality fac-
tors of the inductors and capacitors. Even if design techniques
such as multistage network design are helpful for increasing
matching network efficiency, it is clear that investigation should
be lead in the development of inductors with high quality factor.
Indeed, to improve the fully integration of ATU, the quality
factor of integrated inductors should increase. Moreover, the
variability of inductors is limited today. The use of variable in-
ductors should be investigated in the future to demonstrate its
ability to improve automatic matching network nodal quality
factors and increase the overall matching efficiency. The in-
ductor variability should be not necessary continuous but can
be also discrete.
VII. CONCLUSION
This paper presents a method for automatic matching net-
work design and its synthesis. The method is developed to re-
duce the matching design complexity. The analytic expressions
to achieve the optimal configuration of the automatic matching
network are derived and its efficiency is evaluated. Both simula-
tion and measured results are presented to validate the method.
The experimental results show that a reflection coefficient up to
dB is reached with the presented method applied to an ATU
2235
ACKNOWLEDGMENT
The authors would like to thank ELA Medical (Sorin Group)
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Francis Chan Wai Po (M’10) received the Engi-
neering diploma from Ecole Nationale Supérieure
d’Electronique, Informatique et Radiocommuni-
cations de Bordeaux (ENSEIRB), France, and the
Ph.D. degree in microelectronics from the University
of Bordeaux 1, France, in 2004 and 2010, respec-
tively.
His Ph.D. work was carried out at CEA LETI in
collaboration with ELA Medical and the IMS Lab-
oratory and was mainly focused on the design of a
low power RF front-end transceiver with automatic
power efficiency optimization for biomedical implants. He has since joined the
MINARC research team at Institut Supérieur d’Electronique de Paris (ISEP),
France, where he is currently an Assistant Professor in Microelectronics. His
current field of research is the design of analog and radiofrequency integrated
circuits for biomedical applications.
Dr. Chan Wai Po is a member of the IEEE Cicuits and Systems Society.
Emeric de Foucauld received the Ph.D. de-
gree from IRCOM-University of Limoges,
France, in 2001. This study was focused on
radio-frequency voltage-controlled oscilla-
tors for TETRA-TETRAPOL application of
EADS-Telecom.
He joined the Wireless Division of STMicroelec-
tronics in 2001, and worked on the Frequency Syn-
thesizer IP team as RFIC design engineer. In 2003, he
joined the RF design team of CEA-LETI, Grenoble,
France, and he is currently involved in analog inte-
grated circuit design for wireless systems.
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Dominique Morche received the Engineer diploma
from the Ecole Nationale Supérieure d’Electricité et
de Radioelectricité de Bordeaux (ENSERB), France,
in 1990 and the Ph.D. degree in electronics from the
Institut National Polytechnique de Grenoble (INPG),
France, in 1994. His Ph.D. mainly focuses on sigma-
delta ADC.
From 1994 to 2001 he was employed by France
Telecom as a research engineer. He has been in-
volved in architecture and design of analog circuits
for telecom application. He is currently working at
CEA-LETI, Grenoble. His current field of research is in the specification and
design of RF architecture for UWB and 4G systems.
Pierre Vincent received the M.Sc. degree in micro-
electronic engineering from the University of Mont-
pellier (ISIM), France.
In 1990 he worked as an Analog RF development
engineer and technical group leader in Thomson CSF
semiconductor for space, military, and avionic ap-
plications. In 2000 he joined Infineon Technologies
Echirolles France at its start-up. He was responsible
for setting up the Analog IC development for 40
Gbps high-speed optical network applications. He
joined the CEA-LETI, Grenoble, France, in 2003 as
a design manager and responsible for RF architecture and the RF IC design lab.
He is involved in millimeter wave and RF MEMS cointegration design.
Eric Kerhervé (M’96–SM’09) received the Ph.D.
degree in electrical engineering from University of
Bordeaux, France, in 1994.
He joined IPB ENSEIRB-MATMECA and the
IMS Laboratory in 1996, where he is currently a
Professor in Microelectronics and Microwave Appli-
cations. His main areas of research are the design of
RF, microwave and millimeter-wave circuits (power
amplifiers and filters) in silicon, and BAW technolo-
gies. He is or was involved in European projects,
such as MEDEA+ UPPERMOST, FP6 MOBILIS,
MEDEA+QSTREAM, CATRENE PANAMA, and ENIAC MIRANDELA
to develop silicon power amplifiers and BAW duplexer. He has authored or
coauthored more than 190 technical papers in this field, and was awarded 17
patents.
Prof. Kerhervé has organized six workshops on advanced silicon technologies
for radiofrequency and millimeter-wave applications. He is involved in the tech-
nical program committees of various international conferences (ICECS, IMOC,
NEWCAS, EuMIC, SBCCI) and he was the chair of the international IEEE
ICECS2006 conference. Since 2010, he has been an Associate Editor of IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS.