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    6th Unit DSP

    Uploaded by

    Ramu Saripella

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    © All Rights Reserved
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    G1, Explain the basic architectural features of programmable DSP devices, ans: Thaihardwage features are, (On-chip register to ote ialermediate resus, 2 On-chip memontes for signal samples (RAM). 3. Gchip program memory for programs and fined data Q2. List the basic characteristics of digital signal processor. ae. ro ‘The baie characteris of dig signal procestr ae, ' | Kean 'be used as a direct memory access device in supporting or host enviraaments, 2 Thy lesion cmt mt jl se gu ence ee hg ee, ett hod et tit 3 Te om provide barr ta septs mg, “They aze equipped to handle seal time processing. as. Wa wi ving of OP rcener a lal onl pee procayo? The advantages of DSP processors are, ’ L The DSP jrocesors perfonn tt processing ofarays. ~ : 2 ‘They need only one clock cycle i execue instructions. fi DSP process perp excetoa of ntetinas! . a 4 They have pure progr and data emoren, 2 a4, Daca ieeinanarn fern cpa ng pms ee : Ans: ents, sera, cu + Tw cites ge fem? bglonsi : : 1.” AND enoversion ecm eens. 2. DSeompptina eaart ee . 1 + _ 2 Highly sealable, 4 62 OK What is MAC? Draw Its block diagram. Ane adel Pree aN -A‘Muliity- und Accurate (MAC) nits ween cofewa unis namely mtiply nil end en accurate rey Figure shows the block digs of MAC ail An accumulator tom with seabed Yo wore the proshict, a ‘crema of anquence wf ennsecutive mhipficaion operations ‘which ae require! in apices Maier eu Aqui) inv) ‘Figere:Mahtphy nd Acumulare NACI Unt (6 Expinin muttipie access memory, ‘Ans: Model Papert. Cit) Tee memory that enables atiple acocks per clock pind inrefered tos muhinle access memory. With he help ‘of nigh peed metey, the masber of tetnory scesvesiclock peviod is increased. Two memory accemesiclock perind i said withthe dual access RAM (Random Access Memory). ‘By ung Harvard architect, it i posible to consecteuitiphe RAM t the processing unit of DSP: Four memory accestewebock period can also be vith al sccems RAM, when itis conmected tog programmable DSP with (wo separate addres and data buses. QT. What are the advantages of VLIN architecture? sare - Agree, Bebe, 7) ‘Note: In queriion VLIW is misprinied as VLIN, ‘The adeantages of VLIW architectre we, Pexformance s high. ary wo program. ‘More unter of ezeation units tan be wed allowing DIGITAL SIGNAL PROCESSING LJNTU-KAKINADA] 8, Listihespecial sddressing modes and on-chip pperlpherals of programmable DSPs, (or List the omschip perpthersi, set. 203. dans ‘Spectet waitreming modes The epecinh eens meles of prayrammabie DSPs ae, 1 Short meskes 2 ‘Shoetiiectsddeising 3. Memary mapped siddenng 4 iret ndcesing 5. Bitrevered addressing. 6. Circular ndidresting. On-chip Peripherals ‘The on-chip periptrerals of programmable CSP: arc, On-chip timer Seca port 1 5, 3 4, S. BRVO ports 6 1 a -Aefo-Dand Dito-A converters, ‘Q10, Explain the role of on-chip peripherals for Programmable digital signal processors. Aste, S04 OH “The fimctions performed by onchip petiheals ar, 1. The feature af with exemal devices like Ans: increased lengrh of instruction in VLIW. Of. What are the cifeent stages in piping? rede wal wag dial cooveers spose ‘using o9-chip peripherals ; 2. ‘Onchip petipherss iso contibute fetures that are ‘ecessary in val time syatern plementation with the _ Melpetpreemon. : 2 at or nein my ai _ ea carseat Seen eee er P| OP ele UNIT:6_inireducton To DS? Processors and Architecture of TMS'32005%) a G17. Mention various generations of digital signal processors, wes Ans: arn 3 “The various generations of Uagtl Signal Process (TME120) are, a Ls masraacix, 2 Tasizecax 3._| masniecax 4 TasmIC 4 TMsIICE. & TMsiecex 7. Twstzecex - ‘Here, C1X reprenent fet peneraon; C2X represents second peeration, ee ‘The TMSSINCIX, C2X aod CSR are 16 i fe point procerney and TMS IIOCHY i he vance ‘The FMSI20C1K, 4X are 32 bit luting point processor G42. What are the functional units present in the TMS320CS4XX processor? Shi é “The flowing are the Fimectional wats that are present in TMS320CS420X pmcesne. eb ALY s0.bic Accumlatory i ; Barre shiter ‘ 17 17-bit mubiplier ‘CSSU (Compare, Select ant Store Unit) PPsa Ree ee O13, Write any four features of TMS320CSAX processor. i" ean ‘Ust spectal feature of DSP architecture. Ane: - ‘Theatres a TASSIOCSAX proms, ‘The pecformmee af TMS320C54X procemor in high. » “TMS320€54X ina Sow power consumption processor, 5 Fapiain wuniiary Tegisterin TMSancgy FAISELOCSN as tight stniny eq, ee r fepiters da nul (CALL) to AR ait pt Ut (CAL tol cpr NE AWN arrused ig Uni (ARAU). These i, Pati poist proce ofe high seca wa : Ysera ane namic ‘on-chip peripherals of TMS320C5X processor — etipberals of TMS320C5%, prcesiar are: O17. List eile Meee features se in DSP aytom to achieve high Sore program execution. Ans: eet, St, 7) {Digital Signal Peacewning (DF ckiectore thee 8 Meatucce ae to be woesedered, 1. Architecture of Jw! ot igh sped ef operat Tce hi, the flown There ate algelana for process snl ht coo unpler ‘os speaks fare sacl functions noe la be performed processing tn, sao, cps ed peta ifecture edd fa tga! Piss pombe desing haniware cuca sb a Ube wing al ier io pertsrea ‘opemiie that eaeeated witha co clch pul. Likewise, iflereethaxvary unc are deugsed ro ‘has decreasing the eprasing cost a acta high peed Program execation el inhigh in barend arcsec, ince roam merry i alae rom dinar by petng tndividual bases foe both. When (here are two data inemorees, operminds can be accessed fron iadividhaal memories wt 9 tune, by roving two separate bass, Insead of axing extemal memories that need e » ome its Pes ete ig oy ; Modi aren emcee so coe ote sd bas, cower be a ee it ero im na UNIT-6: (Introduction To DSP Processors and Architecture of TMS320C5X) ‘G23. Explain why traditional measures such as processor clock speed, MIPS and MFLOPS may nelle suitable for comparing the execution performance of OSP processor. Suggest, with justification, wa alternative method of comparing execution performance Ana: er hme In DSP processors, rhe metrics like processor clock speed, MIPS TMiliioas of Instructions Per Second] and Mi [Mitton of Flosting-Point Operations Per Second] are nat suitable neanwres for comparing the extcution performance, ‘mingle gbtuetion is of 8p lerttve operation and fs, requires mors memory and eoraumes mors time. Hone, uch drvebocks an altemutive mets cael benching is triply! for comparing the execution performance, DSP is software program used 9 measure the performances and tix opted due to the following reasers DSP benchmark i writen in 8 high level Inngume end hence bt portable 2 Repossess wide distribution 3, Tan enmity represent the type of programm like ystee, commercial or numerical G24. Explain the different techniques. adopted for incre eycle, “The various techniques that are wed to increase the mumber of memory accesseslinstraction cycié are ax follow. Maltiple Acces Memory Fox anewer refer Unit-V1, Q6. Maltiported Memory Multiported memory izalso used ta increase the muner of aceessesclock peri. The basic diagram of a Sul-per sis shown in the figure below. Adiest ba Dama ‘Adress tact Daw 25. piso the VLNY architecture wh fs Block apres : Ans: ‘VLIW [Very Long Instruction Word} irchinectine is used in programmable DSPs such xs TMS32008% and it Som the memory. The basic Hock diagram of VLIW architecture i shown inthe igre below. 12 DSP application and the muses | ‘f fmetions) unite decide the ‘ ‘ performance of VLIW ‘ashitectire. However, the higher throught of VI LW architecture can only be achive i fo nein wigutg encates G28. What ls the necessity of pipaline operation la DSP processors? Ans: sod programing ste teed By increased pipelining ‘plified. The problems i th prograsn eich, mutply operations and data seca, The three sages of pipeline phase are, 1 Feu 2 Decode 3 Enecute The number of pipeline ines 0g seaeeac phases required by all he instructions are same for fetch and decode sages 2, four ba, for ‘The fou pipeline phases of fetch age ae, : (0) Program address generate: v oe (i) Program address send (il) Program access ready wait us), Program fetch packet recerve, ‘Exght instructions are used by the (ich paickot of tbe processat. The fetch processing is used for procooding of all tag tnstructaons together through the four pipelme phases of the fetch vuge, Instruction dispatch and insruction decode ae the pipeline devode phases. Te fetch packets inthe istction dispatch phase ofthe pipeline dood are pitino execu packs The source registers, destination registers and associated datapaths are decoded inthe instruction dec pus of th pipeline for the execution of instructions in the funcponal units Qa7. What are cfferent steps required to execute the DSP program? ; are Ans: ‘ nt “The following are the differnt step required to create DSP om : ‘ “: 1. Allthe imerrupyy are disabled and DSP hortware i initiate, Boe a ‘The DSPYBIOS modules are initialized. | Ms section ck) poet topes Mo Oj mated wal ONS = Initialization fanctions are also called. . os pspaios enabling | ‘Fubrnore, the lock wed by PRD th is all he bardwore and software itecrupas Fas SA ene eee SS i eich enone mae “The DSP/BIOS loop i cared aller completion ofl eS td aatetar the SLA GROUP led ws peline thes a & | rT at UNIT-6._(iniseddetion To BSP Processors and Architecture of TMS320C5X) 6.13 ‘O22. Explain the various pipeline programming madols that aro adapted! in DSP processars. secs Sta tl (oh Explain citterent pipeline peagramming modais that are adaptad in DSP processars? Ans: ‘sv 8 Set a ‘That are two important pipelioe progaammning model for pipelined procensnes. They are, 1 Tie-saioauy peoyransning mode 2. Dateststionary programming model ‘Thus programatniag models are ts assembly cone formal 1. Time-stutiouary Programming Model 1h time-taticnary model, instructions are spedied such that they contain all information that ix necessary at gives prs ee orogeny a aatcpnsen mr is shown below, adaaep paxty yet pa ttt wW=a0+p + Accumulator adds repistr “ps its current list P + Multia the registers x and 3: ymtO++ +The result is lod in the product register. Betptt+ px and yegistere are loadod yaues atthe mamory locations of registers 0 and pt. 2 Datastatlonary Programing Made {n data-stationary miodel, all information related vo all processing aspects of a ingle data item are specified mone ant the sume imtruction imspective of ting when the processing ia cared out. The eel coe Frm of dan stlonary models shawn bet, i almal ¢ (iSretebeytt eh oe . . > ies | 2 a ay i oe ca a informatica wpe in rations. ; Ye tan ae pn ety ln Nag ln Br stationary cudel is easy to implement. 028. What ar tho imitations of pipelining in digital signal procossor? H The itary ef wart pling te, rr o : ie Thee ppm ina ei nt npn a ene ee 6 sxe bangs 0 iter iste etlestive execaion “ le conti stbekencon ert ‘meat ace eer 3 Sie dnt ca tec eset 4 Therese nance cums mre ie ao nel outa tins, eR AoE FR LTERRERTEATO——————aneaTe = +__ DIGITAL ISIGNAL PROCESSING LINTU-KAKINADA} pm ee ‘034, Explain the special addressing modes In progeammabia DSPs ‘ened Pape. (on Describe any four data addreesing modes of THS120¢%40x processor. Ae 1,902.970) aw a (on ‘Wh examples explain the iiterent nddrenting formnts supported by DSP processors for various tp ‘Signal procesaing applications. os poe, o764 = fon ad ‘What ae the various mdsressing modes used inthe TMS320C5K processor? =f sare a wa 2 Expinin in detail the circular addressing mode and blt-reversed addressing mods, ar . ‘ ‘Apt. 18, Set, OTe L Ans: ~ , “The progeemmable DSPs support six types of opecal addressing modes. They te, (Short tminedinte Addressing . In short immediate addressing made, te opersnd is considered na short constant whose length relifsoe the programmable [DSP and he iwtruction type. The shart coestaconstintes a parton of single word instruction. For example, nn 3-bitcomstnt ° in TMS320C5X is Considered ax an operand in tingle word instructions suchas AND, OR, mdition, subtraction et. (1) Short Drrect Addreming i : {in short direct addresting mode of an instruction, the lower order address of thé operand ix mentioned in the single word instruction. Inthe cave of Texas Instruments like TMS320CXX DSPs, the dana page pointer stores the higher 9 bits of the memory ‘dress anda portion of te instruction is specified bythe lower 7 bis, An insruction inthe Motorali DSP S600X is specified swith. fbi address ming hort inet adeesting : : (iE) Memory Mapped Addressing * Ts memory mapped ikrssing mode if CPU registers and the UO registers of programmable DSPs ae stored atthe ‘pinning or end! of the pape in memory space, then, ey can be accessed as memory location, i ‘The CPU registers aed UO registers restored at page 0 if TMS320CSX and a final page with 64 locations in Motorola DSPSSOOX. Using temic mapped mddtssing mode, these register are accessed with higher adress bits making 2g in Texas ‘insrument DSPs md | in Motorale DSPs, © Indirect adreasing made in programmable SPs allows n ary of data to be proeaed eflztvely by fching and ‘oring. Any one of the indirect addsess registrt (also called as mutiliary registers in Texas instrument processors), is wed 10 se the ora ade. When an witional ALL spe in the CPL core, the sin onde adress repater: which at wed ia operand fetch may be updated. The incrtment or decrement of wuxiimy registers is oe cither in single sep (in steps of |) or pacified steps of oflset register content, The offset register in Texas instruments ix known as INDEX register J ‘whereas in aati devices of programmable-DSP"s, tis known as modifier vegisbtThe updated adres of wuxiiary ALU ta wed to fetch the unable indirect dressing mode operand instead of current. instruction operand that is performing dccode and execution operation, Hence, in Texas instruments 5X DSPs indirect addvewing mode is refered to a8 indirect addressing mode” ‘with post incremeatidecrement: In contrast 16 Texas instruments, Motorola DPS5632X et updated address oetch he current” |} __ instruction operand. This is called as indirect wbdresting mode with pré-incrementidecreaert. Texas instr apport both post and pre inrement/decrement. ale ; aaa an z= ar BERR S RSE sae UNIT-6_ {Introduction To DSP Prooessbt’aha Architecture of TMS320C5X) (*) Bit Reversed Addressing “pacts Gecial mabe converted nto nbinary Sumber by writing te revere order ofthe nat! binary of the mumber. Therefore, the lenst significant bi af the bit reversed number changes to most significant tof tha fmamber and vice vere: In this ndtreasing mode, the bit revered mumber increases or decrees the adress, (v0) ChreabirAddrening [In circular addreesing. the menocy contininialy sores the ing signal for real time gal pressing: The {2 procemed it constantly stored in ther metoey kpice which can be inserted ont the ovtyu device. Her, the vat program i very simple with limited size. Hence, with linear mktresing mode, wea te dia is copied the (np signal is processed, the total memory space isappenrs afer cme period atime. En order to-overcene thin, verification is require to check the Fmt wich i ntevethced.A circular bir cinelareresting mode rece tha pg ‘by ting starting and ending memory atresses. When the adres poster peta incremented, ts omer with address. IF itis more than the ening, memory addres, then the bering adrcas in allot tit rat an a en-ehtn petyrereh Weaken rocremmntin del sire proceceal their tunctions? : Ans: ‘The on-chip peripherals available on programmable digital signal processors ae, 1. On-chip Timer Gn-chip timer ig one of the peripherals available on programmable DSPs. This on-chip timer is Programmable DSPs. Most conimon apptications of on-chip tisers are, (f) , Periodic interopts poeration tothe programmable DSPs. _ (b) Sampling clocks generation for the anslog to digital converters. Actingle pulse or a triin of pulses and a singe square wave or a periodic square wave ere geoerated by Serial Port i rena pela alpen elbbmareseae) or usehemr espe oly tral nd receive data lines are wed. In this ease, from ether cos, bit clock: ts transmited, _Mmowemner DATA ie ee eee wa aa yet te UO dv te Haring oe ib itt id epresented by bit clock signal and fame syacbromous sig 616 TOM Seri Port ‘A special sera! port of te poy DIGITAL gig Sana Aas! set tam re ir, shamugh TDM serial pot are, Se Fre ae eral rej, 2 The bit eloek (TCL 3 Me ake ofthe el dye 7 = detain Foe ati ey TC 4 Patel For k : Bera eat ner ‘The differen approaches to assign the lines fr parle! por ae, * (i) The data bus itself is used for parallel port 1H) Separate ines (including the habahng sgl) red fra pot S Bit VO Ports Me aia 0 pe era 0 tea fp Single bit wide | : es (G) Operated individually ; : Do not have any haadsaoking signals The pro eionsinatspren tia ; ; 6 Hast Port ae an ee es 4 The ftins of host por as, = ey 'Q32. Explain the features of TS320C54X OSP processor. 1 Tas DSP Processors and Architucture of TMS320C5X) 617 1s aad ary bits wide. The oo ces system. Programm posts are sed fa at ns on sag devices and Tena sen are 6 08 cecum port Exaniple; ADSP 2106X, Aste p-te-A Convertars The P-DSPs which are wid for voice applications Ike ancctingtnichines, motes et, have um. chipA-to-D aca D-boA converters Example; Motorola DSPSGEXX, ADSP 2UMSPSX. In syctronow mod, te Wanuminsin o tit clack signa wn fame eichroncas sal efor UO port the al por and serial port the 1 device, The starting ofthe at it ofthe ta a is amend in rocteonocs be Tepeeueed by bit lock signal and ame sychranows Signal ‘The flowing are the features of TMS320CS4X DSP processor, The! penn at NE eee is bight TMS120C54X isa low power consumption proces. : tarantino hic pier etd ise eaon ott i wane en i ni seramleto. sendin ei ine lara pte rents Cnn ae tn Gp at : ‘nape pen bea pm accumulator during ie clack ele. pes psn wy lind os my Rag ti a RA ‘ thas dt bs with weak ack rt (bbe) capi, Whi old is pv yale J ° “es t0C 0% promo roi singe ation pea and nk erat pats preg cde = foe a oe ala oueageriet el ohec iat wrasin Bat e penrtn lope any wi ep a pei wteeregmni eps mpeg hg ; e 6.18 DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA) a ——___PIGITAL SIGNAL PROCESSING [JNTU-KAKINADA) 283. Draw and wxptain the major Block diagram of the TMSI20C3Y. Aoi e89,2r9) (or) Draw and explain the memory archhacture of the TMBI2063X procussor. Ane: Aest-A8. Bet CMa igure) shows the itera! wehietune OC TMSIDUCTX pecan: The tb Mocks of TMSI2003% [Prneecnon are, 1. Ceniva procensing tit 2 Mermiey nit 3. Pevinberns DMA commolier ‘Central Processing Unit (CPU) UNIT-6 (intreduction To DSP Processors and Architecture of TMS32005X). (_Toteger and Floating Point Matiptier cycle, Parafel rmaloply and arithmetic logic unit operations are erred by parallel instructions with in a ringles (10, Haternal Bases for every machine cycle. REC ao! RIG? are tho Fates internal ty the CPU. (UD Integer and Flosting Potat ALU Atiormetc and logical operations are pexformed hy ALU! Single cyce integer a fasting conversions are LyALL, The integer am outing point ALL nfwnya mainiin results at 40-bit Hotingpit or 32-8 integer dv) Barrel Shifter ‘The operands are shied pts 12 bt ight o.12 bits left ina siege eye by barrel sii (o)Auniliry Replrter Arithmetic Unlts (ARAU) : ‘The miliary regis arthoecic units of TMS320C2X processors are ARAUD and ARAU. Theo addreses ie ger by ARAUO and ARAUI in a single cycle, Generally axilary register arithmetic units operated parallel with smuhipieinfiect addresing mode i wed by ARAUs, Ciular and biteeversed addressing modes also auxiliary register arithmetic units. (re) CPU Register Fite ‘The CPU register file of TS320C3X family processors sve 2E mpistr ina maltiport register. The CPU reginr files ere, re Serer rws ti vs aeeeTE4Ss 2 Memery Unit _ Thememory unit of TMS320C3X family eonatsts of afte 32-bt nod oul ee a ear chip ROM, RAM and cache. TMSI20C3% ‘the intemal architecture ‘of TMS320C3X, the RAM block0 have IK # 32 for C30 and C31 family and 256 * 32 for Drocesoor. The RAM block have 1 K x 32 for C30 and C31 processors and 256 « 32 for C32 processor. The ROM! 4K x32 fot C30 processor and bootloader in C31 and C32 family processors. DyRAM and ROM kT ofofEchipxcoes ee eed y beet enoee oe 320CH processae TMS320C92 process uit son pepe ax commana bas er candaar cx nan DIGITAL SIGNAL paces, SING pec bs awe Di ct a Proesos, Perri 12 pel ts id ‘te cerry map DMA cootclers ae wed, es bu aes the DMA UNIT-6 _(Inirodvotion To DSP Pi G24, Discuss in datall the Basic Architectural features of programmable OSP devices, fede scr {or} Explain with the help of black diagram the architecture of TMS320C5X processor. 4 Describe the multiptier/addor ynit of TMS320cS4xx processor with a naat block diagram. paid leacianaa cna fon : Explain the function of Barrel shifter in the digital signal pracessor, aaa ; poner Ans: ‘Tie internal architecture of SX family is ws shown in fguee (3). Popesiee ‘Danae penning ‘mac eEsE ot st $22 nara tana pnocessina LNTU KAKADAY 1 Bee Sersetere In oder improve the proces’ in cane to alot a pmimber of buns a dfferent ertions Of memory ar pevhied dole = targa trettoeancn Matacs aah tort kee prond caddies $ETMEDOCSANY preven nit. These bes ae peed forming four ui eeining wires Yu rl cn cach pt ‘The four pairs are (PAB, PB), (CAR, CB), (DAB, DAN) mee (FAB, Ett), ‘The pair (PAB, FA) in Kiwm as pregram bus pir that is ied to tmmeferinstrwction codes frome the program meena. ‘The ote pis (CAM, CH), (CHAN, ae (AR, Foe rere dt tis wth ink flere blo preset in he CPU Alen, deta present in the date memory ca be rbd ang (CAB, CH) ane (DAR, DB) data ex pair where as daca an be eaters dat rensory wring (TAR, EN) taba pt Thee ve tw sary register aithmeric ums ARAL, and ARAL, inside @he dats acktress generation logic (AGEN) nnit with which « marian of two data-memory addrewees can be pertain oe ete Ts tx pombe to noes to oper me L Content Procewing Unie (CPU) ‘The ceatral prncensing (mt resem! in TMS320CS0X0X ts a stenatard CPU etmployed! in ail the proceennn. There are varios iy sem in CFU, Tey re, ©) Acithetic Logic Unit (ALT) of 40-4 {@) Teo Accummior (A A 8) of 40-bit each (i) Pavel Stier (he) Meatintier (17-bit = 1 7-ba0) Wh Ale (40: (ci) Compare, Select und Sure Unit (CSU) (ii) Exponent Encoder (EXP) ‘(vi hata Address Generation Unit (DAGEN} and, (G2) Program Adres Generation Unit (PAGEN), ‘This sit caries out atm opetios involving 2's eompleccel, boolean operition én operands af ‘znd 40-tits length: At atime, it is capable of out é-bits, 12-bits Tie heaton dau efAUoeaner eee: 6b operstions by dvidtg itself into tro AL.Us of 16-bit each. ‘to of Al gargears 23 C8 ints UNIT-6 (intoduction To DSP Processors and Architecture of TMsg20C8X) _Accumuliors (A wad 8) The rei of ALU operation wt Multiplier unit is ord in these accurolatrs tht, forming the veo inet of ALU unit, There are three section preset in ivi secomalatns (a) Bats for 39 m 32 represent pant its (8) Bleutrom 310016 represent higher onder ite (6). Bits hom 15 w Orepreent lower onder bite 1 in ponsible to wccets exch part of aceumiifster scpamttely (a) Barrel Shier The magnitode of an operand can be scaled up oF scaled dawn while pefering read of wre operations wing aibarel sift, The bre! shift pra in TMISN2OCS4XX rooesirs i capable of ahifting the inet dats to-left (about ‘SI-iti and ight (about Ot 16-bit). The narnberof bit pstions te he sified and ocber renee can be specified inthe insraction atthe eld if shift cont ine tat register (ST Tse the fice of shift count or in the temporary register (T). ‘The bare shifer farce diagram ns shown in figare (3). ‘Figere 3: Fetons! Oiegram of Barrel Shifter in TEAZOCSATX __ Input data can be normalized within one ieycle in an ‘sccurnulator using a barrel shifter and exponent encoder. The ‘ourpit contwints zeros filled in their LSB positions and MSB ‘Positions containing either zero or sin extended as per the comtning, 17 = {7 1bit enahiplier, 40-6 for computing integer amd fractions and step (7 of 16-bit. Thee muitiptier’ser cmt functional sn shee i pare (9. oats pt son tc There ae many CPU Fi povided in They performing calculations 00 them. 1), ZOCSARCK py i" span Yoo Ba TY Rare ane Ey 1 DMR Lmernapt Mask Repisice aon ©} ORR lnterupe Fag Repster | Soi > Stara egies (STO, ST) Avemaloe (ALAN, AG. Bt: i, a) 4 Aepporsy puter (TREG) >emsinon regi (TR) ap > Aanilary segs (ARO AK 7) _ ah Stack pounter register (SP) 9% Circular buffer size register (BK) 1 Block repeat counter (BRC) g : fect ca cna te capable of locating he a ie fats CP repletes ad peg a: Block repeat wart address (RSA) 12 Block repeat end address (REA) 13. Processor mode samis (PMST) regicer p : igen (St Pasar Made Stats Nala Format 035. Expiain the Bus Architecture of DSP Processor. Ans: 7 Apes, Sab, ar) DSP processors employ harward architecture for bases and memory organzatios s shown i gure below, unr a wr mld dain era SPECTRUM AAN-ONE JOURNAL FOR UNIT-G (initoduction To DSP Processors and Archijeclure of TMS32005%) 6.28 figure separate mernory Depcks are antigned one for moving the adresses acl Ow other fr data wi eeu b ge Ale, ach aloied with separate buses. The veasa bein’ splitting the meenory ini peogram wud data mernoris i tha, {Bsc the peed oC eneuton of prgensie bot hy metus cn be csc tanec trnugh a rexpetve There are two data mcraory blocks present inthe architec. For instructions tha requite ne operand (inp at) fr their execution, i fetched fom one af the two data seenories, In CRE if ene iastrction requires two oper ab Yoh the operands can be Fetched rulumenaly from the to ia neti respectively Fur esr egy Oat 0a operation, Two operant are equ, one Yor multiplier ade eter for mullapicanl. So, slong wigan ‘emery two data meanary Nock ae equal toca oul eneoution of rach operations ins singe cyee Apart taaidiagtrtues i td data memones another kind of memory must be employed refered fo ms stich. ke oder icreas he ped satcoutines, grropt calls ara ERIM, ic teeny tl thal ca be accented ta Ppa Coie 36. What are the different buses of TMS320C5K processor and thal functions? Ans: sede TMSA20C3X processor family w-tabricated with CMOS IC technology. Ii a fixed pout 16-bit dugital g i a“ ‘sad opeeaten ata frequency of 4 Mile It poasesea the advanced Harvard archideture with separa proyeam The TMS32005X architects tc the following bases, PS” ~ Programs 8 F E t “Allie buses enable the processor to function ai high speed Le, diffvest buses enable different actions wo take place simaeously and ence crease do eperating yond of he prema . 1 PB-Pregram Bus Pian int i cnc ii pes ene cre. ‘L FAB-Program Addrem Bat Tenn foci of At he Seas pg gy epi ‘The insructods to be assigned ina particular addres are posed tothe respective wexaor location through his bas. esc, te insructons we tre accor atthe reory locating pda by the PAB, 3. DB-Dats Read Bus emia foron of DB bs inn CPU wn say spe Tati he aro sees of PU [ibe ALU, PLU, shifters ef are connected othe data memory space, Thus, the daa i transfered between the registers of CPU to memory space aod vice vena (2, the varios elements of CPU performs the operation (coc tthe commands i be ‘progtain) 00 the supplied data. The result of the operation is thea stored back on the data macmory apace using "data read bus”, 4. DAB-Datn Read Address Bus DAB bus carries the addresses to access the particular dala memory space, The operations to be pertanned. of the dita fe uot posse i te bene of hin ba 8 i of datas defined in the 57, Discuss in detail the Pipetina Opsration of Procassors. ee. % 3 © see 6ab4, ‘A sis-stage-deep instruction pipeline sitions a Wy CFU et THENCE es eh at een enon a: Th i a mitre esi of act Dpdg on he eo “pocesaing an fi iit scion can beat ar any iene. The six ire: age fg peracin © ane discaased below, i Lo Prete: * Vt pes eat the ete ga Ba a toch aig jag nin vo oe Pp (Ps ated wd dei arson Ree ae pple mtnyoenyabnay ‘STUDENTS Sik ero 4h | = DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA] Eo ax nin py toed th the Program fs (FI) eaten, Now, the contents of Istraston ) Memory sscess openstion type _, {6:30 The necesary contol tiga for dat SMe Acco ‘ap Daring programe aceon the read opernna!'s adkrest is placed on the Data Address fas (DAIB), However, the anther J, tury Rdg bun CAB i stared with a relevary metres on requirement of secs opersnd I this stage, the npefation of muxiiary - subayitegisters in indirect addrenting move sel the Stk Mointer #81) i de rons generation tnt and CPU tog pvr rend he avila opeat ae ef he dt ns (i. 8 ae CB. fis tage, he cot Matomayhaan cond proces beg On twe-Shove wit proven, The evaiahle data ween of he sre operation ie nore fe the aetna Lt, HAR ; ARETE Fae cep win sure iene afer ric nt wth oipof t nEB Dosing progam ihe te metas et exci vx difleveen tages of the pipeline are ax shown an figure hekow- [Peta ra [st ne na] to Te Figure iplne Opwrason of TMS120C 2X Procenora (238. Draw the block diagram of TMS320C50 digits! signal processor and explain the functionality of Central Arithmetic Logie Unit (CALU) and Parallel Logic Unit (PLU). ans ‘The Block digram of TMS320C30 digital signa processor i as shown in Figure. ai + Mesiary ; Shey =. a a| [sm DuaPrgam | [DitsDARAM PLES! Tote fee) | ese DARAN mGE ey | ae. x BIGI2s co x ‘BOYSI2= 16) (12% 18) Pas? ses me & S oe sat |] bt 7 serial port ro be counalle: Meco 4 = ‘CALL = ‘Satenbortrl * i == eYSr Hardware sack “Tpcrtary |: |* Ly) _ Orci jee] Altos Bris we bee dope wt (ALU) : FJ ih Th DAl sie lacy a ares al UNIT-6. (Introduction To DSP Processors and Architectite of THISA20CSXD ee ee SS The Genval Frocesing t 1. Central Axtthaetle Lagie Unlt (CALU) “The main paxpowe of wing thin unit by the CU is that is capable of o nnpating 7+ complement writhretic open “There are some Nock presenti hi nit. They ae, @) Porat mater 16» 16) (i) Accumuliter (ACC) 32 0) (a) ACC Baffler (ACER) 2-0 (rv) Prodect Register (PREG) () Shifen \()Aiifimetic Langie Unit (ALU) (32-Dil), \Peiel muipicr negara all 32.48 signedansigned multiplication operation in ene machin cycle, Lo th sige mination operation i perme by the multiply instruction, bunk MIPYU (unsigned mitipicaion) ‘Thetwo ipa operand othe mnliplior ae derived fom 16-bit temporary register © (TRCGO) tnd data ber The cure the emltipication result is stored in the product register, ‘The 32-bit ALU along with I6-bit zccutator executes arithimetic and logic operations within one suachine smut gives ont of the input othe ALL where as product regiscr, Accumulator Buffer (ACCB) or sali thi (gives the second input. Alva, the accumulator stores the output of ALU. ‘The input to the scaling shifter is derive from the 16-bit dat bus. hs output is given as input to the 32-be ALU S : sfc is sed to perform left shift operation om the 16-bit imput withthe shiftcoumt specified by the integer stowed in (CTREG!) or the inetruetion word. ‘2. Parallel Logie Unit (PLU) ‘The other logic unit of CPU is the parallel logic unit which performs logical operations whose resis do sccumalator contents. A multiplier bit preseat in a status/control register can be set, reset, tested or toggled by ‘The vert of logical opertion performed between twa operands ix tore inthe same memory location which wa Explain the memory Interface block diagram for the TMS320C5x processor, Ans: ‘The pupae of ix risers wed inthe TMS320C2X processor are, 1, Aaniliary Register ' ‘The TMS 520C5X has eight auilary episters (ARO-ART) cach af length 16-bit These repairs Coal sees Lags Usk (ALD) adept al eed yer Pel Lage Usk ‘egies Arituactic Unit (ARAU). These repairs ae wed in net abessng of data memory ot for temporary 2 Wider Register ; Auriliary register arithmetic unit during indirect eddressing uses & 16-bit inex register (INDX} to stoted in the aicciliary registers in steps. The INDIX added or subtracted fron the auxiliary reg seven. INDX reper can esp th aden lock dimensions eae ‘3. Aunilinry Register Compare Regliter (ARCR) ‘The ARCR is 16-bit regitter which is wied.to compare address boundary. I limits blocks of data ‘comparisons between the current AR. and ARCR. in conjunction with the instruction CMPR. 1 pucclin teTCtaetstt, 3 = = i a Distray ‘ aa a + PROCESSING LNT) AcaRmiap, The MARE ETEREEIC a as ye ; sober Yue ofa puna ae SSH pr ea a E ae open a HMMs OF 9 regu, ut degre i ena! 9 cond Various cone pe foam pares. Pathe, he ng vat ‘Tis sais eierupt types Supported by TMS32005X pocesir we INTIGINTI. This I icin ut owe ie maskabie eeacrrupe. NT4- INT) ‘0 the extemal mer ines The icra interpsae general bythe tex (TTT bythe sepus part RINT, XPNT, TRNT, TXNT, BRNT and BXNT) by host port ‘sueriags (HINT), through software (TTR, NM end TRAPL. The reset (RS}, NMI are the rwo external non-tuaskableiniccupa. In these 16 interrupts, highest priority goes to RS, Jesemapt and the lowest priority poes wo INTL. Tas interrupt vec locations, printed fincas of ach ata i ow UNIT-6_ (introduction To DSP Procassors and Arctiiecture of TMS320C5X) 6.29 ‘41: Compare THS3200 fixed and flating point processors, Anse The compara between fined and aang point TMS320¢: processors it phen below Ae Fined Patni Processor Fiaating Point Procesvor a 1] Wa fied pot processor, a Bamay pont aed Tinoaing pal proceso, wun wed ko pe er by ‘to hatte binary traction the product af two signed summbery, Le, Masta expouct, Wika 16sbit fixed point DSP process, 1 require gal scaling i onder Yo avo overflow errora Wie 2 in pit pci, 9 a is psn seo ic ell Petre weeny | |r peices ‘td small dynamic range. tncreasing Lage dynamic range. 2 performs haph-apeed operations, 5.| ltpestoans tine conning operons. | ™SiEs Fixed pout procewsors are relatively oconormical | Floating point processors we inore expensivg.apil * 2.aNs) ni conaumes lem power pose ee 3.) Application: Souall computes 7, | Applications: Video conferencing, actor pidkél® rise witching, cellular base jtton, radars ant did °" to the i — (Q42, What are the advantages of CISC? Ans: CISC (Complex Instruction Set Ceaputc ina philosophy for designing chips that are easy o program an which make asuser ficient use of mernory. Each iwirution in» CISC insruction set might perform a series of operations imide ta peacesace ‘wes ‘This rduces the mumber of itrutions raid ta anglementa pen program abl allow the programmer talaga a all bu tial Aenibe set 6 instructions, ‘ RS Adwantnges of CISC 41, The instruction set of CISC proceipor has the insrucjons such as MACD, FIRS, 2 The instruetion st of CISC processor ix very rich and it supports “fe”, “while” and "i sondition te then do”. 3. The assembly language program of « CISC processor is very hari and easy to fallow: 4. For low coat applications, CISC process ar mare prefered than RISC: 5, Micco-programming i sir to implement and mack les expensive than bard-wisng a contol wit. 6 Thecae of micro-coding new instructions allows CISC machines to be upwardly compatible (a:new computes would * ‘contin x superset of he instructions ofthe eatice oa 7. Aseach instruction bycarne mare capable, fewer structions cauld be ised to tmplemen a gives tuk. Tis made mace -elcient ws ofthe relatively slow min merry, : 5, Because miceo- program inatruction sels can be written to maich the constructs of high-level languages, the complet ced be é me Whatare the advantages of RISC? = ans: ‘The illowing ae the advantages of RISC proces, : ae . 41, In RISC processor, the conte unit wis around 20% of be chip ara. Hence, remaining area is wed for incorporating * other features, 2 The delayed branch and call instructions improve the speed of the RISC processor. ae ‘The execution tie equied fr al he iwructons of RISC peocewscr is wae. a SN : e 4, TheRISC procesox hive smaller wad simpler coer uot. Hence, i peed increases. plat ’ 3, ‘Sine a simplified instruction stallows fr « pipelined, mapercalar desig, RISC processor often echiove two to four ee ‘ it processor is simpler, it uses than a CISC procesboe. Bama vets chaser mcapene no ing pone un cn be plcedo tae chip ; a 7. Stee RISC poser cs deed uy, taunts fas ecg omen DIGITAL SIGNAL PROCESSING LJNTU-KAKINADAL Q4. Write short notes on the following, {if -Program controter Ge eit confer consis ola icy which i ete decode tye openetial ntrcsons, hae the pipe tine the CPU cperrtioer sun. is abe uned indecode the conditional epertions. The program contlierencompasiry in Cone! Rogers The PMS 52005 Be fou Goto and ttn eine: They ar, Gal butler como register Process mode sah reste ‘Sats regis STO ad ‘Stas reper STI. | The sac it 16-bit wide and level dap, which inaccened rough the instructions PUSH and POP. This swede sve ond restore the PC contents at the time of interrupts and subroutines, (Ov) Progrem Memery Addresees Generation i neta diem ft titre pe en tn ppt ade hat ionly wed to acces the program menary. (5) Testroctfon Registers . ‘The instruction registers are et a ea ae a (6) On-chip Memory : ? The TS nce ei «wl sem wong oF 224K w= ‘Jom wesmory sgsnents. They art, : (Program Memory Space (4 K-word) ‘ = ct ‘This encompasies the instruction tobe exeeted, ae a - (ii) Local Dats Memory Spree (64 K-werd) ; ; ae! ‘Thi stores the data ed'by the insttiom : vs (hi) npithOatpat Parti (64Kewied) . a insane nti get Gv), Global Dntn Memory Space (22 K-word) ‘ “This shares data with ther proceso with ia he system. mle the LUNIT-6 _(Ihivodiction To DSP Processors and Aighitnchare of TMS:A20085K) ‘O45. Write aibret note on same fags inthe status registers Ans: scone Im CS, the tno register it wae a store or relapd the data memory for sybroutites en an mer ceca STI antamatically ives the conte by using separate j-fevel deep shadow sql ack |, Status Replster (STH) ‘The bit astignment of STO ix shown in fge (1), tw s nar [ ov owns [wru] or | igor 1h AM (Auallinty Regiter Polnttr) _ {tuned for indirect addressing when ARP ix landed the frevious APE pets landed inn ARB (auxiliary ne st QV (Overtiow) Fig Bit In ALU, Reena: eto

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