Шаблон принципов построения ЦБ

Expedition Enterprise
Central Library
Specification Template
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Table of Contents
TABLE OF CONTENTS...........................................................................................................................................3
1 INTRODUCTION...........................................................................................................................................5
1.1 DOCUMENT PURPOSE AND SCOPE...........................................................................................................................................5
1.2 USAGE AND ASSUMPTIONS.................................................................................................................................................... 5
1.3 DEFINITIONS........................................................................................................................................................................5
1.3.1 Cell......................................................................................................................................................................... 5
1.3.2 Component.............................................................................................................................................................6
1.3.3 Part........................................................................................................................................................................ 6
1.3.4 PDB (Parts DataBase).............................................................................................................................................6
1.3.5 Partition................................................................................................................................................................. 6
1.3.6 Pad......................................................................................................................................................................... 6
1.3.7 Hole........................................................................................................................................................................6
1.3.8 Padstack.................................................................................................................................................................6
1.3.9 Pin Mapping...........................................................................................................................................................6
1.3.10 Property.............................................................................................................................................................6
1.3.11 Model................................................................................................................................................................6
1.3.12 Symbol...............................................................................................................................................................7
2 LIBRARY STRUCTURE...................................................................................................................................7
2.1 NAMING CONVENTION FOR PARTITION AND PARTITION SEARCH PATH SCHEMES..............................................................................7
2.1.1 Partition Names.....................................................................................................................................................7
2.1.2 Library Partition Search Path Schemes...................................................................................................................7
2.2 LIBRARY SYMBOL PARTITIONS.................................................................................................................................................8
2.2.1 Symbol Partition Search Path Schemes..................................................................................................................8
2.3 LIBRARY CELL PARTITIONS......................................................................................................................................................9
2.3.1 Cell Partition Search Path Schemes........................................................................................................................9
2.4 LIBRARY PART PARTITIONS.....................................................................................................................................................9
2.4.1 Part Partition Search Path Schemes.....................................................................................................................10
3 COMPONENT PROPERTIES.........................................................................................................................10
3.1 COMPONENT PROPERTIES – ALL CATEGORIES..........................................................................................................................10
3.1 COMPONENT PROPERTIES – RESISTOR...................................................................................................................................10
3.2 COMPONENT PROPERTIES – CAPACITOR.................................................................................................................................10
4 PARTS (PDB)..............................................................................................................................................11
4.1 PART IDENTIFIERS...............................................................................................................................................................11
4.2 PART (PDB) PROPERTIES.....................................................................................................................................................11
5 SYMBOLS..................................................................................................................................................12
5.1 REFERENCES FOR SYMBOL STANDARDS...................................................................................................................................12
5.2 SYMBOL NAMING CONVENTION............................................................................................................................................12
5.3 GENERIC SYMBOL ALTERNATE ROTATED VIEW.........................................................................................................................13
5.4 SYMBOL BODY GRAPHICS....................................................................................................................................................14
5.4.1 Unit Length.......................................................................................................................................................... 14
5.4.2 Grid Setting.......................................................................................................................................................... 15
5.4.3 Symbol Graphics Precision....................................................................................................................................15
5.4.4 Symbol Origin.......................................................................................................................................................15
5.4.5 Object to Object Clearance...................................................................................................................................16
5.4.6 Minimum Body Size..............................................................................................................................................16
5.5 SYMBOL BODY PROPERTIES..................................................................................................................................................17
5.6 SYMBOL PINS.................................................................................................................................................................... 17
5.6.1 Pin Graphics......................................................................................................................................................... 18
5.6.2 Using Explicit Power and Ground Pins (option 1).................................................................................................19
5.6.3 Explicit Bus/Vectored Pins (option 2)....................................................................................................................20
5.6.4 Using Implicit Power and Ground Pins (option 3).................................................................................................21
5.6.5 Pin Naming Standard...........................................................................................................................................22
5.6.6 Pin Name Property...............................................................................................................................................22
5.6.7 Pin Number Property............................................................................................................................................22
5.6.8 Pin Identification Text.......................................................................................................................................... 22
5.6.9 Pin Properties.......................................................................................................................................................23
5.6.10 Pin Property Placement...................................................................................................................................24
6 CELLS.........................................................................................................................................................26
6.1 CELL STANDARD REFERENCES................................................................................................................................................26
6.2 CELL NAMING................................................................................................................................................................... 26
6.2.1 Through Hole Cell Naming Convention.................................................................................................................26
6.2.2 Surface Mount Cell Naming Convention...............................................................................................................28
6.2.3 Generic and Manufacturer-Specific Cells..............................................................................................................29
6.3 CELL CONSTRUCTION RULES.................................................................................................................................................29
6.3.1 Cell Layer Graphic Definitions...............................................................................................................................29
6.3.2 Cell Units of Measurement...................................................................................................................................31
6.3.3 Pin Spacing...........................................................................................................................................................31
6.3.4 Package Orientation............................................................................................................................................ 31
6.3.5 Cell Origin.............................................................................................................................................................32
6.3.6 Assembly Data..................................................................................................................................................... 32
6.3.7 Silkscreen Data.....................................................................................................................................................33
6.3.8 Placement Outline................................................................................................................................................36
6.3.9 Placement Rules...................................................................................................................................................36
6.4 CELL PROPERTIES............................................................................................................................................................... 36
6.4.1 Standard Cell Properties.......................................................................................................................................37
6.4.2 Clearance Types...................................................................................................................................................37
6.4.3 Custom Cell Properties.........................................................................................................................................37
6.4.4 Cell Property Text.................................................................................................................................................37
6.4.5 Cell Pin Text..........................................................................................................................................................38
7 PADSTACKS...............................................................................................................................................38
7.1 PADSTACK NAMING............................................................................................................................................................38
7.2 PADS AND HOLE NAMING....................................................................................................................................................39
7.3 PADSTACK TECHNOLOGIES................................................................................................................................................... 39
7.4 PADSTACK GRAPHICS.......................................................................................................................................................... 40
7.4.1 Padstack Graphics – Through Hole.......................................................................................................................40
7.4.2 Padstack Graphics – SMD.....................................................................................................................................40
1 APPENDIX 1: CENTRAL LIBRARY FILE STRUCTURE.......................................................................................40
Library Specification Template - Page 4

1 Introduction
1.1 Document Purpose and Scope
The goal of this template document is to be used as the basis of a new library specification. Text
items colored blue are notes to the authors who will modify the template for their company’s use.
This explanatory text can be removed once the concepts are understood and choices are made.
The intent of this document is to provide rules and regulations for the creation and maintenance of
the Mentor Graphics Expedition Enterprise ECAD library. Following these rules and regulations
will ensure that all necessary data is associated with their respective objects at the time of creation,
enabling consistent and more efficient use of the design tools.
Companion Documents:
Library Development Process Guide – provides an overview of library organization,

management, part creation, part instantiation, and library/design synchronization.
http://supportnet.mentor.com/reference/documents/index.cfm?product=
Library Requirements to Support Analysis in the EE Flow - This document describes how to
modify a corporate library and how to create the library infrastructure to support simulation and
analysis.
http://communities.mentor.com/mgcx/docs/DOC-2939
1.2 Usage and Assumptions

It is assumed that the reader of this document is familiar with Mentor Graphics Expedition
Enterprise ECAD tools, the < Company Name> product development and manufacturing processes,
and the application of the ECAD tools in their product development and manufacturing processes.
1.3 Definitions
This section defines some of the main terms used in this document. For more definitions refer to the
PCB Glossary for the Expedition Enterprise Flow.
1.3.1 Cell
Two-dimensional graphic component representation used in Expedition PCB. Cells can be of the
following types:
 Package – Graphical and physical representation of a manufacturer’s component.
 Mechanical – Graphical representations of mechanical objects that may not have a pin
association. These objects can be, but not limited to: mounting sockets, nuts, bolts, card ejectors,
heat sinks, and washers
 Drawing – Graphics representations of design documentation and are composed of drawing
objects (e.g. sheet borders, cross sections) and textual notes
 Panel – Graphical elements added to a manufacturing panel to aid in the manufacturing process
Cells are edited using Cell Editor.

1.3.2 Component
In general use, component refers to an electrical part. In the context of this document, component
refers to a part number and related properties in a database. This term is used to distinguish the
database entry from the Part (PDB) defined in the Library Manager Part Editor.
1.3.3 Part
Object used in both DxDesigner and Expedition PCB. The part consists of one or more symbols, one
or more cells and the pin mapping relationship between said symbol and cells. Parts are edited using
Part Editor
1.3.4 PDB (Parts DataBase)
Parts in Library Manager are commonly referred to as being in the Parts DataBase or PDB for short.
Individual parts are sometimes referred to as “PDBs” or “PDB entries”. PDB entries are edited
using Part Editor.
1.3.5 Partition
Storage construct used in Library Manager to group library elements of a similar type.
1.3.6 Pad
A shape within a padstack, represent copper, soldermask, or solderpaste.
1.3.7 Hole
A drilled hole within a padstack.
1.3.8 Padstack
Graphical representation of the physical copper pads, soldermask, solderpaste and/or thermal relief
found in a cell and used on a printed circuit board. Padstacks are referenced by cells to define hole
and pad locations
1.3.9 Pin Mapping
The relationship between a part’s symbol(s) pin names and cell(s) pin numbers.
1.3.10 Property
A characteristic associated with a library element. Properties are comprised of a name and a value,
for example “Value=10K”.
1.3.11 Model
A functional representation of a device or system that is delivered in object code format, used to
perform design simulation/verification.

1.3.12 Symbol
Graphical representation of a manufacturer’s component used in DxDesigner. A symbol is

comprised of symbol body graphics, symbol body properties, pin graphics and pin properties.
Symbols are edited using Symbol Editor.
2 Library Structure
This section provides an overview of the Central Library structure, the naming conventions
and rules to be followed by the library user when creating library objects such as (but not
limited to): Partitions, Components, Symbols, Cells & Padstack.
The table below provides a high level view of the ECAD Library objects:
 Symbols, padstacks, cells and parts define electrical parts
 Templates, Reusable Blocks and Models partitions contribute to the design process and are
managed within the Library.
Expedition Enterprise DMS/Databook Central Library

(Central_Library.mdb) (Central_Library.lmc)
Reusable Misc. Files

SYMBOLS PADSTACKS CELLS PARTS Templates Models
Blocks Work
(SymbolLibs) (CellDBLibs) (CellDBLibs) (PartsDBLibs) (CellDBLibs) (IBISModels)
(LO & LP) Directories
2.1 Naming Convention for Partition and Partition Search Path Schemes
2.1.1 Partition Names
Partition names will be of <case type> case and will use only letters, numbers, and the underbar (‘_’)
character. Partition names are to be as consistent and descriptive as possible without being any
longer than necessary with a maximum of 32 characters.
Note: The names given in this template document serve as examples only.
Example: A symbol partition name for ICs of analog type could be “Analog_IC”.
2.1.2 Library Partition Search Path Schemes
For information on the purpose and usage of library search path schemes, refer to the Library
Development Process Guide.
Search path scheme names will be of <case type> case and will use only letters, numbers, and the
underbar (‘_’) character.

2.2 Library Symbol Partitions
Symbols are partitioned in the Central Library by logic function. This facilitates symbol data search
and maintenance.
The following symbol partitions are used in the library.
Partition Name Description

Analog_IC
Basic The “Basic” symbol partition manages the library “special
symbols” for interpage connectivity and “global signal
connectivity”
Border The “Borders” symbol partition manages the schematic drawing
borders approved for use for all projects
Connector
Diode
Discrete The “Discrete” symbol partition manages the generic symbol set
for resistors, capacitors, inductors etc. where the Part Number
and general meta data is added to the symbol instance via
DMS/Databook
FPGA
Memory
Microprocessor
Opamp
Optical
Transistor
In_Development Symbols under development by librarians or created by
engineers. Symbols in this partition are not approved for general
use. Once approved symbols will be moved to the appropriate
partition.
2.2.1 Symbol Partition Search Path Schemes
The following symbol search path schemes are defined in the library.
Scheme Name Purpose

2.3 Library Cell Partitions
Cells are partitioned in the Central Library by package type. The following cell partitions are used
in the library.

BGA Ball Grid Array components
PTH Pin Through Hole components
SMD Surface Mounted Devices
Connectors
In_Development Cells under development by librarians or created by engineers.
Cells in this partition are not approved for general use. Once
approved cells will be moved to the appropriate partition.
2.3.1 Cell Partition Search Path Schemes
The following cell search path schemes are defined in the library.
Scheme Name Purpose
2.4 Library Part Partitions

Parts are partitioned in the Central Library by logic function. This facilitates part data search and
maintenance.
The following part partitions are used in the library.

Analog_IC
Connector
Diode
Discrete The “Discrete” symbol partition manages the generic symbol set
for resistors, capacitors, inductors etc. where the Part Number
and general meta data is added to the symbol instance via
DMS/Databook
FPGA
Memory
Microprocessor
Opamp
Optical
Transistor
In_Development Parts under development by librarians or created by engineers.
Parts in this partition are not approved for general use. Once
approved parts will be moved to the appropriate partition.

2.4.1 Part Partition Search Path Schemes
The following part search path schemes are defined in the library.
Scheme Name Purpose
3 Component Properties
Component properties are stored in the DMS database/Dx DataBook database. All properties except
those specifically required by the software to be stored in the part (PDB) shall be stored at the
component level.
Component properties differ for each category of component as described in the following tables.
Provide a separate heading and table for each component category. Remember that component
database categories do not have to exactly match the part (PDB) partitions. For example, a DMS
database may have multiple levels of hierarchy in the component categories, such as Resistors/Fixed,
Resistors/Variable, and Resistors/Network. Part partitions allow only a single level of hierarchy,
such as Resistors.
Some properties are used strictly to help guide part selection and are not added to the symbol
(annotated) when parts are placed in a schematic. Other properties are annotated to the symbol to
enable certain software functions or to enhance schematic documentation. When annotated to the
symbol, the symbol property name does not have to match the component database property name.
This is illustrated in the examples below.
3.1 Component Properties – All Categories

This table includes properties added to all types of components.
Property Purpose Annotated to Symbol Property
3.1 Component Properties – Resistor

Resistance Value
Tolerance Tolerance
3.2 Component Properties – Capacitor

Capacitance Value

4 Parts (PDB)
This section describes conventions related to parts in the Central Library.
4.1 Part Identifiers

Three identifiers describe the part in the Central Library.
Part Number and Part Name are required. Part Label is optional.
Part Identifiers
Part Number Company standard part number.
Required to be assigned for every part in the library. Must be unique.
Example: CORPIDNUMBER0100-00’
Part Name General descriptive name of the part.
Required to be assigned for every part in the library, but it does not have to be
unique.
Exanple: 74AC04SC
Part Label Alternate descriptive name of the part
Not required to be assigned for every part in the Library and it does not have to
be unique,
Example: 74AC04_DIP14
Use upper case characters for identifiers.

Do not use following characters in the identifiers: % (percent) * (asterisk) ? (question mark) < >
(angle brackets) “ (quotation) : (colon) , (comma)
4.2 Part (PDB) properties

Height and Underside Space differ from most properties in that Expedition specifically looks for
these properties in the cell and in the part (PDB). Placing these properties in DxDatabook/DMS and
annotating them onto the symbols will have no effect on Expedition. Height and Underside Space
may be entered on the cell, in the part, or in both places. If defined in both places, the part properties
override the cell properties. Height and Underside Space are used by Expedition’s DRC and
mechanical interface (IDF) export functions.
The following properties shall be defined in parts.

Height Height from board to top of part N/A
Underside Space Distance from board to bottom of part N/A

5 Symbols
This section describes conventions related to symbols in the Central Library.
5.1 References for Symbol Standards

Refer directly to the list of reference material shown in table below, when the symbol standards in
this chapter do not address certain problem areas.
The purpose of this standard is to clarify the following reference material, not to replace it.
Identify which specifications are relevant to your company.
Publication or Standard Name

ANSI/IEEE Std 91-1984 Graphic Symbols for Logic Functions
ANSI/IEEE Std 91a-1991 Supplement to IEEE 91-1984
ANSI/IEEE Std 991-1986 Logic Circuit Diagrams
ANSI/IEEE Std 315a-1986 Graphic Symbols for Electrical and Electronic Diagrams
ANSI/IEEE STD 100-1977 Dictionary of Electrical and Electronic Terms
ANSI Y14.2M-1979 Standard Line Conventions and Lettering
ANSI Y14.2M-1979 Line Conventions and Lettering (reaffirmed 1987)
ANSI Y32.2-1975/CSA Graphic Symbols for Electrical and Electronic Diagrams
Z99-1975/IEEE Std 315-1975
ANSI Y14.15-1966 Electrical and Electronic Diagrams
IEC Publication 617-12, Second Graphic Symbols for Diagrams, Binary Logic Elements
Edition, 1991
IEC Publication 617-12, Amendment 1, Graphic Symbols for Diagrams, Binary Logic Elements
1992-06
IEC Publication 617-13, Second Graphic Symbols for Diagrams, Analogue Elements
Edition, 1993-01
IEC Publication 1175, 1992 Designations for Signals and Connections
IEEE STD 200-1975 (ANSI STD Reference Designations for Electrical and Electronics
Y32.16-1975) Parts and Equipment
ISO 3461-2 General Principles for the Creation of Graphical Symbols
MIL-STD-198E Selection and Use of Capacitors
5.2 Symbol Naming Convention

The symbols within a library part shall be named to indicate the function of the symbol.
Provide the character limits defined by the company. Refer to Library Manager Process Guide for
Library Object Name Limits and Legal Character set.

Type Description Convention Example
Shared Graphic symbols that can be XX Function 54FCT244; 74FCT244;
Symbols swapped because they have 54F244
basically the same function, but
are a different technology for
instance
Generic Many of the distinctive shaped Single rotation - res, cap, pcap, diode
Symbols components (like resistors, vertical
capacitors, and diodes) also share Rotated view res.1, res.2, cap.1, cap.2
the same graphics between the provides templated
same component types text location
Other Symbols that are not shared Function opamp, opamp2b,
Symbols amongst various components do opamp2b2c = Opamp
not have to adhere to the same with 2 bias and 2
naming conventions as shared compensation pins
symbols
5.3 Generic Symbol Alternate Rotated view

Generic symbols are often rotated on a schematic, to conform to drawing standards and clarity of
reading, on rotation of the symbol the properties are also rotated forcing the engineer to manually
rotate the text. To make this task more efficient this section provides three options to be considered
as standard process. Each option has benefits and disadvantages as discussed below.
Select one option below for the company standard.
Option Symbol view(s) Advantages Disadvantages

One Symbol Only one symbol to Potentially more
manage. time spent by
Provide the design engineer
most Only one symbol for to move, rotate
common engineers to choose to property values.
view. place.
Differing property
placement with Rotate,
Flip & Mirror.
Replace Part simplified.

Two Rotation clear to Two symbols to
symbols engineers during manage in
with selection. symbol library.
different
names Less time spent by Two symbols to
design engineer as text map in Part
Rotated correctly located. (PDB) mapping.
views
Differing property Replace Part
placement with Rotate, requires “select

Flip & Mirror. by symbol”
potential
multiple passes
required.
One symbol Correct property Engineer is
name with location is pre-defined required to
multiple for each rotation. select from list
views of res.1 .. res.8
Editing res.1 in the without easily
8 maximum symbol editor also knowing the
opens res.2 …res.8. rotation or text
location
Mapping a symbol with
res.1: 0 degree orientation
a part, one only one Find/Replace
symbol (e.g. ‘res’) is part only allows
selected and all single symbol
versions are version to be
automatically included. defined e.g.
(mirrored)
res.1 or res.2 so
DMS ‘Replace Part’ care must be
(mirrored)
Identify Part# option: taken on precise
“assign to” selection of
(mirrored)
functionality on a Part symbol/parts to
lists ‘res’ (not res.n) be replaced.
(mirrored)
and “assign to”
annotates new part
metadata to all
instances regardless of
symbol rotation view.
5.4 Symbol Body Graphics

5.4.1 Unit Length
The ANSI/IEEE 91-1984 standard uses “units” to define proportions for symbol graphics. All
standards in this document are based on unit length proportioning. This convention allows this
library specification to remain independent of the actual measured size in English, metric or scale
factor used on the schematic and ensure correct proportions
A unit is best defined by relating it to other common objects and measurements used on every
symbol. For example, a unit is the length between two pins divided by <eight>; in other words, the
minimum distance between two pins is <eight> units.

The actual length of a unit can be any value desired, but remember that all symbol measurements
must relate appropriately to the unit value. Define your company’s unit below.
The standard definition of a unit is 1 unit = 0.025 inches for English or 1 unit = 0.625 mm for metric
environment.
5.4.2 Grid Setting
When editing symbols the minimum pin grid must be set correctly and displayed. This provides an
easy way to know that measurements are accurate.
The minimum clearance between the graphic items must be two units (refer to ’Object to object
clearance’ section). The Symbol Editor grid setting must be two units.
A grid unit of <Insert Unit in English or metric> shall be set for all symbol creation.
5.4.3 Symbol Graphics Precision
The library Symbol Editor allows for "High Precision" setting and a "Backward Compatible" setting.
All symbols will use the “High Precision" setting.
Note: The “Backward Compatible” setting is used only if symbols are to be used with older versions
of DxDesigner (the values are rounded by 10 mils).
5.4.4 Symbol Origin
All symbols must be built with the symbol origin located on the left side of a symbol, on the lowest
pin.

5.4.5 Object to Object Clearance
The minimum white space (clearance) between symbol objects graphics and text is two units.
5.4.6 Minimum Body Size
Rectangular shaped symbol body minimum width is 16 units and minimum height is 16 units.

5.5 Symbol Body Properties
Symbol body properties are built into a symbol as placeholders in order to provide a graphical
component reference in the DxDesigner schematic and to communicate part identity and system-
level information about the part to another tool or downstream task.
The values for the symbol properties are not populated in the symbol body at the time of symbol
creation. The property values are annotated to the symbol property placeholders on instantiation
from DMS / Databook or PDB and the placeholder will determine its legibility and visibility.
Symbol properties are specified in the Central Library Property Definition Editor (Centlib.prp file)
together with the allowed length and syntax.
Make sure that the properties listed in the table below correspond to the “annotated to symbol
property” column in the table of component properties.
Note: Text height of four units with 1 unit=0.025 inch, approximately matches the font size of 15
typography points
The table below lists the standard properties that will be built into the symbol as place holders.
All symbol properties will have the following default characteristics unless otherwise specified in
the table below.
 Font Type: Fixed
 Font Size: 15
 Font Color: Automatic
 Visibility: Value Visible
Property name Location Visibility Color Font Size Font Type

Part Number X,Y Hidden
Part Name X,Y Hidden
Ref Designator X,Y
Value X,Y
Tolerance X,Y
<Other> X,Y
Property text shall have no less than two units of vertical white space above and below an adjacent
property, and eight units of horizontal white space between any two properties (see also the Object
to object clearance section).
5.6 Symbol Pins

This section defines standards related to symbol pin graphics, text, and properties.

Three options are given below for power/ground pins: explicit individual pins, explicit bus pins, and
implicit pins. Choose one option as the company standard.
5.6.1 Pin Graphics
The pin whisker that extends from a symbol body must follow certain length and positioning
standards. The pin whisker might also contain one or more special symbols to indicate items such as
signal flow, polarity, or a non-logic connection. The following discusses length matching for pin
whiskers, standard whisker lengths, whisker centering, input and output pins, flow arrows and
polarity indicators on pins, special pin types, and pins on the top and bottom of a symbol.
 Pin whiskers on discrete components are distinct graphics, and are not subject to any
restrictions or rules other than the pin spacing rule.
 Do not place pin whisker symbols on discrete analog symbols
 All pin whiskers must be equal in length on any one side of a symbol. The addition of such
objects on a whisker as bi-directional arrows or other special symbols do not affect the whisker
length
 Pin whiskers with no special objects must have a minimum length of eight units
 Pin whiskers with a bubble are always 16 units in length.
 Pin whiskers on one side of a symbol must have the same length, the whiskers might be
different lengths on different sides of a symbol.
 Pin whiskers should be centered to an array element
 The flow of data on a schematic is from left to right, where input lines shall always be on
the left and output lines shall always be on the right.

 If the direction of signal flow is not obvious, then mark the signal lines with arrowheads
pointing in the direction of signal flow
 Line groupings (address, control, data) must have their top-most pin as the least significant
bit (LSB) and propagate downward to the most significant bit (MSB)
 Active low inputs (i.e. set up the status ‘Inverted’ on the symbol pin equals ‘True’) must
contain a bubble
 All pin spacing distances (vertical and horizontal) must be a minimum of eight units or a
multiple of eight units.
5.6.2 Using Explicit Power and Ground Pins (option 1)
This is the method recommended by Mentor Graphics.
 All Pins of a symbol are to appear “explicitly” on the symbol body instance. No pins are to
be defined “implicitly” in the Part (PDB).
 On large parts this may requires the use of multiple symbols containing signal pins and
power, ground, and no-connect pins. All symbols of the device must be placed to ensure device
is powered.
 Place these pins on the side of the symbol, not on the top or bottom of a symbol.
Each individual pin is placed separately as shown below. There shall be no use of bus/vectored pins.

Benefits of explicitly defining pins:
 All connections associated to the component are explicitly displayed on the schematics.
 Specific decoupling can be applied to individual pins.
Disadvantages of explicitly defining pins:

 Schematic complexity is increased due to additional pins to connect to the wires.
 Extra symbols (e.g. power pack symbols) may have to be created in order to accommodate
all the explicit pins. All symbols of the device must be placed to ensure device is powered.
5.6.3 Explicit Bus/Vectored Pins (option 2)
This method is not recommended by Mentor Graphics.
 A bus pin is a single pin on a symbol that represents a group of power/ground pin bundled
together and used to minimize symbol size. Bus pins may be utilized on symbols for
power/ground pins.
 Each bus pin contains a range of pins, for example, GND[10:1] in the figure below
represents a bus pin, where one pin represents 10 bits (GND[10],…,GND[1]). Engineers would
connect a 10-bit bus to the symbol pin and all 10 bits are connected.
 Indicate a bus pin by making the pin graphics bold.
Benefits of using bus pins for power/ground:

 All connections associated to the component are explicitly displayed on the schematics
 There are no ambiguities on how components are powered
Disadvantages of using bus pins for power/ground:

 Schematic complexity is increased due to additional pins to connect to the wires (as
compared to using implicit pins).
 Pin numbers displayed as comma-separated lists on bus pins become long
 Bus pins must be connected to a bus rather than a regular wire.
 Ripping individual nets from the bus for specific decoupling is possible but not optimal.
 Global signal nets attached to bus pins require a special syntax (e.g. {GND}10)
 Bus pins do not display correctly in the nets section of Project Navigator
 Keyin netlists created from designs with bus pins list net names incorrectly

5.6.4 Using Implicit Power and Ground Pins (option 3)
This method is recommended by Mentor Graphics.
 Power, ground, and no-connection (NC) pins may be defined in the Part (PDB) file
(referred to as implicit pins) rather than being explicitly defined on the symbol.
 Default net assignments for each supply pin are included in the PDB.
 To inform the schematic designer exactly what implicit nets are assigned add a Supply
Rename property to any symbol that has implicit pins defined in the part (PDB). Annotate each
default implicit power / ground net name as defined in the part.
 Set the Supply Rename property to visible. The property also appears in the symbol
properties dialog.
In a schematic, the engineer may map the default power/ground nets to different nets by modifying
the Supply Rename property as shown below. For example, the default net “AVDD” is replaced by
net “5V” on the device below.

Benefits of using implicit pins:
 Symbols have fewer pins and are thus smaller
 Schematics have fewer wires, improving legibility
 Implicit connectivity visible in schematic
Disadvantages of using implicit pins:

 Decoupling is set for whole device
5.6.5 Pin Naming Standard
Use pin naming standards to ensure consistency and simplicity for the design engineer. Each symbol
in the library, regardless of the technology or manufacturer of the part, must follow the same set of
pin naming rules.
The pin naming standards followed by digital symbol pins in the library must be compliant with
ANSI, IEEE, IEC, and ISO design standards.
5.6.6 Pin Name Property
A pin name property is required for proper operation of the DxDesigner/Expedition flow.
 Each symbol pin must have a pin name property.

 The value of each pin name property must be assigned in the symbol.
 The value of each pin name property must be unique within the symbol.
 Pin name property values may be invisible. If pin name values are made invisible, visible
identification text must be placed to describe pin functions.
5.6.7 Pin Number Property
The pin number property specifies the physical cell pin number to which the logic pin is related. A
pin number property is required for proper operation of the DxDesigner/Expedition flow.
 Each pin must have a pin number property assigned with the value visible.
 Pin number values are not required to be assigned in the symbol because this information is
stored in the part (PDB) definition and annotated to the symbol when packaged.
 Librarians may assign pin number values in the symbol as an option. This is beneficial
when importing the pins into the part (PDB) editor as all the pin names/numbers will be
automatically mapped.
5.6.8 Pin Identification Text
If pin name properties are made invisible, annotation text must be placed to identify pin functions.
For example, rather than visibly displaying unique pin names “GND1” & “GND2”, identification
text “GND” may be placed between the two pins
Notice, the True Type fonts work best for the PDF generation: adjust font type and font size
appropriately to fulfill height requirement.

The following standards apply to pin identification text.
 Preferred text height for such pin identification (pin labels) is four units.
 Vertically center all pin identification characters to their associated pin whisker. When the
pin identification applies to a group of pin whiskers, vertically center it to the group of pin
whiskers.
 Separate the pin identification text from other objects using the minimum values shown in
the table below.
8 units Horizontal distance to any text not associated to the pin identification.
4 units Vertical or diagonal distance to any text not associated to the pin identification.
4 units Any vertical line other than the corresponding pin whisker body junction.
2 units Horizontal distance to the pin whisker body junction or to a corresponding
dynamic input, hysteresis, bit grouping, and so on.
2 units Vertical distance to any horizontal line.
The figure below illustrates the pin identification placement requirements.
5.6.9 Pin Properties
Pin Name, Pin Type and Pin Number are default properties assigned automatically once the pin is
instantiated in the Symbol Editor. Additional custom properties may be added. Every property must
first be specified in the Central Library Property Definition Editor (CentLib.prp file) before it can be
used.
The table below lists the standard properties that will be added to symbol pins.
All symbol properties will have the following default characteristics unless otherwise specified in
the table below.
 Font Type: Fixed
 FontSize: 15
 Font Color: Automatic
 Visibility: Value Visible

Property name Location Visibility Color Font Size Font Type
5.6.10 Pin Property Placement
The following standards apply to pin property locations.
 All pin properties must be placed relative to the graphical pin on the symbol.
 All pin properties must be placed at the same vertical and horizontal distance from the
graphical pin.
 The justification point for the pin name property is two units above and six units away from
the pin.
 The justification point for the Pin Number property is two units above and five units to the
right or left of the pin (depending if the pin is on the left or right side of the symbol body).
The figure below shows the location of the Pin Name (named “Pin Name”) and Pin Number (named
“99”) properties and their justification points (represented by a hollow circle).
Property Placement on Left-Sided Pins
Pins located to the left of the symbol have properties placed as follows:
 Pin name justification is bottom left
 The Pin Name justification point is two units above and six units to the left of the pin.
 Pin number justification is bottom right
 The pin number justification point is two units above and two units to the right of the
symbol body.
Placement on Right-Sided Pins
Pins located to the right of the symbol have properties placed as follows:
 Pin name is justified bottom right
 The pin name justification point is two units above and two units to the right symbol body
 Pin number is justified bottom left
 Pin number justification point is two units above and five units to the left of the pin.
Pin Name and Pin Number Placement on Analog and Passive Symbols
Many analog and passive symbols do not have the concept of a pin whisker, and pins might appear
on both the top and bottom of the symbol. The figures below show the special consideration given to
the placement of Pin Name and Pin Number on those symbols.

6 Cells
This section describes conventions related to cells in the Central Library.
6.1 Cell Standard references

Below is a list of existing industry standards for physical cell creation. Choose those that apply to
your company.
Cells must be created according to the specifications in the IPC, JEDEC, ANSI, and MIL-STD
standards.
Standards for Cell creation

JEDEC publication No. 95, May 1995 JEDEC Registered and Standard Outlines for Solid State
and Related Products
ANSI Y14.2M 1979 Line Conventions and Lettering
ANSI Y14.5 -1982 Dimensioning and Tolerancing
ANSI/IPC-SM-782 Surface Mount Landing Patterns
IPC-2221 Generic Standard on Printed Board Design
IPC-2222 Sectional Design Standard for Rigid Organic Printed
Boards
IPC-CM-770C Printed Board Component Mounting Guidelines
IPC-7351 Generic Requirements for Surface Mount Design and Land
Pattern Standard
IPC-1902/IEC 60097 Grid Systems for Printed Circuits
Drawing Requirements Manual, Sixth DOD-D-1000, DOD-STD-100, ANSI Y.14.1, ANSI
Ed, Global Engineering Documents Y.14.2M
DOD-STD-100C Engineering Drawing Practices
DOD-STD-00100D (AR) Engineering Drawing Practices
MIL-D-5480E Data, Engineering and Technical Reproduction
Requirements
MIL-STD-275E Printed Wiring for Electronic Equipment
6.2 Cell Naming

Use upper case alphanumeric characters and underscore symbols to name the cells.
Do not use * (asterisk) ? (question mark) ‘ (back quote) " (quotation mark) : (colon) in the name.
In the following cell naming conventions, the text between curly braces {L|W} represents optional
information, while the text between angle brackets (such as <P|C>) represents a required element of
the name.
6.2.1 Through Hole Cell Naming Convention
Naming conventions for different package types are defined below.
Through Hole Package Types

DIP DIPxx{L|W|X}_<P|C>{_SB|_BB}{_mfr} ‘xx’ = number of pins in the

package
{L|W|X} = Length, Width and
Example: DIP14_C, DIP14_C_SB_ANA Height in case it is not standard
value for DIP.
<P|C> = package material is
plastic or a C to indicate the
package material is ceramic
{_SB|_BB} = side-brazed DIP or
bottom-brazed DIP
{_mfr} = the manufacturer code,
for example, ‘_CYP’ for Cypress
SIP\ZIP SIPxx_<P|C>{_mfr} xx = number of pins in the
package
Or P = package material is plastic
C = package material is ceramic
ZIPxx_<P|C>{_mfr} {_mfr} = the manufacturer code,
e.g. ‘_CYP’ for Cypress
Example: SIP14_C, ZIP24_P
SIMM SIMMxx_<JEDEC_name> xx = number of pins in the
package
Or <JEDEC_name> JEDEC names
are documented in JEDEC
SIMMxx_<mfr>_<comp_height> publication No. 95 (November
Examples:SIMM30_MO064AA,SIMM30_MO064AE 1988) entitled “JEDEC Registered
and Standard Outlines for Solid
State Products”.
<_mfr> = manufacturer code
e.g. _IDT
(use only when the SIMM package
does not conform to the JEDEC
standard)
<comp_height> = component
height
(use only when the SIMM package
does not conform to the JEDEC
standard)
CFP CFPyy{_REC}{_W}{_mfr} _REC = rectangular packages.
The absence of _REC indicates
that the package is square
_W = body width in inches
_mfr = manufacturer code
e.g. _IDT
Standard Diodes and transistor analog packages use the common JEDEC package names TO18,
Analog DO35, or TO220AB. JEDEC names are documented in JEDEC publication No.
Packages 95(November 1988) entitled “JEDEC Registered and Standard Outlines for Solid State
Products
Passive discrete packages use the case style as the cell name; for example, CDR01, CK05,
RC07, RLR05, IM2, or IM4

6.2.2 Surface Mount Cell Naming Convention
SMD Cell Name Format Fields

General format: xxxxyy{optional_info}
xxx = JEDEC package type name.
yy = number of pins
{optional_info} is optional information depending on the package type
<required_info> is required information depending on the package type
_W = body width in inches or millimeters
_REC = rectangular CLCC, LCC, PLCC, or QFP packages. The absence of _REC indicates
that the package is square.
_J = J leads (SOIC packages only)
_mfr = manufacturer code, for example, _IDT. The absence of _mfr indicates that the
package conforms to the JEDEC standard.
Package Type Description Example Format
BGA Ball grid Array: BGAyy_<pitch>{_J}{_mfr}
with a square or rectangular array
of solder balls on one surface,
ball spacing typically 1.27 mm
LCC Quad-in-line: LCCyy{_REC}{_W}{_mfr}
Leadless Chip Carrier, contacts
are recessed vertically to "wick-
in" solder
MELF Two terminal package: Melf = MMB207
Metal Electrode Leadless Face Mini_Melf = MMU0204
Includes:- MICRO, Mini_MELF Micro_Melf = MMU0102
Mostly resistors and diodes;
barrel shaped components
PLCC Quad-in-line: PLCCyy{_REC}{_mfr}
Plastic Leaded Chip Carrier,
square, J-lead, pin spacing PLCC28_REC = 28 pin rectangular
1.27 mm PLCC package
QFP Quad-in-line: QFPyy{_REC}{_mfr}
Quad Flat Package, various sizes,
with pins on all four sides
SMD Two terminal package: JEDEC Package type e.g. 0201
Rectangular Surface Mount Packages (SMD
passive case forms) 0201 = (0.6 × 0.3 mm)
components (mostly resistors and capacitors) (0.024 × 0.012 in)
0603 =
1.6 × 0.8 mm (0.063 × 0.031 in).
SO Small Outline (4 to 28 pins)
SOD Two terminal package: SODxxx
Small Outline Diode
e.g. SOD523: 1.25 × 0.85 × 0.65 mm
SOIC Dual-in-line: SOICyy_<W>{_J}{_mfr}
Small Outline Integrated Circuit,
dual-in-line, 8 or more pins, gull- SOIC14_0.15 = 14 pin SOIC
wing lead form, pin spacing package with body width of 0.15

1.27 mm inches
SOT Three terminal packages: SOTxxx
Small Outline Transistor with
more than three terminals e.g. SOT223
= 6.7 mm × 3.7 mm × 1.8 mm body:
four terminals, one of which is a
large heat-transfer pad
SSOP Dual-in-line: SSOPyy{_W}{_mfr}
Shrink Small Outline Package,
pin spacing of 0.635 mm or in SSOP48_0.30 =48 pin SOP package
some cases 0.8 mm with a body width of 0.30 inches
TSOP Dual-in-line: TSOPyy{_W}{_mfr}
Thin Small Outline Package,
thinner than SOIC with smaller TSOP56_IDT =56 pin TSOP
pin spacing of 0.5 mm package from IDT
VSO Dual-in-line: VSOPyy{_W}{_mfr}
Very Small Outline Package, 0.4,
0.5 mm or 0.65 mm pin spacing
6.2.3 Generic and Manufacturer-Specific Cells
Other through-hole cells that do not follow the JEDEC standard package types or do not follow the
JEDEC specified dimensions use the format xxx_yyy where:
 xxx is an uppercase string denoting a code for the generic type of part or a specific
manufacturer.
 yyy is the manufacturer-specific designator or base part number of the device.
Examples of cells using generic part codes include CONN_RM351_152, FUSE_265, and
RELAY_640.
Examples of cells using codes for a specific manufacturer include MOT_22A01, NS_H08B, and
SANYO_SPA_2040
6.3 Cell Construction Rules

 Cell graphics must be drawn as viewed from the top side of the board. The part can be pushed or
placed on the bottom side during the PCB design process.
 The standard unit of measurement is one thousandth of an inch (mils) or one millimeter (mm))
 The standard grid shall be set to .050 inch (50 mils) or 1.27mm.
6.3.1 Cell Layer Graphic Definitions
Graphic Definition Properties

Placement Closed boundary shape Height= the maximum height above the
Outline around the entire part that mounting surface in “inch” unit value
compensates for placement Underside Space = Space between the
tolerances. bottom of the cell and the mounting
Assists to ensure proper surface.

spacing between components Layer = Layer on which to place the
when placing cells next to placement outline. I.e. Mount Side,
each other. Opposite Side, Top, or Bottom.
Line width = 0
Assembly Shape that represents the Layer = Layer on which to place the
Outline maximum space taken up by placement outline. i.e. Mount Side,
the part packaging. Opposite Side, Top, or Bottom
Assembly Placeholder value on the cell
Reference for the reference designator Line width = 0.05 inch
Designator property
Assembly Part Placeholder value on the cell
Number for the part number property.
Insertion The area(s) around the part Layer = layer on which to place the
Outline that Batch DRC uses to verify insertion outline. i.e. Top or Bottom
that the insertion machine
head does not collide with
other parts or assembly
outlines placed on the board.
Line width = 0
Silkscreen Appear on the silkscreen Layer = Layer on which to place the
Outline layer of the printed circuit placement outline. i.e. Mount Side,
board to show board Opposite Side, Top, or Bottom
assemblers where to mount
components. A silkscreen Not to be used on small parts where
outline must avoid solder outline is not legible
pads, traces, or other
conductive areas on the
silkscreen layer.
Silkscreen Part Placeholder value on the cell
Number for the Part Number property.
Silkscreen Placeholder value on the cell
Reference for the reference designator
Designator property.
Pin Text Text to Identify a pin on the Displayed Text defines the type of pin on
cell. which to display the text.
Helps engineers relate the Logical Pin (schematic), Physical Pin
physical board to the (layout), or User-Defined.
electrical schematic diagrams The settings create the following text
or other user-defined labels. strings when clicking a pin:
Attach pin text to a physical • Logical Pin: LP_<number of selected
pin and logical pin text is pin>
displayed. • Physical Pin: PP_<number of selected
pin>
• User-Defined: User Defined_<number
of selected pin>
Logical Pin and Physical Pin text is non-
editable. Only User-Defined pin text is
edible.
Property Text Placeholder text associated Layer = Displays all system and user-

with a specific property. defined layers available for implementing
Placing the part in a design standard text.
replaces the property text Property Name = Defines the list of
with the property value available properties. A librarian creates
specific to that part from the the properties that appear in the dropdown
parts database (PDB) list using the Library Manager Property
Definition Editor.
Route Obstruct Area to keep out a trace Layer = single layer or all layers
and/or a via.
Trace Obstruct = keeps out If the obstruct is an unclosed shape, traces
all conductive material, cannot cross the shape
including traces and copper
balancing data..
Via Obstruct = keeps out All conductive material is allowed within
vias. the area
Both = Trace and Via
keepout
6.3.2 Cell Units of Measurement
Cell data shall be entered in inches or millimeters according to the data sheet.
6.3.3 Pin Spacing
Cell pin spacing shall comply with the following standards.
The company standard could specify different pin spacing rules for standard through-hole cells, axial
and radial cells, and surface mount cells (see the examples below).
Refer to component datasheet. When pin spacing is not given use IPC-CM-770B.
For example, follow the requirements listed in IPC-1902/IEC 60097 - Grid Systems for Printed
Circuits where the preferred nominal grid in the layout is 0.5 mm or 0.05 mm.
Package Pin Spacing Increments Comment

Standard Data sheet
Through-Hole
Non-standard Data sheet
Through-Hole
Axial and xxx
Radial
Surface Mount Data sheet
6.3.4 Package Orientation
Cell package orientation shall be consistent with the standards below.
Package Type Orientation Pin 1 location

CFP, DIP, SOIC, Vertical. Pin 1 to the top left, with silkscreen notch at top
TSOP,SSOP
LCC, PLCC Pin 1 at top center
Radial Lead Horizontal. Pin 1 on left
Two-pin analog Horizontal. Pin 1 on left
and two-pin
passive devices
BGA Pin 1 at top right
Other Choice of orientation is optional. Refer to data sheet.
Pin 1
BGA Packages
6.3.5 Cell Origin
Cell origins shall be consistent with the standards below.
 The cell origin for all Surface Mount Devices shall be at the center of the device.
 The origin of all Plated Through Hole geometries shall be at the center of pin 1.
 For all others, the origin shall be at X,Y coordinate value of 0,0.
6.3.6 Assembly Data
Assembly data includes the placeholder for Ref Designator and Part Number property and Assembly
Outline (graphic combination of lines, circles, arcs and text).
Define standard line thickness and text setting for assembly items. The following requirements could
apply.
 Ref Designator and Part Number shall be placed inside the cell body if possible. If this is
not possible because the cell is too small, place outside the placement outline.

 All assembly text shall be set to a font type of XXX
 Reference Designator minimum text size is 0.05 inch (or 1.25 mm).
 Part Number minimum text size is 0.02 inch (or 0.50 mm).
 The standard line thickness used for the outlines and text is 0.01 inch (or 0.25 mm)
6.3.7 Silkscreen Data
By default, the silkscreen data includes the placeholder for the Ref Designator and Part Number and
silkscreen outline (graphic combination of lines, circles, arcs).
 All silkscreen text shall be set to a font type of XXX

 Ref Designator minimum text size is 0.05 inch (or 1.25 mm).
 Part Number minimum text size is 0.02 inch (or 0.50 mm).
 The standard line thickness used for the outlines and text is 0.01 inch (or 0.25 mm)
 Silkscreen graphics shall not overlap copper items.
Silkscreen Reference Designator Text Size
 On vertically oriented through hole geometries, the text size is 0.10 inch (or 2.5 mm for
metric-based cells).
 On all other through hole and surface mount geometries, the text size is 0.075 inch (or 2.0
mm).

Silkscreen Reference Designator Position
Reference Designator text should always be positioned outside of the component outline.
Text is positioned as follows.
Device Text orientation Text origin

Vertically-oriented CFP, DIP, Vertical with an orientation of Left of pin 1, immediately
SIP, SOIC, SSOP, and TSOP 270 degrees outside the placement outline
Radial, analog, and passive Horizontal and centered above Text orientation is 0 degrees
the placement outline.
LCC, PLCC, and ZIP devices Horizontal text is centered Text orientation is 0 degrees
below the placement outline.
Silkscreen Outline Guidelines
Device Outline orientation marking

CFP, DIP, SOIC, Rectangle as the body outline Rectangle to indicate the notch at
SSOP, TSOP the top of the package near pin 1.
The notch has a standard height of
0.060 inch (1.5 mm) and a
standard width of .040 inch (1
mm).

LCC, PLCC Corners to be marked outside of Corner with a beveled corner
the physical package area indicating orientation.
Others Approximate the outline of the

physical package.

Silkscreen Anode and Cathode Markings
A good design practice is to add anode and cathode markings on the silkscreen layer.
Cathode
6.3.8 Placement Outline
Placement outlines shall have a minimum line thickness of 0.01 and a maximum line thickness of 0.1
Use placement outline to specify the cell height and undersize space properties if needed. A cell may
have multiple placement outlines that each can carry a different height and underside space.
6.3.9 Placement Rules
Use this section to specify the allowed placement sides and rotations when the cell is placed in
layout. Rules are typically associated with particular types of cells, specified by Package Group or
Clearance Type.
6.4 Cell Properties

Properties may be assigned to cells and to cell pins.

6.4.1 Standard Cell Properties
Height and Underside Space differ from most properties in that Expedition specifically looks for
these properties in the cell and in the part (PDB). Placing these properties in DxDatabook/DMS and
annotating them onto the symbols will have no effect on Expedition. Height and Underside Space
may be entered on the cell, in the part, or in both places. If defined in both places, the part properties
override the cell properties. Height and Underside Space are used by Expedition’s DRC and
mechanical interface (IDF) file export functions.
The following properties are included on cells.
Property Required/Optional
Height
Underside Space
Package Group
Mount Type
6.4.2 Clearance Types
Clearance Type is used to further refine package type-to-package type clearance rules in CES.
When first beginning to use Clearance Types in Cell Editor, none will be available in the pick list, so
the name must be typed in. Once entered, each Clearance Type name is available in the pick list for
selection in any cell.
The following Clearance Types may be assigned to cells.
Clearance Type Purpose Required/Optional
6.4.3 Custom Cell Properties
Use custom cell properties to add optional properties to cells such as case to air thermal resistance.
The following custom properties shall be assigned to cells.
Custom Property Purpose Required/Optional
6.4.4 Cell Property Text
Property Text is a “text placeholder” in the cell which is associated with a specific Part (PDB)
property. When the cell is placed in Expedition the property text is automatically updated with the
property value specific to that part from the parts database.

The following property text shall be placed on cells.
Property Name Required/Optional Layer Display Condition

Rating Optional Assembly Mount Any Mount
6.4.5 Cell Pin Text
Pin Text is optionally used to create text to identify a pin on the cell. Such text helps engineers to
relate the physical board to the electrical schematic diagrams or other user-defined labels. Typically
only one type of pin text is used in a cell. For logical pin names, the pin text values are updated
based on the associated symbol when the cell is placed in Expedition. Update the table below per
company standards.
The following pin text shall be placed on cell pins.
Property Text Required/Optional Layer Display Condition

Logical pin name Optional Assembly Mount Any Mount
Physical pin number Not used
User defined Not used
7 Padstacks
This section describes conventions related to padstacks in the Central Library.
7.1 Padstack Naming

Padstack name shall follow the conventions specified below. The name should also help users
interpret the parameters (hole size, pad size and shape, etc.) of the padstack if possible. An example
padstack naming convention is shown below.
Padstack naming convention

<T>{S}{X1|_Y1}_{D}{X2|_Y2}_{ABC}
Definition Key Examples

T = Padstack type B = Bondpad TC1.5_D0.9_N = through-hole pin,
D = Die pin circle pad diameter 1.5 mm, hole
F = Fiducial size 1 mm, non-plated
M = Mounting hole
P – Shearing Hole TC60_D22 = through-hole pin,
S = SMD pinT = Through circle pad diameter 60 mils, hole
pin size 22 mils, plated
V= Via
S = Shape C = Circle SR1.5_1.0 = SMD pin, rectangle pad
D = Donut 1.5x1.0 mm)
E = Octgon
F = FingerR = rectangle SX100_20_CROSS = SMD pin,
O = Oblong custom pad, geometry size 100 x 20
S = square mils, CROSS is a custom shape
T = Thermal name
X = custom
X1 = pad size in the X axis
Y1 = pad size in the Y axis Empty if the pad is circle
shape or square
D = label to notify the drill size Applicable to pin-through
padstack
X2 = drill size in the X axis
Y2 = drill size in the Y axis Empty if the drill is circle

shape or square
ABC = additional identifier(s) Examples: hole plating,
to notify other parameters offset,
For consistency use upper case character set across the library.
Do not use following signs in the names: % (percent) * (asterisk) | (pipe), ? (question mark) < >
(angle brackets) “ (quotation).
7.2 Pads and Hole Naming

Options are to “generate name from properties” automatically in the Padstack Editor or use a custom
naming convention.
Use the Expedition “Generate name from properties” option for pad names and hole names.
7.3 Padstack Technologies

For information on the purpose and usage of Padstack Technologies refer to the Library
Development Process Guide and the Library Manager Process Guide.
The following padstack technologies shall be defined for all pads.

Technology Name Purpose
7.4 Padstack Graphics

Padstack graphics shall be placed on layers as described below.
Enter company standards below. Values given are just examples. Plane clearance and thermal pads
are used only for negative planes.
7.4.1 Padstack Graphics – Through Hole
Pad Layer Required/Optional

Mount side pad Required
Internal pad Optional
Opposite side pad Required
Plane clearance Do not use
Plane thermal Do not use
Mount side soldermask Required
Opposite side soldermask Required
Mount side solderpaste Required
Opposite side solderpaste Required
7.4.2 Padstack Graphics – SMD
Pad Layer Required/Optional

Top mount pad Required
Bottom mount pad Required
Plane clearance Do not use
Plane thermal Do not use
Top mount soldermask Required
Bottom mount soldermask Required
Top mount solderpaste Required
Bottom mount solderpaste Required
1 Appendix 1: Central Library File Structure

This section gives a brief overview of the Expedition Enterprise (EE) Central Library file structure.
Central Library data is stored in a single directory containing several subdirectories and files.
Central Library File Structure
Name File type Description

CellDBLibs Directory Contains all cell (.cel) files managed by the Cell Editor.
Layout Directory Contains the padstack file PadstackDB.psk and

JobPrefsDB.jpf file (which is read by the Cell Editor).
LogFiles Directory Contains log files associated with the central library
(.lmc) file processing.
MaterialDBLibs Directory Subdirectory created when the Material / Process Editor
opens from the Library Manager interface
Models Directory Stores Verilog (uncompiled and compiled Verilog A
models), VHDL and SPICE model data.
Models are separated into subdirectories with like type
models. While stored as files on disk, some files may
contain more than one model.
PartsDBLibs Directory Contains Part Database (.pdb) files
ReusableBlocksLO Directory Contains Logical-Only reusable blocks. When a LO RB
is first created it is in “unverified” state and is contained
in the RB “Work” directory. On user verification it is
moved to the RB “Cert” directory.
ReusableBlocksLP Directory Contains Logical-Physical reusable blocks. When a LP
RB is first created it is in “unverified” state and is
contained in the RB “Work” directory. On user
verification it is moved to the RB “Cert” directory.
SymbolLibs Directory Contains symbol files.
Templates Directory Contains subdirectories containing project files and
layout, drawing, and panel templates.
Drawing Sub-Directory Contains the drawing <template_name>.mdf file.
Layout Sub-Directory Contains Layout templates and supporting files.
Panel Sub-Directory Contains the <template_name>.pnl file control file.
Work Directory Working directory used for temporary storage.
CentLib.bak File Backup file of the CentLib.prp file.
CentLib.prp File Contains properties defined in Property Definition
Editor.
User-defined properties may be added to this file to be
recognized as company standard properties.
Note: this file has a fixed name and could be overwritten
during update of new software release.
<Central Library File DxDatabook user configuration file.
name>.dbc
< Central Library File Central library launch file.
name >.lmc
< Central Library File Cnfiguration file that stores information on the flow type
name >.cfg of the central library
nse_lm.ini File This file contains grid settings and default color settings
that are used by the Dx Symbol Editor (as specified in
the Preferences dialog box).
sysindex.cbf File Central library index file. This file can be deleted and
will be automatically re-generated the next time the
library is opened in Library Manager. This is known as
“re-indexing” the library and may be required on rare
occasions to resolve library issues.

Шаблон принципов построения ЦБ

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Шаблон принципов построения ЦБ

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Expedition Enterprise

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Library Specification Template - Page 4

Library Development Process Guide – provides an overview of library organization,

1.2 Usage and Assumptions

Cells are edited using Cell Editor.

Library Specification Template - Page 5

1.3.4 PDB (Parts DataBase)

A shape within a padstack, represent copper, soldermask, or solderpaste.

A drilled hole within a padstack.

1.3.9 Pin Mapping

Library Specification Template - Page 6

Graphical representation of a manufacturer’s component used in DxDesigner. A symbol is

Expedition Enterprise DMS/Databook Central Library

Reusable Misc. Files

2.1.2 Library Partition Search Path Schemes

Library Specification Template - Page 7

The following symbol partitions are used in the library.

Partition Name Description

2.2.1 Symbol Partition Search Path Schemes

Scheme Name Purpose

Library Specification Template - Page 8

Partition Name Description

2.3.1 Cell Partition Search Path Schemes

Scheme Name Purpose

2.4 Library Part Partitions

The following part partitions are used in the library.

Partition Name Description

Library Specification Template - Page 9

Scheme Name Purpose

3.1 Component Properties – All Categories

Property Purpose Annotated to Symbol Property

3.1 Component Properties – Resistor

3.2 Component Properties – Capacitor

Library Specification Template - Page 10

4.1 Part Identifiers

Use upper case characters for identifiers.

4.2 Part (PDB) properties

The following properties shall be defined in parts.

Property Purpose Annotated to Symbol Property

Library Specification Template - Page 11

5.1 References for Symbol Standards

Identify which specifications are relevant to your company.

Publication or Standard Name

5.2 Symbol Naming Convention

Library Specification Template - Page 12

5.3 Generic Symbol Alternate Rotated view

Select one option below for the company standard.

Option Symbol view(s) Advantages Disadvantages

Replace Part simplified.

Library Specification Template - Page 13

5.4 Symbol Body Graphics

Library Specification Template - Page 14

5.4.2 Grid Setting

5.4.3 Symbol Graphics Precision

5.4.4 Symbol Origin

Library Specification Template - Page 15

5.4.6 Minimum Body Size

Library Specification Template - Page 16

Property name Location Visibility Color Font Size Font Type

5.6 Symbol Pins

Library Specification Template - Page 17

5.6.1 Pin Graphics

Library Specification Template - Page 18