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BL0940 datasheet
Datasheet
Version update
Version Date Content Author
Catalog
Version update .................................................................................................................................................... 2
4 Order Information...................................................................................................................................... 30
5 Package ...................................................................................................................................................... 30
1 Product Description
BL0940 integrates 2 high-precision sigma-delta ADCs to measure current and voltage simultaneously. It
can measure electric parameters such as current and voltage RMS, active power, active energy, fast current
RMS (for over-current protection), and temperature detection, waveform output and so on. BL0940 output
data through the UART or SPI interface. It is available for the smart socket, smart appliances, single-phase
multi-function power meter, electric bicycle charging pile and information requirement of data acquisition in
electricity applications.
BL0940 has a patented anti-creep design, which can be combined with reasonable external hardware
design to ensure that the noise energy cannot be calculated in the energy pulse when there is no load
Features
VDD
Internal Power
LDO
BL0940 Clock On/Reset
SEL
IP1
PGA SDM UART SCLK
IN1
/SPI RX/SDI
TX/SDO
DSP ZX
CF
VP REG
VN
PGA SDM
1.2V
Reference Temperature
OTP
Voltage Sensor
GND VT VPP
Figure 1
VDD 1 14 VPP
VT 2 13 TX/SDO
IP1 3 12 RX/SDI
IN1 4 BL0940 11 SCLK
VP 5 10 SEL
VN 6 9 CF
GND 7 8 ZX
Figure 2
Pins description(TSSOP14)
1.6 Performance
AC power suppression
(output frequency ACPSRR IP/N=100mV 0.1 %
amplitude variation)
DC power suppression
(output frequency DCPSRR VP/N=100mV 0.1 %
amplitude variation)
Differential current input
Analog input level (current) 50 mV
(peak)
Differential voltage input
Analog input level (voltage) 100 mV
(peak)
Analog input impedance 370 kΩ
SEL pull-down resistor SEL(pull-down) 56.9 kΩ
Analog input bandwidth (-3dB) 3.5 kHz
Internal voltage reference Vref 1.218 V
Logic input high-level VDD=3.3V±5% 2.6 V
Logic input low-level VDD=3.3V±5% 0.8 V
VDD=3.3V±5%
Logic output high-level VDD-0.5 V
IOH=5mA
VDD=3.3V±5%
Logic output low-level 0.5 V
IOL=5mA
(T = 25 ℃)
Parameter Symbol Value Unit
Power Voltage VDD -0.3 ~ +4 V
Analog Input Voltage to GND IP1,VP -4 ~ +4 V
Digital Input Voltage to GND UART_SEL,RX/SDI -0.3 ~ VDD+0.3 V
Digital Output Voltage to GND CF,TX/SDO -0.3 ~ VDD+0.3 V
Operating Temperature Range Topr -40 ~ +105 ℃
Storage Temperature Range Tstr -55 ~ +150 ℃
2 Function Description
BL0940 is composed of analog signal processing module and digital signal processing module. The
analog module includes two-channel PGA, two-channel sigma-delta ADC, internal clock, power on/reset
monitor, temperature sensor and other related analog modules. The digital module is digital signal
processing module (DSP).
IP1
PGA ADC SINC3 HPF I_WAVE
IN1
Figure 3
BL0940 has two high precision ADCs, the current signal is differential signal. Current channel is IP1/IN1,
voltage channel is VP/VN.
The current and voltage waveform data are updated at a rate of 7.8k. Each sampled data is 20bit signed
value, which are saved in waveform registers (I_WAVE, V_WAVE). The waveform value can be read
continuously when the SPI rate is greater than 375Kbps.
External Internal
Address Symbol Bits Default Description
R/W R/W
0x01 I_WAVE R W 24 0x000000 Current waveform register
0x03 V_WAVE R W 24 0x000000 Voltage waveform register
Bit[19:0] are valid, Bit[19] is the sign bit. Bit[19]=0 means the waveform data is positive and Bit[19]=1
means the waveform data is negative, in complement form. Bit[23:20] are filled with 0.
WA_CREEP RMS_UPDATE_SEL
I_WAVE
LPF_ WATT
× + AVERAGE WATT
WATT ANTI-CREEP
V_WAVE WATT_t
WATTOS
Figure 4
External Internal
Address Symbol Bits Default Description
R/W R/W
0x08 WATT R W 24 0x000000 Active power register
4046∗𝐼(𝐴)∗𝑉(𝑉)∗Cos(φ)
WATT =
𝑉𝑟𝑒𝑓2
I(A) and V(V) are the voltage RMS of analog input PIN(IP&IN, VP&GND), φ is the phase angle
between I(A) and V(V) (AC signal), Vref is the on-chip reference voltage, the typical value is 1.218v.
This register indicates whether the active power is positive or negative. Bit[23] is the symbol Bit.
Bit[23]=0 means the current power is positive and Bit[23]=1 means the current power is negative, in
complement form.
External Internal
Address Symbol Bits Default Description
R/W R/W
0x15 WATTOS R/W R 8 0x00 Active power offset adjust register
WATT − WATT0
WATTOS =
8 × 3.05172
WATT is the active power after adjustment, and WATT0 is the active power before adjustment.
This register is 8bit unsigned data, default value is 0BH. The corresponding relationship between this
value and the active power register value is shown in the following formula. When the absolute value of the
input active power signal is less than this value, the output active power is set to 0. This can make the value
of the active power register is 0 and the energy does not accumulate in the case of no load, even if there is a
tiny noise signal.
External Internal
Address Symbol Bits Default Description
R/W R/W
0x17 WA_CREEP R/W R 8 0x0B Active power no-load threshold register
Set WA_CREEP based on the value of the power register WATT, their corresponding relationship as
below:
WATT
WA_CREEP =
3.0517578125∗8
Note: when the channel is in the anti-creep state, the RMS current register of this channel is
also set to 0.
CF_CLR
CF
Figure 5
External Internal
Address Symbol Bits Default Description
R/W R/W
0x0A CF_CNT R W 24 0x000000 Active energy pulse count
The count of active energy pulses corresponds to the consumption of electricity. The result is saved in
CF_CNT register. The count of pulses can be counted directly from the CF pin through I/O interruption. When
the period of CF is less than 180ms, the pulse is 50% duty cycle. When it is greater than or equal to 180ms,
the fixed pulse width of high-level is 90ms.
Note: CF_CNT is pulse algebraic sum accumulation. It means that pulse plus at positive
energy and minus at negative energy.
1638.4∗256
tCF=
𝑊𝐴𝑇𝑇
I_RMS_t
I_RMSOS RMS_UPDATE_SEL
V_RMS_t
V_RMSOS RMS_UPDATE_SEL
Figure 6
External Internal
Address Symbol Bits Default Description
R/W R/W
0x04 I_RMS R W 24 0x000000 Current RMS register, unsigned
0x06 V_RMS R W 24 0x000000 Voltage RMS register, unsigned
324004∗𝐼(𝐴)
The current RMS conversion formula: I_RMS =
𝑉𝑟𝑒𝑓
79931∗𝑉(𝑉)
The voltage RMS conversion formula: V_RMS =
𝑉𝑟𝑒𝑓
Note: I(A) is the input signal between IP1 and IN1 pins (mV), and V(V) is the input signal of VP
pins (mV).
External Internal
Address Symbol Bits Default Description
R/W R/W
0x13 I_RMSOS R/W R 8 0x00 Current RMS offset adjust register
RMS2 −RMS02
Calibration formula: RMSOS =
9.3132×215
RMS0 is the RMS current value before correcting and RMS is the RMS current value after correcting.
AC_FREQ_SEL
FAST_RMS
Figure 7
External Internal
Address Symbol Bits Default Description
R/W R/W
Shanghai Belling Corp., Ltd. 18 / 32
810, Yishan Road, Shanghai, China, 200233 Tel: +86-21-24261000
www.belling.com.cn
BL0940 Calibration-free Metering IC
External Internal
Address Symbol Bits Default Description
R/W R/W
0x00 I_FAST_RMS R W 24 0x000000 Fast current RMS
This register is updated according to one cycle or half-cycle. Bit[23:9] compare with the over-current
threshold FAST_RMS_CTRL [14:0]. If the value is greater than or equal to the threshold, CF pin outputs high-
level.
over-current alarm output indicator pin is CF, set MODE[12]=1 and TPS_CTRL[14]=1 before use it.
The response time ofover-current is up to 2 cycles or 2 half-cycles because the fast RMS values are
updated by cycle or half-cycle.
zx_pos_V
CORNER CORNER[15:0]
zx_pos_I
Figure 8
External Internal
Address Symbol Bits Default Description
R/W R/W
Current voltage waveform phase angle
0x0C CORNER R W 16 0x0000
register
V_WAVE
I_WAVE
Figure 9
𝑓𝑐
Phase Angle conversion formula: 2*pi*CORNER*
𝑓0
𝑓𝑐 is the frequency of the AC signal source, the default value is 50Hz. 𝑓0 is the sampling frequency, the
typical value is 1MHz.
Shanghai Belling Corp., Ltd. 20 / 32
810, Yishan Road, Shanghai, China, 200233 Tel: +86-21-24261000
www.belling.com.cn
BL0940 Calibration-free Metering IC
570us
ZX
Figure 10
Turn on the alarm function, the CF pin will output high-level if the TPS2 is greater than or equal to the
alarm threshold, when the temperature value is lower than the alarm value or the alarm function is turned
off, the CF pin output low-level.
External Internal
Address Symbol Bits Default Description
R/W R/W
0x0E TPS1 R W 10 0x0000 Internal temperature register, unsigned
0x0F TPS2 R W 10 0x0000 External temperature register, unsigned
Tx=(170/448)(TB/2-32)-45
The external temperature is measured by SAR ADC. The maximum input signal of the VT pin is VDD/2
(V), full scale is 1024.
External Internal
Address Symbol Bits Default Description
R/W R/W
External temperature sensor gain
0x1C TPS2_A R/W R 8 0x00
coefficient correction register
External temperature sensor offset
0x1D TPS2_B R/W R 8 0x00
coefficient correction register
3 3 Communication Interface
Register data are sent as 3 bytes (24bit). The data is fixed 3 bytes, if valid data bytes are less than 3
bytes, invalid bits are filled with 0.
3.1 SPI
The master device works in mode1: CPOL = 0, CPHA = 1. In idle state, SCLK is at low-level. Data is
received on the falling edge and data is sent on the rising edge.
Figure 11
In SPI communication mode, MCU send 8-bit identification byte (0x58) or (0xA8). (0x58) is the read
operation identification byte and (0xA8) is the write operation identification byte. Then send the address
byte of the register will be accessed (refer to BL0940 register list). The below figure shows the data transfer
sequence for read and write operations respectively. After one frame of data is transmitted, BL0940 re-
enters the communication mode. The number of SCLK pulses required for each reading and writing
operation is 48 bits.
There are two types of frame structures, which are explained as follows:
Write operation
frame
0xA8 ADDR[7:0] DATA_H[7:0] DATA_M[7:0] DATA_L[7:0] CHECKSUM[7:0]
The checksum byte is ((0xA8 + ADDR + DATA_H + DATA_M + DATA_L) & 0xFF) and then bitwise
inverted.
BL0940 return
data frame DATA_H[7:0] DATA_M[7:0] DATA_L[7:0] CHECKSUM[7:0]
The checksum byte is ((0x58 + ADDR + DATA_H + DATA_M+ DATA_L) & 0xFF) and then bitwise inverted.
Note: The data is fixed 3 bytes, high byte first, low byte last, if valid data bytes are less than
3 bytes, invalid bits are filled with 0.
The serial write timing is performed as follows. The frame identification byte {0xA8} indicates that the
data communication operation is data writing, and ADDR is the address of the target register. The MCU need
make the data ready before the lower edge of SCLK, and shift the data at the lower edge of this clock. All
remaining bits of the data are also shifted left on the lower edge of this SCLK (Figure 12).
SCLK
SDO
Figure 12
During the data read operation, BL0940 shifts the corresponding data to the SDO pin on the rising edge
of SCLK. SDO keeps unchanged during SCLK =1. MCU can sample SDO value before the next falling edge.
MCU must send a read command frame first before read operation.
SCLK
SDI ADDR[7:0]
Figure 13
When BL0940 is in communication mode, the frame identification byte {0x58} indicates that the data
communication operation is data reading. The next byte ADDR is the address of the target register. After
receiving the register address, BL0940 starts to shift out the data in the register on the rising edge of SCLK
(Figure 13). All remaining bits of the register data are shifted out on subsequent rising SCLK edges.
On the falling edge of SCLK, an external device can sample the output data of the SPI. Once the read
operation is completed, SPI re-enters the communication mode. SDO enters a high-impedance state on the
falling edge of the last SCLK signal.
SPI supports soft reset function, reset SPI interface individually by sending 6bytes of 0xFF.
3.2 UART
3.2.1 Description
BL0940 supports UART communication. The UART interface only requires two low speed optocouplers
to achieve isolated communication.
Baud rate: 4800bps Check bits: None Data bits: 8 Stop bits: 1.5
t1 t2 t3
t0
t1 t1 t1
(0xA8) is the frame identification byte for the write operation. ADDR is the internal target register in
BL0940 corresponding to the write operation.
t0
RX 0x58 ADDR[0:7] 帧头 ……
t0
TX
DATA_L[0:7] …… DATA_H[0:7] CHECKSUM[0:7]
t1 t2 t4 t3
(0x58) is the frame identification byte for the read operation. ADDR is the internal target register in
BL0940 corresponding to the read operation.
Timing Description
t2 Interval between the end of MCU sending register address and BL0940 72 uS
sending byte during read operation
checksum=(((0x58) + 0x55 + data1_l + data1_m + data1_h +…….)& 0xff)and then bitwise inverted.
If the frame identification byte is incorrect or the checksum byte is incorrect, the frame data will be
discarded.
UART module reset: The RX pin is pulled high after the low-level exceeds 6.65mS, and the UART module
will be reset.
4 Order Information
BL0940-TSSOP14L
5 Package
Moisture sensitivity level: MSL 3
Package: Taping