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Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital to Analog
Digital to Analog
Conversion
Conversion
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Pages 390
Pages 390
-
-
391
391
EE4512 Analog and Digital Communications Chapter 8
Traditional
Traditional
analog transmission
analog transmission
(AM, FM and PM) are less
(AM, FM and PM) are less
complex than digital data transmission have been the basis
complex than digital data transmission have been the basis
of broadcasting and communication for 100 years.
of broadcasting and communication for 100 years.
Analog television signal Analog television spectrum
S&M Figure 8
S&M Figure 8
-
-
1a
1a
EE4512 Analog and Digital Communications Chapter 8
Here n =
Here n =
4 and there are 2
4 and there are 2
4 4
= 16
= 16
levels for a full scale input
levels for a full scale input
of 2 V (
of 2 V (
1 V). The
1 V). The
step size
step size
= 2 V / 16 = 0.125 V and the
= 2 V / 16 = 0.125 V and the
quantized value
quantized value
is the
is the
midpoint
midpoint
of the
of the
voltage
voltage
range
range
.
.
S&M Table 8.1
S&M Table 8.1
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Sampling Baseband
Sampling Baseband
Analog Signals
Analog Signals
Pages 392
Pages 392
-
-
399
399
EE4512 Analog and Digital Communications Chapter 8
=
s
k =
x (t) x(t) (t k )
S
T
S&M Eq. 8.1
S&M Eq. 8.1
=
`
)
=
`
)
=
s
k =
s
k =
s
k =
X (f) X(f) (t k )
X (f) X(f) (f k )
X (f) X(f k )
S
S S
S S
T
f f
f f
F
S&M Eq. 8.2
S&M Eq. 8.2
EE4512 Analog and Digital Communications Chapter 8
k =
(t k )
S
T
=
s
k =
x (t) x(t) (t k )
S
T
=
s
k =
X (f) X(f k )
S S
f f
k =
(f k )
S
f
S&M Figure 8
S&M Figure 8
-
-
3
3
EE4512 Analog and Digital Communications Chapter 8
2 V, 20
2 V, 20
initial
initial
phase,
phase,
500 Hz
500 Hz
sinusoid
sinusoid
sampled at
sampled at
5 k samples/sec
5 k samples/sec
S&M Figure 8
S&M Figure 8
-
-
4a,b
4a,b
EE4512 Analog and Digital Communications Chapter 8
Aliased samples
Aliased samples
can be
can be
reconstructed
reconstructed
for a 4500 Hz
for a 4500 Hz
and a 5500 Hz
and a 5500 Hz
sinusoid that
sinusoid that
appears to be
appears to be
a 500 Hz
a 500 Hz
sinusoid
sinusoid
S&M
S&M
Figure 8
Figure 8
-
-
4a,c,d
4a,c,d
EE4512 Analog and Digital Communications Chapter 8
The
The
aliasing
aliasing
of
of
the signal can
the signal can
be predicted by
be predicted by
the magnitude
the magnitude
spectrum of the
spectrum of the
original 500 Hz
original 500 Hz
sampled signal.
sampled signal.
If the 4500 Hz
If the 4500 Hz
and 5500 Hz
and 5500 Hz
signals are then
signals are then
sampled at
sampled at
5 k samples/sec
5 k samples/sec
aliasing at occurs at | 4500
aliasing at occurs at | 4500
5000) Hz
5000) Hz
S&M Figure 8
S&M Figure 8
-
-
4a,b
4a,b
EE4512 Analog and Digital Communications Chapter 8
The sum of
The sum of
three sinusoids
three sinusoids
does not have
does not have
any aliased
any aliased
frequencies
frequencies
since the
since the
sampling
sampling
frequency
frequency
f
f
S S
is greater than
is greater than
twice the
twice the
highest
highest
frequency
frequency
f
f
max max
f
f
S S
> 2
> 2
f
f
max max
S&M Figure 8
S&M Figure 8
-
-
4a,c
4a,c
S&M Figure 8
S&M Figure 8
-
-
5
5
EE4512 Analog and Digital Communications Chapter 8
The frequency
The frequency
2
2
f
f
max max
is called
is called
the
the
Nyquist
Nyquist
frequency
frequency
.
.
Harry Nyquist,
Harry Nyquist,
who contributed
who contributed
to the understanding of thermal noise
to the understanding of thermal noise
while at Bell Labs, is also remembered
while at Bell Labs, is also remembered
in electrotechnology for his analysis of
in electrotechnology for his analysis of
sampled data signals.
sampled data signals.
S&M Figure 8
S&M Figure 8
-
-
4a
4a
Harry Nyquist
Harry Nyquist
1889
1889
-
-
1976
1976
EE4512 Analog and Digital Communications Chapter 8
For
For
practical signals
practical signals
f
f
S S
> 2
> 2
f
f
max max
using a
using a
guard band
guard band
for
for
LPFs
LPFs
S&M Figure 8
S&M Figure 8
-
-
7
7
f
f
S S
= 2
= 2
f
f
max max
f
f
S S
> 2
> 2
f
f
max max
guard band
guard band
EE4512 Analog and Digital Communications Chapter 8
With
With
out
out
-
-
of
of
-
-
band noise
band noise
and sample signals, aliases of the
and sample signals, aliases of the
noise now appear
noise now appear
in
in
-
-
band
band
and should be filtered before the
and should be filtered before the
sampling process.
sampling process.
S&M Figure 8
S&M Figure 8
-
-
8
8
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Sampling Baseband
Sampling Baseband
Analog Signals
Analog Signals
Pages 149
Pages 149
-
-
182
182
EE4512 Analog and Digital Communications Chapter 8
=
=
2 2 2 2
s-h S
k =
2 2
s-h
k =
PSD | X(f k ) | T sinc 2 f
PSD | X(f k ) | sinc 2 f
S S S
S S
f f T
f T
MS Eq. 4.4
MS Eq. 4.4
EE4512 Analog and Digital Communications Chapter 8
=
=
2 2
k =
2 2
s-h
k =
PSD | X(f k ) |
PSD | X(f k ) | sinc 2 f
S S
S S
f f
f T
MS Eq. 4.4
MS Eq. 4.4
=
n
x(n ) x(t) (t n )
S S
T T
MS Eq. 4.2
MS Eq. 4.2
EE4512 Analog and Digital Communications Chapter 8
2 2
k =
PSD | X(f k ) |
S S
f f
MS Eq. 4.2
MS Eq. 4.2
EE4512 Analog and Digital Communications Chapter 8
=
=
2 2 2 2
s-h
k =
2 2
s-h
k =
PSD | X(f k ) | sinc 2 f
PSD | X(f k ) | sinc 2 f
S S S S
S S
f f T T
f T
MS Eq. 4.4
MS Eq. 4.4
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Sampling Bandpass
Sampling Bandpass
Analog Signals
Analog Signals
Pages 399
Pages 399
-
-
400
400
EE4512 Analog and Digital Communications Chapter 8
f
f
1 1
) which is substantially less than
) which is substantially less than
2
2
f
f
2 2
S&M Figure 8
S&M Figure 8
-
-
9
9
f f
1 1
f f
2 2
f f
S S
= 20 ksamples/sec = 20 ksamples/sec
f f
S S
= 7 ksamples/sec = 7 ksamples/sec
LPF 10 kHz LPF 10 kHz
BPF 8 BPF 8- -10 kHz 10 kHz
8 10 kHz 8 10 kHz
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Sampling Bandpass
Sampling Bandpass
Analog Signals
Analog Signals
Pages 180
Pages 180
-
-
181
181
EE4512 Analog and Digital Communications Chapter 8
The
The
Simulink
Simulink
simulation uses the DSB AM modulation
simulation uses the DSB AM modulation
block and the sum of three sinusoids source.
block and the sum of three sinusoids source.
MS Figure 4
MS Figure 4
-
-
32
32
MS Figure 4
MS Figure 4
-
-
33
33
EE4512 Analog and Digital Communications Chapter 8
The
The
Simulink
Simulink
simulation initially uses a sampling rate of
simulation initially uses a sampling rate of
5 MHz and results in 4 194 304 = 2
5 MHz and results in 4 194 304 = 2
22 22
sampling points. The
sampling points. The
PSD shows the DSB
PSD shows the DSB
-
-
LC AM signal with the LSB and USB.
LC AM signal with the LSB and USB.
MS Figure 4
MS Figure 4
-
-
33
33
LSB USB
LSB USB
f
f
C C
Scaled PSD
Scaled PSD
f
f
max max
= 50 kHz
= 50 kHz
EE4512 Analog and Digital Communications Chapter 8
f
f
1 1
= 22.5
= 22.5
Quantizing Process:
Quantizing Process:
Uniform Quantization
Uniform Quantization
Pages 400
Pages 400
-
-
404
404
EE4512 Analog and Digital Communications Chapter 8
The
The
quantizing process
quantizing process
divides the
divides the
range
range
(
(
The
The
error
error
associated with the quantizing process is
associated with the quantizing process is
assumed to have a uniform probability density function.
assumed to have a uniform probability density function.
The maximum error for uniform quantization is:
The maximum error for uniform quantization is:
The quantizer range is
The quantizer range is
V
V
max max
and the uniform quantizer
and the uniform quantizer
voltage step size is:
voltage step size is:
The mean square quantizing E
The mean square quantizing E
q q
is the normalized
is the normalized
quantizing noise power:
quantizing noise power:
S&M Figure 8
S&M Figure 8
-
-
11
11
| |
= =
|
\ .
max max
n n
2 V V
q 0.5
2 2
= =
max max
n n-1
2 V V
2 2
( )
( )
/ 2
/ 2
= = = =
2 2 2
2
max max
q
2
2n
n
V V 1
E q dq
12
3 2
3 2
MS Eq. 4.7
MS Eq. 4.7
MS Eq. 4.6
MS Eq. 4.6
EE4512 Analog and Digital Communications Chapter 8
The
The
signal to quantizing noise power
signal to quantizing noise power
(SNR
(SNR
q q
) is:
) is:
P
P
S S
is the normalized power of the signal that is quantized.
is the normalized power of the signal that is quantized.
For the ADC here
For the ADC here
Quantizing Process:
Quantizing Process:
Nonuniform Quantization
Nonuniform Quantization
Pages 400
Pages 400
-
-
404
404
EE4512 Analog and Digital Communications Chapter 6
Uniform
Uniform
quantization
quantization
(top) results in
(top) results in
a large amount
a large amount
of error for
of error for
small sample
small sample
amplitude.
amplitude.
Non
Non
-
-
uniform
uniform
quantization
quantization
(bottom)
(bottom)
reduces the
reduces the
error for small
error for small
sample
sample
amplitudes.
amplitudes.
S&M Figure 8
S&M Figure 8
-
-
13
13
Uniform quantization Uniform quantization
Nonuniform quantization Nonuniform quantization
EE4512 Analog and Digital Communications Chapter 6
-
-
Law
Law
compressor
compressor
is used in
is used in
telephony
telephony
with MS Eq. 4.9
with MS Eq. 4.9
Companding
Companding
Pages 157
Pages 157
-
-
159
159
EE4512 Analog and Digital Communications Chapter 8
The
The
-
-
Law compander concept can be simulated in
Law compander concept can be simulated in
Simulink
Simulink
with the
with the
-
-
Law Compressor and
Law Compressor and
-
-
Law Expander
Law Expander
blocks. The A
blocks. The A
-
-
Law Compressor and A
Law Compressor and A
-
-
Law Expander
Law Expander
blocks are included for comparison.
blocks are included for comparison.
MS Figure 4.13
MS Figure 4.13
EE4512 Analog and Digital Communications Chapter 8
The
The
-
-
Law compressor voltage transfer function is
Law compressor voltage transfer function is
sigmoidal
sigmoidal
(S
(S
-
-
shaped).
shaped).
MS Figure 4.14
MS Figure 4.14
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Pages 171
Pages 171
-
-
175
175
EE4512 Analog and Digital Communications Chapter 8
The
The
pulse code modulator (PCM) transmitter utilizes a
pulse code modulator (PCM) transmitter utilizes a
Simulink
Simulink
-
-
Law compressor block, an 8
Law compressor block, an 8
-
-
bit ADC subsystem,
bit ADC subsystem,
an 8
an 8
-
-
bit DAC subsystem and a
bit DAC subsystem and a
-
-
Law expander block.
Law expander block.
MS Figure 4.21
MS Figure 4.21
EE4512 Analog and Digital Communications Chapter 8
The
The
Simulink
Simulink
8
8
-
-
bit ADC subsystem has a sample
bit ADC subsystem has a sample
-
-
and
and
-
-
hold
hold
block controlled by a
block controlled by a
sampling
sampling
pulse generator, an 8
pulse generator, an 8
-
-
bit
bit
encoder block, an integer
encoder block, an integer
-
-
to
to
-
-
bit converter block which
bit converter block which
provides an 8
provides an 8
-
-
bit
bit
vector
vector
to a demultiplexer block and a
to a demultiplexer block and a
multiport switch.
multiport switch.
An 8
An 8
-
-
level
level
staircase
staircase
subsystem
subsystem
sequences the multiport switch to select 1 of the 8 inputs for
sequences the multiport switch to select 1 of the 8 inputs for
bit serial output.
bit serial output.
MS Figure 4.22
MS Figure 4.22
EE4512 Analog and Digital Communications Chapter 8
The 8
The 8
-
-
level
level
staircase Simulink
staircase Simulink
subsystem sequences the
subsystem sequences the
multiport switch with a 3
multiport switch with a 3
-
-
bit counter and a 3
bit counter and a 3
-
-
bit DAC for the
bit DAC for the
output.
output.
MS Figure 4.22
MS Figure 4.22
3
3
-
-
bit DAC
bit DAC
3
3
-
-
bit counter
bit counter
EE4512 Analog and Digital Communications Chapter 8
The 8
The 8
-
-
bit DAC
bit DAC
Simulink
Simulink
subsystem for the PCM system
subsystem for the PCM system
uses a 8
uses a 8
-
-
bit
bit
shift register
shift register
and an 8
and an 8
-
-
bit DAC.
bit DAC.
MS Figure 4.24
MS Figure 4.24
8
8
-
-
bit DAC
bit DAC
8
8
-
-
bit shift
bit shift
register
register
EE4512 Analog and Digital Communications Chapter 8
The 8
The 8
-
-
bit DAC
bit DAC
Simulink
Simulink
subsystem for the PCM system
subsystem for the PCM system
uses a 8
uses a 8
-
-
bit
bit
shift register
shift register
and an 8
and an 8
-
-
bit DAC.
bit DAC.
MS Figure 4.24
MS Figure 4.24
8
8
-
-
bit DAC
bit DAC
8
8
-
-
bit shift
bit shift
register
register
EE4512 Analog and Digital Communications Chapter 8
8
8
-
-
bit DAC output after 8
bit DAC output after 8
-
-
bit ADC and
bit ADC and
-
-
Law Compressor
Law Compressor
MS Figure 4.25
MS Figure 4.25
MS Figure 4.21
MS Figure 4.21
EE4512 Analog and Digital Communications Chapter 8
-
-
Law Expander block
Law Expander block
output of the PCM system
output of the PCM system
MS Figure 4.25
MS Figure 4.25
MS Figure 4.21
MS Figure 4.21
EE4512 Analog and Digital Communications Chapter 8
LPF
LPF
output of the PCM system
output of the PCM system
MS Figure 4.25
MS Figure 4.25
MS Figure 4.21
MS Figure 4.21
EE4512 Analog and Digital Communications Chapter 8
Pages 407
Pages 407
-
-
411
411
EE4512 Analog and Digital Communications Chapter 6
1) + 0.2 s(n
1) + 0.2 s(n
2) +0.05 s(n
2) +0.05 s(n
3)
3)
where
where
S
S
(n
(n
)
)
is the
is the
predicted
predicted
value of the
value of the
n
n
th
th
sample
sample
and
and
s(n
s(n
-
-
i)
i)
is the
is the
n
n
-
-
i
i
th
th
sample.
sample.
The error
The error
signal is
signal is
s(n
s(n
)
)
S
S
(n
(n
)
)
S&M Figure 8
S&M Figure 8
-
-
15
15
EE4512 Analog and Digital Communications Chapter 6
Pages 175
Pages 175
-
-
180
180
EE4512 Analog and Digital Communications Chapter 6
A 4
A 4
-
-
bit first order
bit first order
differential pulse code modulator
differential pulse code modulator
(DPCM)
(DPCM)
can be simulated in
can be simulated in
Simulink.
Simulink.
MS Figure 4.26
MS Figure 4.26
EE4512 Analog and Digital Communications Chapter 6
2
2
s(n
s(n
) + s(n
) + s(n
-
-
1)
1)
MS Figure 4.27
MS Figure 4.27
error signal
error signal
input
input
ADC conversion command
ADC conversion command
EE4512 Analog and Digital Communications Chapter 6
The
The
Simulink
Simulink
4
4
-
-
bit ADC subsystem of the DPCM system is
bit ADC subsystem of the DPCM system is
similar to the 8
similar to the 8
-
-
bit ADC of the PCM system and illustrates
bit ADC of the PCM system and illustrates
design reuse.
design reuse.
MS Figure 4.28
MS Figure 4.28
EE4512 Analog and Digital Communications Chapter 6
The
The
Simulink
Simulink
4
4
-
-
bit DAC subsystem of the DPCM system is
bit DAC subsystem of the DPCM system is
also similar to the 8
also similar to the 8
-
-
bit DAC of the PCM system and
bit DAC of the PCM system and
again illustrates
again illustrates
design reuse.
design reuse.
MS Figure 4.29
MS Figure 4.29
4
4
-
-
bit DAC
bit DAC
4
4
-
-
bit shift
bit shift
register
register
EE4512 Analog and Digital Communications Chapter 6
s
s
e e
(n
(n
1)
1)
MS Figure 4.30
MS Figure 4.30
reconstructed
reconstructed
signal
signal
input
input
EE4512 Analog and Digital Communications Chapter 8
Analog in
Analog in
put signal of the DPCM system
put signal of the DPCM system
MS Figure 4.31
MS Figure 4.31
MS Figure 4.31
MS Figure 4.31
EE4512 Analog and Digital Communications Chapter 8
Output of the 4
Output of the 4
-
-
bit first order
bit first order
DPCM system
DPCM system
MS Figure 4.31
MS Figure 4.31
MS Figure 4.31
MS Figure 4.31
EE4512 Analog and Digital Communications Chapter 8
Output of the 4
Output of the 4
-
-
bit first order DPCM system
bit first order DPCM system
startup
startup
EE4512 Analog and Digital Communications Chapter 8
Output of the 8
Output of the 8
-
-
bit PCM system
bit PCM system
MS Figure 4.31
MS Figure 4.31
Output of the 4
Output of the 4
-
-
bit first order DPCM system
bit first order DPCM system
startup
startup
startup
startup
MS Figure 4.25
MS Figure 4.25
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Delta Modulation
Delta Modulation
Pages 411
Pages 411
-
-
415
415
EE4512 Analog and Digital Communications Chapter 6
Delta modulation
Delta modulation
is an extreme example of DPCM
is an extreme example of DPCM
using
using
1
1
-
-
bit data representing
bit data representing
:
:
S
S
(n
(n
) =
) =
S
S
(n
(n
1) +
1) +
b
b
i i
= 1 if
= 1 if
S
S
(n
(n
1)
1)
s(n
s(n
1)
1)
S
S
(n
(n
) =
) =
S
S
(n
(n
1)
1)
b
b
i i
= 0 if
= 0 if
S
S
(n
(n
1) >
1) >
s(n
s(n
1)
1)
S&M Eq. 8.10
S&M Eq. 8.10
S&M Figure 8
S&M Figure 8
-
-
18
18
DM transmitter DM transmitter
DM receiver DM receiver
EE4512 Analog and Digital Communications Chapter 6
on each
on each
transmitted bit.
transmitted bit.
b
b
i i
= 1
= 1
S
S
(n
(n
) =
) =
S
S
(n
(n
1) +
1) +
b
b
i i
= 0
= 0
S
S
(n
(n
) =
) =
S
S
(n
(n
1)
1)
S&M Figure 8
S&M Figure 8
-
-
19
19
4 1s 4 0s 4 1s 4 0s
EE4512 Analog and Digital Communications Chapter 8
Chapter 8
Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion
Delta Modulation
Delta Modulation
Pages 72
Pages 72
-
-
75
75
EE4512 Analog and Digital Communications Chapter 6
= 20 mV.
= 20 mV.
MS Figure 2.61
MS Figure 2.61
DM transmitter
DM transmitter
DM receiver
DM receiver
f = 2 Hz
f = 2 Hz
A = 1 V
A = 1 V
f
f
S S
= 2 kHz
= 2 kHz
T
T
S S
= 0.5 msec
= 0.5 msec
EE4512 Analog and Digital Communications Chapter 6
DM can be subject to
DM can be subject to
slope overload
slope overload
which occurs when:
which occurs when:
/
/
T
T
S S
< max | d
< max | d
m(t
m(t
) /
) /
dt
dt
| SVU Eq. 2.61 modified
| SVU Eq. 2.61 modified
Here the sinusoid has A = 1 but f = 10 Hz and:
Here the sinusoid has A = 1 but f = 10 Hz and:
/
/
T
T
S S
= 20 mV / 0.5 msec = 40 < max | d
= 20 mV / 0.5 msec = 40 < max | d
m(t
m(t
) /
) /
dt
dt
| = 80
| = 80
Granular noise
Granular noise
occurs
occurs
in
in
DM because if the input
DM because if the input
m(t
m(t
) is
) is
constant the received signal
constant the received signal
oscillates
oscillates
by
by
because there
because there
is no
is no
0
0
possible.
possible.
Clocking
Clocking
occurs at the DM symbol interval
occurs at the DM symbol interval
T
T
S S
= 0.5 msec.
= 0.5 msec.
MS Figure 2.64
MS Figure 2.64
= 20 mV
= 20 mV
=
=
20 mV
20 mV
T
T
S S
= 0.5 msec
= 0.5 msec
EE4512 Analog and Digital Communications Chapter 6
= 20 mV and
= 20 mV and
T
T
S S
= 0.5 msec (
= 0.5 msec (
r
r
S S
= 2 kb/sec)
= 2 kb/sec)
here.
here.
EE4512 Analog and Digital Communications Chapter 6
10t)
10t)
max | d
max | d
m(t
m(t
) /
) /
dt
dt
|
|
= 20
= 20
If step size
If step size
= 20 mV and
= 20 mV and
T
T
S S
= 0.5 msec then
= 0.5 msec then
/ T
/ T
S S
= 40 < max | d
= 40 < max | d
m(t
m(t
) /
) /
dt
dt
| = 20
| = 20
so
so
slope overload is
slope overload is
predicted to occur
predicted to occur
.
.
EE4512 Analog and Digital Communications Chapter 6
10t)
10t)
max | d
max | d
m(t
m(t
) /
) /
dt
dt
|
|
= 20
= 20
= 20 mV but
= 20 mV but
T
T
S S
= 0.25 m
= 0.25 m
sec
sec
then
then
/ T
/ T
S S
= 80 > max | d
= 80 > max | d
m(t
m(t
) /
) /
dt
dt
| and slope overload is
| and slope overload is
mitigated but
mitigated but
r
r
S S
= 4 kb/sec.
= 4 kb/sec.
EE4512 Analog and Digital Communications Chapter 6
In comparison, an 8
In comparison, an 8
-
-
bit PCM system sampling a 10 Hz
bit PCM system sampling a 10 Hz
sinusoid at a reasonable sampling rate of 500 Hz (50
sinusoid at a reasonable sampling rate of 500 Hz (50
sampling points/period) has
sampling points/period) has
r
r
b b
= 8(500) = 4 kb/sec or
= 8(500) = 4 kb/sec or
r
r
b b
= r
= r
S S
but PCM is more complicated than DM.
but PCM is more complicated than DM.
EE4512 Analog and Digital Communications Chapter 8
End of Chapter 8
End of Chapter 8
Analog
Analog
-
-
to
to
-
-
Digital and
Digital and
Digital
Digital
-
-
to
to
-
-
Analog
Analog
Conversion
Conversion