Module 3 - Design of

Combinational Logic Circuits

Dr. E.Papanasam
papanasam.e@vit.ac.in
Associate professor
School of Electronics
VIT Chennai
Design of Combinational Logic Circuits
 Half adder
 Full adder
 Half subtractor
 Full subtractor
 Decoder

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Decoder
 Discrete quantities of information are represented in
digital systems with binary codes
 A binary code of n bits is capable of representing up to
2n distinct elements of the coded information
 Combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output
lines

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3 to 8 Line Decoder

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 Decoder with Enable input
 Enable lines are a convenient feature for connecting two or more IC
packages for the purpose of expanding the digital function into a similar
function with more inputs and outputs

A 2-to-4 Line decoder with enable input 9/9/2022 FS2022-23 6

Practice Problem
 Draw the logic diagram of a 2-to-4-line decoder with
only NOR gates. Include an enable input.

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A 4 x 16 decoder constructed With two 3 x 8
decoders

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Practice Problem
 Construct a 5 X 32 decoder with four 3 X 8 decoders
with enable and one 2 x 4 decoder

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Boolean Function Implementation
 A combinational circuit is defined by the
following three Boolean functions. Design
the circuit with a decoder and external
gates
 FI = x'y'z' + XZ
 F2 = xy'z' + x'y
 F3 = x'y'z + xy

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Implementation of a full-adder with decoder
 S(x, y, z) = ∑ (I, 2, 4, 7)
 C(x, y, z) = ∑ (3, 5, 6, 7)

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Practice Problem
 Design a half subtractor using decoder
and suitable gate

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Behavioral modeling
 module decoder24_behaviour(en,a,b,y);
 input en, a, b;
 output reg [3:0] D;
 always @(en, a, b)
 begin
◦ if(en==0)
 begin
 if(a==1'b0 & b==1'b0) y=4'b0111;
 else if(a==1'b0 & b==1'b1) y=4'b1011;
 else if(a==1'b1 & b==1'b0) y=4'b1101;
 else if(a==1 & b==1) y=4'b1110;
 else y=4'bxxxx;
 end
◦ else y=4'b1111;
 end
 endmodule 9/9/2022 FS2022-23 13
Data flow
 module decoder24_assign(en,a,b,y);
 input en,a,b;
 output [3:0] D;
 wire enb,na,nb;
 assign enb = ~en;
 assign na = ~a;
 assign nb = ~b;
 assign y[0] = ~(enb&na&nb);
 assign y[1] = ~(enb&na&b);
 assign y[2] = ~(enb&a&nb);
 assign y[3] = ~(enb&a&b);
 endmodule
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Gate Level
 module decoder24_gate(en,a,b,y);
 input en,a,b;
 output [3:0] D;
 wire enb,na,nb;
 not n0(enb,en);
 not n1(na,a);
 not n2(nb,b);
 nand n3(y[0],enb,na,nb);
 nand n4(y[1],enb,na,b);
 nand n5(y[2],enb,a,nb);
 nand n6(y[3],enb,a,b);
 endmodule
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Test Bench
 module tb;
 reg a,b,en;
 wire [3:0] D;
 decoder24_behaviour dut(en,a,b,y);
 initial
 begin
 $monitor("en=%b a=%b b=%b y=%b",en,a,b,y);
 en=1;a=1'bx;b=1'bx;
 #5 en=0;a=0;b=0;
 #5 en=0;a=0;b=1;
 #5 en=0;a=1;b=0;
 #5 en=0;a=1;b=1;#5
 $finish;
 end
 endmodule 9/9/2022 FS2022-23 16
Demultiplexer
 Circuit that receives information on a single line and transmits this
information on one of 2n possible output lines
 The selection of a specific output line is controlled by the bit values
of n selection lines.

 The decoder can function as a demultiplexer if the E line is taken as

a data input line and lines A and B are taken as the selection lines
 The single input variable E has a path to all four outputs, but the
input information is directed to only one of the output lines, as
specified by the binary value of the two selection lines, A and B.
 Decoder with an enable input is referred to as a demultiplexer.
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Demultiplexer

Courtesy: Electronicshub
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Decoder as Demultiplexer

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Encoder
 Digital circuit that performs the inverse operation of a decoder
 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines generate the binary code corresponding to the
input value
 Example
 Octal to-binary encoder
◦ It has eight inputs, one for each of the octal digits, and three
outputs that generate the corresponding binary number
◦ It is assumed that only one input has a value of 1 at any given
time; otherwise the circuit has no meaning
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Octal-to-Binary Encoder

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Octal-to-binary encoder

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Priority Encoder

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4-input priority encoder

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Practice Problem
 Three Types of modeling of Encoder
 4 to 2 Priority encoder with D3 having
highest priority

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 MULTIPLEXERS
 Multiplexing means transmitting a large number of information
units over a smaller number of channels or lines
 A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single
output line
 The selection of a particular input line is controlled by a set of
selection lines
 A multiplexer is also called a data selector
◦ It selects one of many inputs and steers the binary information
to the output line
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4-to-1line multiplexer

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Multiplexer with Enable Input
 Quadruple 2-to-1 line multiplexer

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Boolean-Function Implementation
 F(A, B, C) =∑(1, 2, 4, 5)

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Full adder Implementation
 Implement a full-adder with two 4 x I multiplexers
 Implement a 8 x 1multiplexer using 4 x 1 and 2 x 1 Mux

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Practice problem
 F(A, B, C) =∑(1, 3, 5, 6)
 F(A, B, C, D) = ∑(0, 1,3, 4, 8, 9, 15)
 Construct a 16 x 1 multiplexer with two 8 x 1 and one
2 X 1 multiplexers. Use block diagrams for the three
multiplexers
 Implement the following Boolean function with an 8 x 1
multiplexer. F(A, B, C, D) = ∑(0, 3, 5, 6, 8,9, 14, 15)

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Parity Generator and Checker
 Parity bit is used for the purpose of detecting errors during
transmission of binary information
 A parity bit is an extra bit included with a binary message to make
the number of l's either odd or even
 The message, including the parity bit, is transmitted and then
checked at the receiving end for errors
 An error is detected if the checked parity does not correspond
with the one transmitted
 The circuit that generates the parity bit in the transmitter is called
a parity generator
 The circuit that checks the parity in the receiver is called a parity
checker
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Even-Parity-Generator

 P = x XOR y XOR z
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Even-Parity-Checker

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