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CPBO423 - Lesson 2 - Computer Function and Interconnection
CPBO423 - Lesson 2 - Computer Function and Interconnection
William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Computer Components
n Hardwired program
n The result of the process of connecting the various components in
the desired configuration
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Data
Sequence of
arithmetic
and logic
functions
Results
Hardware
and Software Instruction Instruction
Approaches
codes interpreter
Control
signals
General-purpose
Data arithmetic Results
and logic
functions
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
+ • Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
MAR
I/O address I/O buffer
register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O exchange of data
+ device between an I/O
module and the
CPU
MBR
I/O AR
Data
Execution
unit Data
I/O BR
Data
Data
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Processor- Processor-
memory I/O
Data
Control processin
g
• An instruction may • The processor may
specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data
0 1 15
S Magnitude
Multiple Multiple
operands results
Table 3.1
Classes of Interrupts
1 4 1 4 1 4
Interrupt Interrupt
2b Handler Handler
END END
3a
3 3
3b
(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait
i
Interrupt
occurs here i+1
Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled
HALT
1 1
4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
1 1
4 4
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
Multiple Multiple
operands results
No
Instruction complete, Return for string interrupt
fetch next instruction or vector data
Interrupt
handler Y
Interrupt
User program handler X
Interrupt
handler Y
15
0 t=
t =1
t = 25
t= t = 25 Disk
40 interrupt service routine
t=
35
Data N–1
External
Address M Ports Data
Internal
Data Interrupt
Signals
External
Data
Instructions Address
Control
Data CPU Signals
Interrupt Data
Signals
An I/O
module is
allowed to
exchange
Processor Processor data
reads an Processor reads data Processor directly
instruction writes a from an I/O sends data with
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
n
same time period their signals will
overlap and become garbled
n
e
Typically consists of multiple
Computer systems contain a t
B c
communication lines
number of different buses
• Each line is capable of that provide pathways
transmitting signals representing
binary 1 and binary 0 between components at e
u t
various levels of the
computer system hierarchy
r
s i
System bus c
• A bus that connects major The most common computer o
o
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses
n
n
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Data Bus
n Data lines that provide a path for moving data among system
modules
Control lines
Data lines
I/O device
I/O Hub
DRAM
DRAM
Core Core
A B
DRAM
DRAM
Core Core
C D
I/O device
I/O device
I/O Hub
Routing Routing
Flits
Link Link
Rcv Clk
Transmission Lanes Reception Lanes
Fwd Clk
Rcv Clk
Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge
PCIe
PCIe PCIe
Switch
PCIe PCIe
Physical Physical
128b/ PCIe
B6 B2
130b lane 2
128b/ PCIe
B7 B3
130b lane 3
Differential
Scrambler Receiver
8b 1b Clock recovery
circuit
Data recovery
128b/130b Encoding circuit
130b 1b
1b 130b
Transmitter Differential
128b/130b Decoding
Driver
128b
D+ D–
Descrambler
(a) Transmitter
8b
(b) Receiver
n Configuration n Message
n This address space enables n This address space is for
the TL to read/write control signals related to
configuration registers interrupts, error handling,
associated with I/O devices and power management
Appended by PL
2 Sequence number
DLLP
Created
by DLL
4
2 CRC
12 or 16 Header 1 End
0 or 4 ECRC
4 LCRC
1 STP framing