— —_~ ee CONTENTS " Part-1 : Introdu Pimctional «2... -escacca-c 1-2B tp Lan | Units of Digital System : and their Interconnection Part-2 : Bus, Bus Architecture, 20.0000... IASB to 1-68 : Types of Buses Part-3 : Bus Arbitration .... . + one 146B to 1-68 { Part-4 : Register, Bus and 0c 1-8B to 1-11B i Memory Transfer | Part-5 : Processor Organization, ......... seve 1-1 LB to 1-128 General Register Organization | Part-6 : Stack Organization... csttttteeeeeeee 1-1SB to 1-17B _ Part-7 : Addressing Modes .. 1-17B ta 1-299R Secongue Organon ‘reangementof CPE memory. npuout pet to work 88 compuin surge it oa [fants] 7 Top ate Outpe re Sen ts sere, (a) se Cae ise ee ‘ea 7 Soe 7 a tntiates aw of Malate ierscone tod ata Maineraal ie aia tt = = taercaedby tbe 1a snr ea cate roceiag oanccrtn ete |& Input unit: This unit is used forentering data and programs into the rig. 121. Poocina! a of lace ‘computer system by the user for processing. hone (AL): 1 AritimetieLoge Unit AL: oat b Storage unit : The storage unit is used for storing data and instructions ig rexpunsible for earring out fllowing oper inet on 2 Alvar oe aay ae © Gntput unit The output uni isused for storing the reel aa oats ‘ltipngenddvingene et ian produced bythe eompster after posing 22 Lael opert yO ge anand Processing unit ‘The task of performing operations like arithmet a See _ ‘Stel ae where ‘een Poning Unt CU) ae dt ed srs om te Ba rats es ac deine PME IT sortsfcaeultion based on the inatrctons -Biven and the typeof data provided. Its then sent back to the storage unit. arava coat it (CO gts earn ‘GeTRT] cptsn the enetionl units of dial aysem and this ca any ed fr prating he cnc interconnections. al crue cto ah 8 ieee aah ld yn en Loren ae ‘Temalnfurettons onto gal omputer are shawn nF 1.2. eT ed ort mr 1 Central Prcesing Tate CPU) fered eo pecan ‘4 The CPU isthe brain of a computor system, . anagesand contri eae ', Thisunittales the data om the input devices and process it sit An inp unit petorm ouuide wor sesring ate stein eld open ee 3 ee acento ee © Bieityrcming tie tiated theca dees the atrcione on a ‘eo iron me nea Ne cements sat a : é (CPU kos wo njr par ealod ALY and Contra Unit. iesb. The CPU sends signals on the control bus to enable the outputs of addressed memory device or port device Que 14. | Describe the architecture of bus. Answer ‘The computer bus consists of two parts, the address bus and adata bus ‘The data bus transfers actual data, whereas the address bus transfers address or memory location of where the data should go ‘The bus provides physical inks and the means of controlling the communication exchange of signals over the bus. Fig. 14 1 depicts the organization of a single shared bus. i System bus Fig. 1.4.1. Architecture of a single shared bus, The principle use of the system bus is high-speed data transfer between the CPU and memory Most V/O devices are slower than the CPU or the memory The VO devices are attached to the system bus through external interfaces The Input/Output (VO) ports are used to connect various devices te the computer and hence, enable communication between the device and the computer PART-3 Bus Arbitration, Questions-Answers Lj} | Long Answer Type and Medium Answer Type QuestionsQue 1.5. | Discuss the bus arbitration. OR Write a short note on bus arbitration. AKTU 2014-15, Man Answer 1. Bus arbitration is a mechanism which decides the selection of eu, master to access bus. wren Among several masters and slave units that are connected to a bus, it may happen that more than one master or slave units will Tequest access to the bus at the same time. In such situation, bus access is given to the master having highest priority 4. Three different mechanisms are commonly used for this : i. Daisy chaining : a. Daisy chaining method is cheaper and simple method, b. All master make use of the same line for bus request. The bus grant signal serially propagates through each master until it encounters the first one that is requesting. Parallel arbitration : The parallel arbitration consists of priority encoder and a decoder. In this mechanism, each bus arbiter has a bus request output line and input line. |. Independent priority : In this each master has separate pair of bus request and bus grant lines and each pair has a priority assigned to it Que 1.6, | Discuss the advantages and disadvantages of polling and daisy chaining bus arbitration schemes. OR Explain daisy changing method. Write its advantages and disadvantages. Answer Daisy chaining : 1. In this, all masters make use of the same line for bus request. 2. The bus grant signal serially propagates through each master until it encounters tho first one that is requesting access to the bus. 3. ‘This master blocks the propagation of the bus grant signal, activates the busy line and gains control of the bus any other requesting module will not receive the grant signal c5 Ongar Ta AtC eS Normal tugar k———4 pe Hah de ~o | Comtsoh ayat Cm Fig. 18.5. 4 The conteoi input determninen the output state When the control ingut is equal to 1, the vutput i erated snd the gate behaves like any conventional buffer, with the ovtpal equal Wo (he normal input 10 Wher the control input ia 0, the output 1 disabled end the gate gone to a high state, regardless of the value in the normal input 11. Alarge number of three state gate outputs can be connected w Th wires to form @ common bus Line without endangering loat.cg effects bit 12. The outputs of four buffers are connected together to form a single bus line. 13. The control inputs to the buffers determine which of the four normal inputs will communicate with the bus line 14. Not more than one buffer may be in the active state at any given tame 15. To construct a common bus for four registers of 1 bits each using three state buffers, we need n circuits with four buffers in each 16. Each group of four buffers receives one significant bit frou the four registers, 17. Only one decoder is necessary to select between the four registers Que 1.9. | Explain why the single shared bus is so widely used as an interconnection medium in both sequential and parallel computers. What are its main disadvantages 7 Saal Single shared bus is so widely used as an interconnection medium 1n both sequential and parallel computer because of following reasons 1 The shared bus is the simplest and least expensive way of connecting several processors to a set of memory modulesComputer Organization & Archit _ MBC Seq. erty itn attain ll gee Disadvantages of single shared bus are: "The main ditadvantage ofthe shored bus is that its throughpug, ling ie portormane boundary or the entire mulproceasor sate “yt tenet only ome mor een ranted Hy gg se olen pera eres ~ ec G Sans seu eny eta eae = Ten nd ered esi ay Satna ite ae peas _no processor will be able to access memory. — ‘GoetI0.] What is the benefit of using multiple bus architectun compared to a single bus architecture ? Following are the benefits of using multiple bus architecture comy single bus architecture : rontia 1 Single us have kng control sequence reaos ony the data tem canbe transferred over te bin in lock ele. To reduce the umber of steps aseded, moet commercial processor Providesmltpe internal paths using matiple buses, Theintrdectionofineremenser nt eliminates the need to add the PC using the main ALU, Porta By proiingmore pathsfor dts tranarasignfcant reduction in number of lc eles needed to exerts annsructan nace PART-5 Processor Organization, General Register Organization, ‘Gosutions Answers Long Anawer Type and Medhum Answer Type Questions RS TIT] Extain general-porpose repater based organisation. | Jn his organization, the ny or deaation, the registers communicate with eachother not operations ‘anafers, but also while performing various micro 1188 (CanTem.9) ee ternal input MUX a aa pe Be ‘Asthma| ‘unit (ALU Output (a) Bloc diagram aa sk Bea [Seve [SeLO] OF |] “B) Control word ig. 12.1. Gensralpurpserisir based erusization. eo rogter are used pers purputhe cuptf each reer > Sete oe muse MU) input : Three ins re wed ont any on ofthe ven reir z the contents of selected registers are mupplied to the inputs of ALU. 4c Tuners aren flora hipsters athe teanialt 5. ‘Theopertonta i pertrmed Patera epee (on fh mic apron ram & Mayotte apache oe af te cinaon ogee 1 ay ich uscd nee se jin the ALU and is determined ani the information from the data and ase[rawness Stork Orgonazaton Gestion Anwwers 1 | ih a avenary lemente and explain th [awro aie the organization of register stack working of push ang sei] lred set ofelementain which only one element can be 2 Thepantofaceseis called the top ofthe stack, 8 The numberof elements inthe stack length ofthe ack is variable pop aperations te added or deleted trom the top of the stack Last En irs-Out (LIRO) tem mayo Astackisalo known sa pushdown i Organiration of register stack ¢ Won of « Skword register stack ilustated in Conder the organ hetit The four separate reiatrs ned in 1 Slack Pointer regivter (841 Ieenntayss a yal nar) coctiol Antes whieh ude af the tp athe stack He te tek fpomtar SP eontuina tea Pannen ent 8 Tithe val L renter can stone 1 at formation io aw EMPTY register: eae sore | tt information Hos ot se | he ack sempty 44. Data egiater (DR) :F hobs the datas be Irom the stark Workin of POP and PUSIL POP (Performed if stack i not empty Ir. if EMPTY =) Re MSP) Teead te rom the op of tack I : Decrement sack pointer WISP =0)them EMPTY « 1) Checkif rack wom PULLe-0 Mark the ack a fal PUSH (Performed ifstack in not full if FULL # Tacrament stack pointer She SPst MISP!« DR Write tem ontop ofthe stark WiSP0)then\FULL© 1) Check ifetack EMPTY «0 Mark the stack mot emp ‘Gow TS] What isa memory stack ? Explain ite role in managing “eubroutines with the help of neat diagrams Taree Memory stack: Mem -y tackisaserasfmuinory spaces that in wed io Ibe peeeace that sone by procensor and sterpor ary stored in egies Role in managing subrovtine 1 Tho stack supports proprom execution process state data Ifthe main rostion of «program. or exarple ‘which in tora invokes fuseton b 1. funetiom bw Teor contol a fenctien at which turn wil return coral to the 4. To return control to the proper loration, “he sequence of returs tildressen ut be stored 4. Astacis well suited for maintaining this information becouae 1 8 dymame data structure that exn support any fvthe poss at any rena Te adnan to the reture addrem, the stack is sted fo ato s=pmevts othe sbvwutine aswel local or sctermai ‘© nfraton ped cnto the tack ra em af faction call aus Ta laren ofthe corent fume tered i the ‘ase poster pater 1 Wes abroad, the ame ait for the 1m pad ent the sack so that ean be ested RTI] aati stack organization ? Compare eater sad memory sack ‘Stack organisation: Refer Q 1.12, Page 1-138, Unit 2 Become taeinete me ste “i memory from where the next awtractucn: | pre ammcer Sasa pax Ee— HITEC, : " the etal tomporay peravions ALL Ger Mer ost van Register. The an . Ving volved m a 8 the reece tek rare ack MAnAgeS he segue i amnents of CP ae a en carnmzre the omPUtationg mya 17 nao am anthimeti operating St ™ o Sins oe om ary ding adi ead nih # - Gary ot te ee entenieg ey gears be enn ore a ee nents wen i ni Monfcreat DetWeCD MeBOTy and Cy, eel ane tem Fac ae | Baplain varios sexiest of mon Sean Ht ypes of procentor orgunization, (Reno BIS er Tower | Bra rs eared Rls Q.2.1 Pe. oe ord "15, Page 1-168, Unit-1 4 Aoeumulator based Refer Audresing Mode. spaintheallewing desing mode with te einen cee On Diewet i Roginter indirect tig, Implied A Immediate vy Indexed ‘aor newer] very simple form of adres is direct addroming inwhi he o etecivenddron a he operand A= A ‘ithe heaton LJ Fig 1174. Dawe orig imran non eo reference Lo aA Read operand Read netraction i, Displacement addressing: Pray perl ne ef aceaing combines the capabilities of Avec irevsingand rete indirect adress 4 Teisknown by aarte timex depending upon the content of {teas bt the basi mechanism the sie 5. Dinplacerpentaddrestng snguires that the instruction have to, ‘remit eat on of eich api 4. Trevauetotatned nen adres eld aloe =A ised directs . Theuther aligns rtd ean impli reference band ot apc Feferstoreisterhec canton re added to to produce the ‘ects adds i x is gare Fig. 1172 Duplacmentaddesiog,‘ik Malate ‘ seaamnime weno EIA CST ssiresing sin eae tht he et intro te, ge teh eee me Snore a eet Sa 3 unter NOT stn ene aay Joe eed aeumuler =) estan hcg fhe tee colt Bt ne ect istrcion 3 nee ena Nae none a a mk ry mires iv. Regiater indirect mode 1 2 Ampliea 1 Fi Immediate te fcc indret re iia to indirect addressing ‘nl dfereoce wheter tears eld eer emery Ieention ora register ‘Thun for regen indirect address, BA =(2t) Tastee q Fig LIT pte indirect mode thinners pied ipl inth in All eter eterno intrtions that se an accumulator are ‘npn ae introns ‘Zeroadiresiwtrctonain a stack organized computer ar implied ‘eo lstrcton nce th peran ar implied to bron pet ‘ack slo nwa an ack addreasing node, (Cisrectien ] Trapt L- sai waar a en FE esi Seecibremtaretatraat eo 1-208 (CSI Sem) Ineroduction| Inaction Mig. LITE, tamediete nada: ik Indened 2 2 ‘The effective address of the operand ix generated by sing & onslant valet the content aa ese ‘more commonly sy be any O62 Feginersinthe CPU [tis relered to au an index rgiater We indicnle the dex mode symbolically a, 1 ‘There Xdenoten x constant and iste ae of reise inraved. ‘The efecive addres of the operand ia gven by BA =X Rl lathe proca of gonratng the effctive adress, Ube contents of the index router arent changed ae o = soo co oo aJer Organization & Architecture 1-21 B (srr, Computer On ww [Seal ‘Que LK] What is diference between implied and immediate ‘addressing modes? Explain with an example. Pres Immediate) addressing mode Operand is specified in the Iouplied _addrensing mode No operand i specified in the instraetion, | instruction ise = | estroction Son | Tie operands are specified | The operands are eeatalned |_| implicit in the definition of | in an operands field sernee | instruction | than an address fel, This mode is very useful Tor | imitating the registers toa "This mode ssa all regia reference instructions 3 i constant valve Example Example: | | Meeinstraction*Complement. | The instruction Accumulator” written ae = | MVIO6 L__feua’ | ADD os RveL18.] Describe auto increment and auto decrement ‘addressing modes with proper example ? ‘Answer | ‘Auto increment mode : 1 % Mier sccnasng the operands, the contents of thin register are incremented to point to the next tem inthe hat Example Aid (2), 0 Sonesta ie {operand eg 6 Secret tlhe wed an FA to the content of RO modes: Refer . 1.17, Page 1-178, Unit-1 ‘am Refer Q.15.“qa. Pepi the we ese i desi. aux ter I8 rma tack ? cv the organization of regia 8 What ic secseary elements and explain the warking Jush and pn operation’ saw fara Qe Wha is memory stack ? Explain tx role in rae sin th help of ent diagrams, aux ter 18 Gt maple scion pp af promemne ori er fer 136 ion. 8 Eaplan the following addrening ‘ example each : the help of fi, Register indirect picoe te eo cence sa fer Bor addon sa sips Oe oe aegis signe crete lain different types of addressing moda, ‘aus Refer Q.120 600Arithmetic and Logie = 2 ee i ls tars ety meng as ren nw required te determine carry oa 3 Tha By combang arithmetic and gi cirrus withthe help o coc pete wet and apt ee ae ae 5 — To arithmetic] — sos 1 Ti | =p% Pest ee ] pt (en ee ee Pig 2:5. Block diagram of ALD Wins heeds et ae ee ical mits eapatt water coe travel stead 1 CiiewaetS-Viierupae asgcciess hoses tee Sovisteteowscian Sent iopeicary(s emeep ae the namber af arithmetic and logic operations 5 When S, = 0, the ALU performs arithmetic operation and wha! ith. = 0, the ALU performs lage operations. S Weksow tha the carry input not required in the lagi eivevita 7. When lap operation i selected (S, «1, the carry input ast be apes 8 Ths piven asthe outpat sum in fll adder creat ae (Go ¥2498, GREET] write short note om look ahead carry adders. Asewer |] : 2 Carry Lok Abad adder (CLAY fat adder i a type of adder used etal loge,ompater Onemicatin orn SE ioariane empleo tnmat orang MUP a. Fo sepa mabe. 7 Stop Initialise the ‘ 3 Clean , Step4:Chock Usb ce eatin ea Este, tt St edeme eH pigs ef at fs | tiie fo {anne | 5]Acitheticand Logie Uni GREE] Explain Booth’s implementation. newer | ig 241 ne rei is similar to the ieuit eof an at adder, contro plementation for Booths algorithen, 2 cat for postive number multiplication, (cand four register A, B, and, mart oe I 2.41 Hardware implementation fig "Mac cululcates Boats arn 4. Mubipir ad mitpeaod ar ede nt register Gand reir 4 finger ndQ and inti st 0. 8 The nit adder performs addition, tpt of adders comes fromm 7 cue ofaitin. 5/ Sabine therfore, = 0nd pean ise apple as nsecond inp totem 8 der cane of subtraction, Ad/Sub line is 1, ther fore C, = 1 and iplcand complemented and thea applied tothe n-bit adder. Asa ‘erul, thei complement ofthe multiplicand ie added to the eoateot The control logic sean bit Q, and ‘contra ignals to port ome ata time and generates the sponding function ©), then al the bits of A, @ and without addition o subtraction Maltiplicand Q + Mtutipier 2 EQ Sen prem ag tem penta incerctin hn). | 4 Ni) Se Ieount 1 Rapeat pe 2 8 Lath nat ang A 2 0 eteryin iQ, «1 then perform Foc exmmeale fps 0 OR ewehow step by step the multiplication provess 3) numbers are thn when (+ 18) and Booths algo That hold signed numbers. toon | 9 10081 oY eae tooo | n1o01__| 1_| sie | 100.4 a eT sion] 01100] 1 | naw ono _| sono | o | sun 00010 11011 o sua woou_| 10 __| 0 [rea (iter 1 Ts Tanai > i008 | 100) = BREET stow the contents ofthe registers EA. Q, SC during the, procens of mabtiplication of two binary numbers 11111 (sultiplicand) S010! tmaltiplier). The signs are not included.Feu] ' om 100 i va y | one ae inet wer ONT ait ee ent 10son come ee method with the help GeeTIa] tera array mltier Fedo] Hao example. ‘ane seal crtimpleented peri aatipiation call pint ONE Aen, or LED Temes Mig $105 Bia dapan dah . ‘hitalsai terran eae eae JFhor, the fit 4 ole adr ae he et af dct opooenta to prod in pra eae ‘he cary ott ted opp th nt fi anyone red produce et pr pat ‘Toe rlmequent alder enh parca prac with he et peodct Division ad Lie Operations 1 Meee aan pent ay msi Bi mani a ae oie tw chown in ig 210. BRAT ky a i Ag, Ag, MiB, Ag, PPD aa Ay MBAS AD —_——Pr mom mm Fy BM Peta PP Mig 4302. Hanae aintin pr ‘ac sited mica whichis pHa eter Dor | dapendig to hecrepnding map icaled Paral Prod PP ae prca pase os ur pout conpenents, ° PeABoaa, | ‘Long Anewer Type and Media Answer Type Questionpumnicertsemsy __Arveteunilags nt Geet] Wete down the wep fr restoring and now-restoring o¢ division operations, Jarwer Restoring division operation: ‘Step 1:ShiR A and Qe one binary positon ‘Step 2: Subtract dio from A and place answer backin ALA —A~B), Step: iFthe sign to Ai, nt Q, 10 and add divisor back to A (that ia, eatore A) terse set Qt ‘Step Repeat sep 1, Zand upton times, Nom-restring division operation Step 1s Ifthe sign ofA a abi A and Ql one bit position and aubtract vine rm otherwise shi A and Qe and od divior oA ‘Step 2: Ifthasign of AiO et Qo there set Qo ‘Step 3: Repeat sepa Land 3fora times ‘Sep 4: Ifthe sgn of ila visor to A. Step ¢is required to leave the ‘roperpakive reine in Am the end fn ye, eet] Draw the flow chart for restoring and noo-restoring ‘ivision operation. awe] ‘Flowchart fr etring vision operations shown in Pig. 2.121. puter Organization & Architecture 2138 (COTTSem-3) ‘flow char fr noo-enteringdivson operation in hown a Fig. 2.122 @ ao Be Diver De Dindend Count em No Yo. aw aE Ae BSE] eee esate patho mquery avr Give the nen rstragdvslon slg for unsigned itor ‘Ac theirs sigurtem for aslged ltoger tes sees inane Eo)14D (CT Sem 3) Arithmetic and Loge Unit mer Detapath of sequential n-bit binary divider nex anim tor nonseterag divin : Rr @ 2.11 Page 2128 van orerampe, consider bt dividend ane 2-8 ioe Drrseod = 1010. Desor = 0011 opie Crmcain tAnhiecary 218 BC8MT Sem 2) Ingiven example Ire eae er Acre raga Aw pnt ad ben sep 3 ot WET) Pete Besktt he division proceas of 00001111 hy O01 ae 8 dividend of bits, Gee Brot Beteu Overflow: Over i coding when to mambers within gts re aed a Qierearenimeseuppegs + Tet a REBT Spelen dagen eter bres the amt fe ‘ome punt werd iret tring awe en of erie Toe sec aneefige 7 Posive averflow eter te iteeet ret antenna arg tae a8 Tiina nage mb a8 a< ett ste sae a Std her Stet 80 oa a vets eaten ee Given men be eee ‘onbt re 1 oui miso att 38 Tee one? Tawon 78 xy ore Sreveton #9 x he two carries are apa ‘pee cari ae lhl be detected when thr geguats thie OR ee i“ fe gate 2 ~ Arithmetic ond Logie ving Pont Avihmeic Operation Pasting Pit Ashes rman : ‘Goestoas-Anewers Leng Anewer Type sed Medium Answer Type Questions [CTE] Ketan tne basic format ured to represent Noting otnt numbers. SS ‘etn patent ha he Bel BF alge eget trie ether he number npn Spi 0 ear te lr and ese pe 4 Theexponent: Toe cgont fd onde to represent tth pin snd teretve eon To doth tanec to cd Erte een Po IEEE sng rsa ‘Se tapeea Bilin Sand hs Uae vl af Fe ool a. Breton nt lio tn neat ‘ston, alm known athe sgn (Computer Orguiztion& Ae taper —— Sra carton ‘Ten pera retro Dott mambo in 2 * | Side pecan FMR tae s_| © __] Deeb pciame ire] Steps fr varios ating . hades end marasdon nme opener Seep Check see, Sept: kie ane hdr mtr he mania Step 4: Normale re [B56] etn tnt ortho creat th the ble tore ding. ‘Arete et pres pan th nin rant (Clutporabel cadectnbearar tte cea [™eRoDeUew arsed fl ar, nd prorat surscnsftn nd ate 2. RUEROR pisae wotrceicrencrs Speco Peseh ones tam ae‘Tables .181. Truth able of EKOR Gute, ee eee 8. IfC=0, the toput variable Xin either O or T output terminal = 1, the input variable Xs elther Oo 1 wil be ‘eanaferred te output. By wing this EXOR gat ‘pateinthe Abitadder/oubtracor crust.utp Dot Pet + satpt of AND gate that in Wen Tacit ‘lve. Thiasignal in applied to Chmd FF wana Osing yt rte IEEE 74a Ranard er Soting peat comp TERE Ta ncmters are dein tweet OTe et rember -btar tnge Pe ee ue ne ° 3] © © cecetecahy Songend DBE Raat acon een orem Pg 2201 Sa prs ‘2a Noting pat umber ge Prin i epresest ewe {Pi relate betwee Kad Fs single pecan eg oer im The Biot annigned for expraeat Modind expect ii the range 0 B+ 255 fr sormal vanes Thaw the Ata, cxpoent in the range 1272 8 IZ? ‘The values O nd 25 ae und to nates the Saag pans ans of erat Oana ast reap et? Double precision The focting umm ie 64 are doe preemson Pig 2222 there the dsbieprccnor rato TERE saad form ‘The doubie preci format has increaund, expect ad ‘Tie tanned forenguanet Fhe rag << 7 or (veal ales Tos the arta! expect Bs the age {cis E1008 To rwstnip etwewe Kaa Bix de : prec in oven as B= Bs 1h Tor Af nt corgned for mations, provides « prion (rrornieat te sho We deea apts Freeing eat nal os eue pvc epee cries Foe fraction, 02022-0500 20 050-2: tom ot (O12), «0000, (140 125, © ot 2000 an, step 2: Normale the utr "ol1oti0100 01 {oiotiovam ingle precision: Fors given Boating pn minder, Toviotiotuagot ran aia \or) mae apace fo wg yee Foire Digi wear, ata, Sarber i sng prime armaArithmetic an 2. 2¢n (cSt Sem Double precision + Fora given nu Lontd10100001 Se B= af = 0110110100001 ‘has ar muifidexpanent for double precision Bas 1003, = 0 1023 = ins), = (19900002001), asain a AR a [oJicoonnioarg oro mea0or 9 1, Describe sequential Arithmetic and Logie Unie proper diagram. ‘ama: Kotor Q.2.1 Q2 Explain Hooth’s multiplication algorithm in. Ans Kotor 2.8- 8 ew ea pho See Recep of complet matin {rcs hate et fo sme Holer Q 28 eeeInstruction Crete so ‘rae ‘Pech ad Baeoute ote) iro operating, x ceution oF Comat: nseThinimtreton will maltipy two operand A and 3 and result ind Describe the typevofinstructions on the hasivof, fields wsed in the instruction with example. Tower | Four types of instructions are available onthe basi of referenced Sele Let us evaluate the following arithmetic expression, snatrution pe As BIC+D) 1. Three address instruction : Computers with three Instraction formats can use each address felts to processor regater or «memory operand. The program in Taguage to evaluat ‘DD App 2.0.0 MUL XRIR2 MIX]e RL RD ‘Two address instruction : In this format each adden sy either a processor register oF a memory word. [neuage programs towvaluate arithmetic expression saa Kia Rie MAL Tose a Ose B RSs A+B)‘Computer Organization & Architecture on [Explain the different cycles of an instruction execution, oR ‘Explain all the phases of instruction cycle, Instruction eyele : 1 Tactrution eel sa complete proces of instruction execution, 2 Wisatasic operational proces ofa computer. |S eis the process by which a computer retrieves a program inst from its memory, determines what actions the instruction, and carries out those actions = ‘The instruction cycle is divided into three sub cycles ; Petcheyele Decode cyle_Bxecute cele Gam LS. Haan [a |. The opcode whichis fetched fram the memory is placed inthe Data Register (DR) (dataaddrese buffer in case [50S5). Thereafter it goes tothe Instruction Register (I). | Fromthe instruction rier it goes tothe decoder creitry, ‘Afri pends decoded oe CPU comes a canister snd tn nro Ppl tet inten i pie tpn eae ai anioadeat BRET ite the steps in fetching a word from Ditereatine between branch instruction and eal)Computer Organisation & Architetare Novas (Take actor etter in wie i Sato vty ADDR, RR, (Nal waren, ade, nat gil stored in Ry) ee ‘Thus, Ky has valve of 12 7 IWalue of is subtracted from Ry and noe et keto 5 Si MULE, 8, iMag wih srry eS cen ole steel lle og werneeane ps tnstrectdon cat here aa eer] instruction word. Bit 0 to 11 convey the address of the Iocation for memory related instructions. For non me instructions these bits convey various register or UO operat Bits 12 to 14 show the various basic memory operations ADD, AND, LDA ete Bit 15 shows ifthe memory ix accessed 6 indirectly. For eveh an instruction format draw block Of the control unit of a computer and briefly explain instruction will be decoded and executed, by this control bi designated by ‘The mode bit iO fora direct address and 1 for an indirect {A direct address instruction is shown in Big. 8.7.10). Iti ‘adress 22n memory. The Pits 0, o the instruction is recog binary equivalent of 487, ‘The control finds the operund in memory at address 457 and added the content of AC. me “The instruction in address 36 shown in Fig. 8.7.1(¢ has « made To Therefore, ele recognized ax a indirect address ‘The addrose part i the binary equivalent of 300. The address 300 0 find the address ofthe operand. ‘The address of the operand in tis caue ix 1350, The oper address 1960 is thes added tothe content of AC, ‘The indirect address instruction needs two references to {atch 42 operandLat it 15 6 ‘TReLCikt Sequence Counter (SC) can count i binary from 0 as ‘The counter output is decoded into 16 timing pues 7 ‘Tre soquence counter can te incremented ty INR inp or clear by Gh input synchronous FERRE] scribe mier-peretion ad ela trp,Computer Organization & Architecture S11 Garry wae Ris HB yt FE nt symbol forthe 1 complement o 2 Adding tt yy complement proce the 2x empl, , 4. tng he cotents of tothe scomploment of Rie og 1-2 Te other basic arithmetic micr-opertions arg ‘abled 104 Table 310.1: Arithmetic miro operations ‘Symbolic osiation emer [eR | Contents of Rn watered BS me "Compleaent te content of Re Bee Rit iat ‘Rint __[ Decrement the eontents of Ty wm 7 z 1 [Ree 7 é 7 GET] write « short note on logic micro-operation. Answer | 2 Laem peta mtu pert ong 2 These operations consider cach bt ofthe register ‘he contents of two registers 1 and R2 symbalized by P: Rie RLS R2 It specifies logic mizro-operation isto be exeeuted on the ‘nts ofthe registers provided that the contol variable P= 1 For example, the eontent of Ris 1010 and content of 2s 1100 content of 22 0110 content of Rater P= 1 ‘The Boolean functions oftwo variables andy are expressed {orm in frat column of Table 3.1.1. ‘Table 3.111; Sixteen logic micr-aperations,an ret, etn meses eMart oy ry (ESET) ant ; * gee taal shi mir operon e ircutar shi scepertion * tranaere #0 (zero! throagh the a lB cedar he eps meron mrp ntrandereinngh | «Repth rctia gerrae BL orf lal dit ato i ta ee at dasa aw w Pade meeee dc etme ih ie | : ecerce * | diss reame rmny be carried ou by CPU? Explain each cateyory of mero 3 12 ahowing th gli ight i a follows ‘operations ving one example frvor 89. Pe 998, rage 3-108, Vit Tis, vats 18, Ua cs ee Nepnatacnclae rec BEE yea annem ae onand meinen 5 Beem tigtrctin ce rat te monte eect te tation nc ced ration tote prtrmed, 5 pedo apn the ora Pert in poe a lm a tated ty Haig th en MAR abd mg vet theme me ny ae tranaerted by meny re te a An are arate ALU pa ctor 4 | og Atnwer Typ and Medives Anewer Tye FoeBTO] Wha cE Rapa charaternion seis Marks 9] ca om] The tert CIS" Camps ntrction Set Coe ners to computrsdengae wth fal of hat ree need ride ce eaparis me met IC hae umes sera 1 variable longth encoding Dore an 1 Bie te lag muni of abdesg ee forthe perations 208 ration he CISC mp general cog fr (vor he venga, ne 14 PrSer wring fr C13 archtectres tend t tae los carectorntin of CIC: emunuest cmatr ee reer icmp oer hgh then the perfor the CIS mere tte o mpemet — SC tendo hve many nara format accord end pean pra iene net 3 Gscha aay anrcton rat stig GIS precast proves dete monipaation of operands residing “Gue] Discos te adeatnges and inadeaninges of wing * viable eng inatrtin format, eral engin instruction forma: Cteton ope 2 Mlreniog contre Bulwer eee narering mesAcie on rite short note om piping Computer One seperti ect sent = ‘The provennr executes & iter het se tes of aeonce of fetch Eis nthoeie Pie 218. Thiet Irion oer iu le 6 Now consider acmpute nt has two eeerate RORRREND rections and another for executing then, bene ee [etch nod execute stepe of any lnstroction can be lek ele 10, Operon of te computer proceeds asia Fig. 9.193. Clockeseleiasruction 128 4 11, Inthe fest clock yee, the feteh anit sand stores iti bull B, a the end oftheecoreanennas Arner 21 Crp, _ toad Acne _2 SI HET oy ao Fig. 2202 Pocesne spline Inseruction pipelining = one f gstractins can te pipeined, white sion eck ahead TS ATe EO epeeMardiived contol voit: se tcnrr nea equentnl lie iat ora ale ‘gona a contra sale oi pent 2 Fieeint ages implemented with ete, App, "ata te—- 2-261 CUT om 9) Hespemratte e contrast hardwired and micro ts. Alo Hits thelr advantages and (RU BOTT TW ty] Tsplnin hardwired and micro-programmed control and compare on What are the differences between hardwired and miers. Fepin the hase concept of hardwieed and software contr unt with neat diagrams. P| Hawirod control eer @. 423, Pago 288, Units Micenspogramined control: Refer 3.24, Pape 3-208, Unie Programmed control wait? eisai a wit Itmera hardin ental end mic proransneg cic | “oo | eid [os fe fs tm | © ietie —tSoeesnae——t pom ——~+ |__ litem” ae -_ | = ‘Sistas otal ental Pant Dinas o hardwired contr! wit: 1 Expensive taplomeat . Cimon ‘Adcantape of 1 ehegerinines 2 Lan towe pee 3 _ Gata ry ne pce ge. Disa satae of miceoprgranmed entra waits control unit "RGSS Weat ie mico programm contra unit? Give he asic structure of micruprogrammed crntral anit, Also dn imicro-nvtruction format an the sontfl wait srgerisnon or {plea icroprogranmed contalers ining sacle dageaee SaeaioReiawn | Micco-promram Guinn Page 2 1 [a : cole] wa OS SPars worn Falls ean or amhing oo panel Nb alton ld he ‘the its fe er instruction ar = ee seam, Pai ogee : Ie ttt dc aa hen Beni geein cli ca tee ee ar coop eer Se an sera © Race conse oe age Oe rotachend Onolins o meee ner orl a Taran tnenecas See er i tla Seon Se afer of SL SS J Sf — rogater ‘row | | eogeme fH rat ide sta far Fonction! parang ‘lg. 828. programaed conte rpaination 1 Thecanta memory addrens restor soci the adres of te {ineastiom sd the control data register hoe the le ed fon bemory, erie 4. TRermenrinstractoa contain antral word that specifies one tneroaprations forthe Gat process Once these epersteny a ‘cuted, the control must determine the next addrena. 5 The lecation ofthe neat mire inctruction may be be ope next ‘uncer my be oct ed sonst el inthe cota 5 While the micro-perstions ar being executed, the next address ‘cate in te neat addres generator ere and then eco incor addres neater tread the next rine 328M C8TT-Sem9) ais 1. Thera ens a tng sept auc remn pas nda Ce tent asses oom mimconaceey ‘The next uddvens generator ix sometimes elled a micro-program = ras it determines the address sequence that is read from a a a conte adress ese yoo nag athe contol aren ete este taal amy eater oe ae Senco setae seca a ae iat ‘holds the present micro-instruction whale the seceiieteetoanr cared omeaoor PP neepeme nia eon s oS 4 short note on micro-pragram sequencer for control memory. on Explain miro-program sequencer for @ coutrol memory using suitable block diagram. (4 Te hic tho ares souse pide by the vest {sformatien bt thar seuener receives from the pom ml 1 Alle netrutions are loaded inthe contr memory.1 The present mero-inatraction i placed in micre-inatruetion ny fer execution coding of contr [* [eee ant perating spd BBB] bescrive micro program sequencing in detalt, 1. Micro program mquencing is a prices of controling the gesettion of set addres 5 2 My orogram soca ix done wth the el of meron sensencor 4 Amer program mquencer tached control moma ap crag [Sia metronome ermine eae+ eer tapraian et ofopratins hat the proc ik Microinetructions| fi Mcroinstruction iit Mioro-peogram It Microcode Control memory 1 URSiiim to execute the major phases of instruction eel, ‘The imaration cele has three major phates af teh, donde ieee function of a CPU is to execute. 2 Deri tote to eee 1 Micr-instructons are the dividual control words i 292m (C9TTSem.9) or 2 Mis wed ane temporary stnnge fr data Aecnasto contra semen data reise ie than to sain meron this speeds ip CPU operat ‘Write an ansemly level program for the folowing peewdocade: Bihan wat Bate Soest RES) = (SUM=0 cea oe peas tae “(Add Ato SUM us Add B to SUM sein ts eae Mood C10 AC Ine ‘PRreate Pe camplement a ‘Subtract € trom DIF ee ene est Bo est & pa Malt WME Se eee, oe Fhe dagram of 4-6 combinational cru incrementer i shown in 2 Oneaf the inputs tothe eat significant Half Ader (HA in connect fo loge and the other inputs tonnected tthe leat sigsicant at of thenumber tobe incremented. Peete tee it is comected to ane of the sone hisherardr bala apt, Pace settee tren yi onan The also causes eeputetute LAI HICMIT Sem.) re: a, 4 nay neem mei, the clack ple trang Tor] Initialise counter {Preamplement of NBRINC stacTe ge NBR te unter La ape : vor.cha 1 seve 1 iseTR | ieremont counter BUN LOP | Branch to LOPICTH 0) mur |} Mate wea Cra= 0 [SR MEX FF NBR ofeiared worde one Counter ‘ADR. HS 500| ,3.85 BICMITSem, bina Nev Re 4 Atirne nel rn ate arethe fur srmls ORG, © Reyne and eX subroutine that proceases he aurmbert a abtie th te serene of the meMory-eerence vicavade quent Thee lectus he ee roe aceontaves he epmbols fr the 1A teatro 2 Ta no RE a ther 1 ney eo ga ae oer deterine We inary vale _| jing quetona are very important. These questions |Fotacing ee in sour SBSSIONALS as ell en UNIVERSITY EXAMINATION. | (D1. Wat fe an taptruction In the content of computer re ena apne ie vatowr ace SF mcaon ih tne bly afc cpae rane VERY IMPORTANT QUESTIONS _ 42. tvaluate the arithmetic statement X= 1A + BIC + Di using ‘Shaneralreginter cocoputer with tires mareen two dre tind one address intruction forma program to elena the expresso. ana Heer 33 (3. Explain all the phason of instruction eycle, ne ete ah 4 Write the steps in fetching «ward f Differentiate between a branch Instruction tad tal aan tetera S.96MCSITSem3) nae ait 5, fran instruction format: there are hits in an instruction ‘word. Bi Otel couvey te iy = var memory lation for memory related insiruesions ar nom m instructions there bits convey various reqter = ‘operations Bits 3 to 14 show the various hase memory ‘peraions rach ax ADDL AND, LDA et. it LSshom ifthe ‘memory is aceenced directly or indirecty, For vuch an Iratraction format ew bck ‘it (ota compater and riety xp -“ ‘be tdeceded und executed, by this control unit ase Weir at 6 Lstand ain diferent types of shit miero-aperstion fm berg 07. Whatare he iterent categories of miro-operations that may be carted out by CPU? Explain nach category af Imicreoperation: psig one example for tach aaa feerg oh Qe matic tan Retr 2t3 2 Hxplaia en characteraten. 2. What i ASC 7 xpi ts various charnetristien. premiere 2.10. Give the dotted comparion between RISC and CISC. ‘ame er 2tm 11 Write «short note on pipelining ‘ame eer Inthe basic comcnpt of hardwiced and soft ‘contrat unit with meat diagrams. aw Heer 325, fnganlestion for atypia! micro programmed contraliers Sea ettate diagram, paw Teter ae 14 Write short aote on miere- program sequencer for contrat ame Hor 327fg Arshitetre B87 NCAT Som MT Sem 5) ‘qin Brey desing the ooing e08: P Mierw-operation 4f Mierocimatenetion fr Aticro prorat fe Microcode eer 830 iy 3 eamlyIevol program for the followin ER Becta vent program forthe following pug, SUMsA0B DIF = DIF-C SUM = SUM + DIF pox Beers 4.1%, Explain Abit inerementer with a necessary diagram, Spat Refer Q 332 ts: Write aprogram loop Using a pointer and a counter to¢ & ee etiana a0 to SFR wi the conter ams Refer Q.3:38, 1@.18, Demonstrate the process of second pass of axtombler using ble diagram. eee 2424 0 Mews ON Mesories Sn Replacement Mownete Disk, Magnetic Tape Cope mpeeen 1B (CST Se) CONTENTS 42 eeeFig 4.1.1 showsthe Acca time sceneyanmic sateRAM. oe mae Random hve Memery (RAM) a amo Sema ion wonee Reqemtly ted prone Seman th roel epee of eye apm. doth ter car ‘herefe the date need ob felted portal “ype ching perma omptars ta "forms he mala RAR forthe computer 2 stam sriceatniter ‘= State Random Access Messony ie 4 SAM aati in at. ecg mere power le em sd mae baa 2Memory Adress gitar (MAR olathe adres of th Tededhe operon weneeted, tn Pig 4.81, MARI a ‘Te cantent of MAR ie dcoded by an vest dene on the "Sinead nord. ‘hncolsineh un reconnected x ena ‘atin Tow bt nes ure complement to cach other. ‘The samrie crue activated by the Chip Slee ‘Theme cients ce connected a Uh at ie Gt Duna read operton, these ict sence o ead the ‘iedin cells a nerd se a tre th {obednestnoe 1 a write the sensefwrite cireuite receive oF © pena remit ibe cee Word bat ioe |sder x5 pastes! ze 1.280 organnaion there ext seen Toe coment of MAR dived note pert andy umber of ite ‘Theamber omen egal o X= 2 driveline fin the el arvay andy sen bite decode ratte imeem seman a re array in otk there ‘S50 somber oft ne ra bp word memory ‘hae rns hy MAT, secede “Satcher ty tro AR whe parca word iene ge hb umber ots nthe ary are acemted by enabling Serontfoeands monte ines amahesenatyAm UCNIT Sem) GT] what i ROM Paplain the types of HOM on Raplain the semiconductor based ROM memorion “Anwwor | mow 1 The Real Only Mesmory 64 type of remiconductar memory thay jp designed to held data that ta either permanent or will moe frequently 144 las kaown te non-volatile meenary ‘Typer of ROM: {Programmable read only memory (PROM) 1 isc programmable ROM (OTP) and ea be ‘reuramined via w apectal devi called PROM p writen to ue orm wes permanently dsteyy ives within the ip ‘Consequentty. a PROM cua only be programmed once, Eraable programmable read only memory (EPROM): 1 TYplealy thi device aes high orereate internal inks ise ar 1tcan bo erased by expose to strong ultraviolet in {10 mint loner then reiten a a oe ‘ners apt hight ase Oa Rerrted sport UV het wil vena wear ota 2 mt ie euranc of mont BPROM chip exceeds 1000 eye ‘erasing and reprogramming j [BPROM chip packagos can often be ident # Memory With programmed VO, erie Pind then st the appropriate bite in the UO state ‘Tor 10 module takes no further action to alert the CPU {i does not sterrupt the CPU. Thos, itis the bility of CPU to periodically check Toon dedte amit Gnd thatthe operation i complete,S128 (CRIT Sem) { Porenumpl « FCT otal nd shad dre controler eu ‘Nirowe rDNA col ck ogra for DMA Add, READY and WET, Micro Data be Working of DMA controller + Wher the peripheral device sends a DMA request, the DMA, forming the CPU to relinquish ‘respands with its BG line, informing the DNA ace diblodAdeantage of inlated VO aera oeecos of 10 wre treated in x eeparate deenain Trea a 1808 addres apace allowed for memory applications. ae marine the PO operations isolated separate’ RSIS Rovaee te peter these operations [WO meena operate fat 2 The SQLite rary pede leas RAM. Diaadvantages of memory mapped YO: L Man BO erret on memory-mapped fle cannot by spptcation eohia ino program crash mene Performance @ reduce bythe ane of emery mapped LO. BETTE] wea do you mea by Input Output (U0sre cheaper a loc nat ee ro elt ted for applatine where or ‘eeanemission © of acne igh proprson of the tranentied eer amps ad Unis arty no el GaeRAa] Dittorontiate Peace nine! and handshaking asynchronous dat rat and asynchronous tr Syachronee cnted and Bitoriented protocols, Gaara Tauerrupt initiated LO techniques, [ARTES 1 emplays a singe |feotra ine to time| lcoch transfer Jcknowindgement| Reply messages oot Iproeat 5 [tacking |p ay 4 | Tiniagdiagam | SESEProgram : EXT. XXs00 XID, XXTOH v7, 108 NEXT: MOV AM. STAXD XH INxD, Der 8 INENEXT Hurster? fare ro 204 "which are: ain i fixed position: Be epoying a lost Pm tne various facts related to bus and re fated to bus and bus sy “Gi multiplex kreist ‘lin cor ates needed toconeruct ha serum ofits in each register. 1 the cach mulipese, mua be # x 1 sinoe it datalines. Give various advantages Various advantages of polling The pioity can inthe controller Ifthe one modale fal ‘Basie components of) Rogitere and their functions i Taformation Operations transferred atone time.compuer One Br What is look ahead ‘sas, Alvok abe carry adder Ay reducing the amen 22 What is arithmetic and logic Arithmetic circuit: 1 « am anes operaanns bm 1 'AND, OR and NOT ete cireuit Logie circuit operation sch 28 23. Define following terms: Micre-operation + RIL ae pert: Reguter Transfer Language (RTL) is Siiutythe internal organization of digital [io peccse manoer. Ie can aloo be ued to facilitate 25 What is the is the need of having many addressingrcitecture computer Onesie ‘ki, Raplain one, two and three address instruction, instruction : One address instruction MA ne address * dro (AC) register or al da ‘re ace ona pntraction inthis format each dress nesceanoe register of a memory word. ‘Smemary operand. 432 What are the various facts related to operation code: Anz Various facts related to operation code are Thr mimberof tate required for the operation code ofan vail the ependson the total number of operations & The uperation cade must consist of at least m bite fora Astin! operations. 33. Define the necessary factors for instruction um Necessary factors for instruction sequencing are : T Rencedea counter te calculate the address of next ‘execution ofeurrent instruction is completed. i Tein also necessary to provide a register in the control storing the instruction code. "a 4. What operations are included in micro-operations ? ‘Asx Micro-operations includes : Transfer a word of data fromone CPU register to another Ale, | Perform the arithmetic or logic operations on the data (CPU registers and store the result in a CPU register. 4ik Fetch a word of data from specified memory location and lod into aCPU registermagne of the micro” “rth specie ation chit rere D raion | One micro-inatr : Tae naroorons | Sorrel seqoence, Ong aan gewuted dunb6 * aly ifthe ‘Straight binary code to | ero sep on E oe | Gach micro-eperation. 7 inti ppesfnde the mie |code contains the eoatral Sova without a7 Hori aetrction contain a lot of ‘Sais and hence doe to that Tite alse | be decoded toa | ke number of£0-11B(C8AT 56.5 3) aces ser merase are ec (ARTO ROIS 16 PTT Mara sax ACastnt Addrenable Memary (CAM) i ici that comes Aspartic storgenuingidevie isa ta ‘Sitar andrending avord ken RAM we spp thes go EAM ook to ee IF 1 has a copy and return the ie the satching ro. oF the ane Ausibary’ 46 Whats CAM? 47, Which of L1 and L2 cache is faster ? ane 1 All processors rely on Lt eache, which is usually located on processor and is very fast memory and expensive, the 2. L2eache is slower, bigger and cheaper than L1 cache 48 What is cache memory used for? ane 1. Cache meinory is used to sore frequently used data or instruction, 2 Cache memory is used to improve computer performance by reducing its access time. 3. Acache holds instructions and data that are likely to be needed fr the CPU'snext operation, Gina earedeie na i diaentapr artes saps tte oud Bre nde ofr marlng th the Mt ain drop Beacon eee 4.10, Define access time, seek time and latency time, ‘AUS Access time : The disk accoss time is the time delay between ‘eeeiving an address and the beginning of actual data transfer, Seek time : The seck time isthe time required to move the read/ write head to the proper track. Latency time: The rotational delay also known as latency time is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed section passes under the read/write head, 11. Discuss the advantages of erasable optical disk. 120 (CSIT-Sem.2) antares of 9 Nveide higher eel 1 Per seca Re prtsble soda Ee px. State the disadvanty, ee be faodvantage soe Plcadvantage oer * een teat 5 verwrting data on ma he magnetic media, sines o, o-optig sory a second is required ta yryft'Slitgn tg oe ite hatte ny sea fe 35 Whats memory my Memory Managemen a 2 thecomputer theta ADR? sent to the BU ange semaine teeta table for matching physical men, Y Rathngetteage since 8 roe Ser yng, Recreate called @ Program status word or pgyy tt * CPV ig 2 Ther SW ionored in eeeeePoW Hoag the status information that characnes et PEST and, i characterizes the tr 3 Helder tenn et specifies the interrupts that are allomed osu, PPEO0 ad it CPU is. ‘operating in a supervisor or user mage Meth the i, Delayed load; ut made, 1 vip codeine rte any the load instruction eshte ea ee 2. If the compiler cannot find a useful. ‘instruction | ro pa 4 belies onmopivaprneaetin ete isiea beatin are 4 mgperatia, has wasting ack ye berm stone freer tT saa is referred to as delayed load. — {24 Explain the following ermy, Delayed loadampte Oe sas. What son vey arene a cay ced rae atin re ory aces pale? enventy ‘epsom th rivet difference beeween RAM & ROM, 416 Ws we RAM Fr rondow access memory (RAM! device allows data Hers to be read or weiter. almost the same amount of time irreapeetive of the physical Toeation of di Inside the memory Types of RAM 1 Dynamic random. (DRAM) li. Static random access memory (SRAM) @0eme ream wae i ea Seoamo programmed 0 and interrupt driven VO, by the epee with which the cay 54, Compare PF spinterrat ina + ready tovend inforas gaat is implemented implemented using 1 ts capper. [hardware engert. enna i doer not depend on {interrupt must be eAablad ie . Lnrocen interrupt driven WO. DMA controller fa required -out data transfer, a T An VO channel has a special-purpose processor. 1 The YO istration are stored in alo meray. [The 10 program specifies the devices, the area of memory priority and actions tobe taken for certain error conditions, 8A Explain the type of LO channels. ‘Aug There are two main types of VO channels ; Selector channel & Multiplexer channel 59 What are the modes of data transfer ?a of modem in synchrouous com, rAehroN commy oo; (ART ROTE ets Sear cain abe rac Seal ema he meri we Te modes werd in eecinae SGRET beang transmitted in the cornmunication fe 7 that 18, Describe eyee stealing in DMA, ad Me A IMA te tp Direct Memory Access (DMA), cele stealiog is « me stoning LO controllers read or write RAM withove een sithehe CPC 2. DMA coctrallere can operate in cycle stealing mode in cooler take ner the ba cach tof data tbe tages then return coat! to the CPU AIG Write the difference between serial and paratie, a | Scion | comuttension | sommaaitin Wang Distesindecin | Mali never ig | wget udeate, Shoo | | | Genacacine MS Espesive >| es steer tine) Bins [ate transferred at 1 clock pulse example, computer to printer, | Short distance. For | |csumeniton or [ns a Oo oneaitnn& Areiag By, nati ‘ech, (geM. IV EVEN spy, Cte atriui ea sel melee * iain ttn at as coon en oat nc ow a eo, Simplify the following fn cireuit using AND, 0} ha * Fa.B.eD wane MAPA ay « ‘This qestion nowt ahaa, a8 4. Add ~35 and -91 in bin, Ys complement and signed Fy et, ny = Refer Q-2.15, Page 2-158 tage enema snow sy yn ema algorithm when (+ 15) and (13) gare ibe boothy tines. begun eee Refer Q. 2.6, Page 2-88, Unit-2. —_n 2 Attempt any two parts ofthe filming a What is an instruction in the of an instruction with the help f« ample insets format. Refer Q. 3.1, Page 3-28, Units, = ‘a, Explain the following addressing mae withthe bapofas example each : i. Direot Register indirect ith, Implied i, Immediate . Indexed sux, RoforQ. 1.17, Page 1-178, Usit1 samc? ra 5B, Units. = Scorer oven, ena 0 Refer Q 5.10 pat ne 08 Peo MA: Refer DMA Refer 512. Page uy bd ee) ot he followin raorired nod lero programmed Aer any rar sevantanee ee nee ee Foe +258, Ut _sagoriee f mlere-operations that 1 ie cach cology elmore 1b. What are the different c ried out by CPU one example for each. maybec con pving one exA2 ane erg 318 Page 1B, US lowing: e Write short notes on the fol rte shettam mequencer for control Memory. Page 3-28B, Unit ame efor Q32 i Ruse. : Refer @.4.17, Page 3-178, Unit 44 Attempt any two part ofthe following ier TR Gitterence between isolated /O and memory rast J UO? Buplain the advantages and disadvantages of ‘each. nun, Refer Q.5.13, Page 5-138, Unit. insider u cache uses «direct mapping scheme. The size of IK bytes and word size of cache is 2 bytes ‘memory is ‘The ize of cache memory is 128 bytes. Find the following. b L. The size of main memory address (assume each byte of main memory has an address) ii Address of cache block li, How many memory location address will be translated to cache addrese/block/location ? iv. How can it be determined if the content of specified main ory address in eache. mx Refer Q 4.16, Page 4-18B, Unit-s Explain the following memory schemes discussing why needed the: L Interleaved memory {i. Associative memory uma: Refer Q. 4.24, Page 4-24B, Unit-4Solved Paper (2015 1, sr-snicotT Som) . B.Tech. (SEM. V) ODD SEMESTER THEORY ATION, 2015-16 COMPUTER ARCHITECTURE eer SECTION-A| ves Ang yr Al yr cay et rh el ac Woe coe mla oretage oT? Lb Matte i iar ocran Urs tee rt Quentin Define control word. ae Refer Q. 18, Page SQ-2B, Unit-1, Two Marks Questions, & Give block diagram of microprogram sequencer. awa Refer Q 3.15, Page SQ-7B, Unit-3, Two Marks Questions, @. Why are read and write control lines in a DMA controller bidirectional ? Aa& Refer Q 513, Page SQ-I6B, Unit-5, Two Marks Questions ‘e List two important instruction set design ismues. ‘Auk Refer Q 8.11, Page SQ-7B, Unit-3, Two Marks Questions, List the two techniques used for grouping the control signals. Am& Refer Q 3.13, Page SQ-7B, Unit-8, Two Marks Questions. Which of Li and L2 cache is faster ? fax Refer Q 47, Page SQ-IIB, Unit-4, Two Marks Questions 1h. What is the use of modem in synchronous communication ? Ama Refer Q 5.14, Page SQ-17B, Unit-5, Two Marks Questions i. What is CAM? ABE Refer Q 48, Page SQ-11B, Unit-4, Two Marks Questions J. List three types of control signals. awk Refer Q 3.14, Page SQ-7B, Unit-3, Two Marks Questions penne Ne mete, 1 the ade fy 7 er chaining bon eta Sy peter @- 16 Page eta ene 4 i A ag, riety defi She felwing mat {ee Nery, a # 2 Einar © gefer Q. 3.30, Page 3-aap, 1, Z ag at do e 4 fat de, Tot 00 by ay feler @ 428, Page d2en, "he i it is sxplain various typeg = “oe ‘ ot Bee 1178, Uae tay, 5 Esplain the weauence that tay, = ‘occurs Place, feler @ 5.5, Page 5-88, Units a 1 AcomPuter Use RAM hip ee a eed eee aad ho hy, 4 Hee zany chips ar eed pe mc tothe address bus, tow techie cman oo: Befer Q.48, Page 118, Uneg 4 AROM chip of 1024°8 has four from a5 volt power su opts PD How may tt pg the IC package ? Draw & block, and output terminals in the Row! 5 Refer Q.4.9, Page 1B, Unita, differences bet tween hardwired ws microprogrammed control unit ? sm Refer Q. 3.25, Page 3-258, Unit, i What is RISC ? Explain its varioos ws felerQ. 3.37, Page 3-178, Ung. unitSolved Paper 2015 1 SECTION-C aston nes = suo the mukiptcation provost Using oOth' algo Shor te sc aumbers ore mullplied (aie Riera 26 Pape? 98, Cate . ‘Why input output interface is required? Describe in, Refer 52, Page 5-28, Unit detail Difterentiate among: robe control and handshaking asynchronous transfer modes lata Processor and 10P. Synchronous and asynchronous transmission, Charscteroriented and Bit-oriented protocols. [DStA and interrupt initiated UO techniques, Refer Q 5:19, Page 5-288, Unit ooo gE) ops i AMIN ‘Toy, =a COMPUTER Ae R, acenst all rst pease T fp bre HL Reecqn etl T | Ik stands for Single Instruction | Stream, | Matuole Data Stream Tle this. © parallel | Te { soupoter consists of X| smease ge ee® Se IES aoSP-#B(CSTT-Sem-3) Solved Paper (2016-17, Se 5 TT ‘AME Refer Q 6 10, Page SQ-18B, Unit-5, Two Marks Questions 8 Differentiate between synchronous and asynchronous transmission. Rax Refer Q 5.11, Page SQ-16B, Unit-5, Two Marks Questions, 10, What is cache memory used for ? AME Refer Q 48, Page SQ-1B, Unit-4, Two Marks Questions, SECTION-B Note; Attempt any five questions 1L Show the contents of the registers E, A, @, SC duriay procearof maltiniaton of two binary oumbers Tint Gaaltipicand) and 10101 (multiplier). The sigs ert included. oe bee max Refer Q 27, Page 2-88, Unit 2 2 In an instruction format, there are 16 bits in an ina word. BitO to 11 convey the address of the memory location For non ious regi operations. Bits 12 to 14 show the various basic m ‘operations such as ADD, AND, LDA ete. Bit 15 shows ifthe memory is accessed directly or indirectly. For such an Instruction format draw block diagram of the control unit ‘of a computer and briefly explain how an instruction will be decoded und executed, by this control unit. ‘a Refer Q 37, Page 8-7B, Unit 3 4. Write an assembly level program for the following for memory relate: ‘SUM SUM = SUM+A+B DIF = DIF-C SUM = SUM + DIF Aus Refer Q 2.31, Page 3-328, Unit-3 4 Explain microprogram sequencer for « control memory using a suitable block diagram. Hak Refer Q. 3.27, Page 3-288, Unit-3 5. Give the detailed comparison between RISC and CISC. Amz Refer Q 3.18, Page 3-17B, Unit-3 organisation & Arey eo ae Section sempt any two, , acme BUestiong # Biplain the Booths iter, control te Trrangement can wy rly €0 memory, op HelorQ 11 Page 1-25, ee te the ou > Dee of data, Writeg, op fee Q 5.20, Pee 8-208, van |, Beplain the operation ina use in design of cme p BelerQ 18, Page 1-98, Une "ody 5 Beplain 4bit incrementer wie, Refer Q. 3.92, Page 3-228, Uni, OY dag «Write « program loop using the contents of hex locations Soge so * merece RelerQ.3.35, Page 3-538, Unie TF vihe. + Demonstrate the procee of cond pu rome ing 6 Refer Q. 3.34, Page 3-398, Units, Explain how matrix multiplication a carried. computer supporting vector computation, 1 This question is out of yllabus since seion 01618, 4 Explain Flynn's classification of computers,