Scribd Logo
Upload

Welcome to Scribd!

  • KS88C3208

    Uploaded by

    Cesar Jakoby
    8 views125 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    8 views125 pages

    KS88C3208

    Uploaded by

    Cesar Jakoby

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 125
    KS88C3208/3216 ELECTRONS 8-Bit CMOS Microcontroller Product Specification OVERVIEW ‘The KS88C3208/3216 single-chip 8-bit microcontroller is fabricated using a highly advanced CMOS process. The K$88C3208/32 16 is using a modular design approach and the following peripherals are intergrated with the SAMB core to make the KS88C3208/3216 microcontroller suitable for being used in color television and other types of screen display applications. FEATURES cpu + Watchdog or oscillation + SAMB CPU core stabilization function Memory TimeriCounters + 16-Kbyte intemal program One 8-bit timericounter (TO) memory oe with three internal ¢ looks or an external clock, and three operating modes; includes. capture Input module + Two general-purpose 8:bit + 272-byte general-purpose register area Instruction Set + 79 instructions timer/counters with interval + IDLE and STOP instructions timer and PWM modes added for power-down modes. (timers A and B) Instruction Execution Time (?C-Bus Interface Controller + 750.ns (minimum) with an8- + Single master bus controller MHz CPU clock + Two pairs of bus interface Interrupts pins + 12interrupt sources with 12 A/D Converter vectors + Four analog input pins; 4-bit + Seven interrupt levels resolution + Fastinteupt processing for + —_7.68-41s conversion time (8- select levels MHz CPU clock) General VO Pulse Width Modulation Module + Four /O ports (30 pins total) + ‘14-bit PWM with 2-channel + 15 bit-programmable pins for ‘output (one open-drain and general VO cone push-pull) + Ten open-drain pins for upto *—_~&+bit PWM with 4-channel, 10-vot loads open-drain output + Five open-drain pins for up to * PWM counter and data S.voltloads Capture input pin 8-Bit Basie Timer + Frequency: 5.859 kHz to 23.437KH2 with a 6 -MHz + Three selectable intemal rane clock frequencies ‘On-Screen Display (OSD) + Video RAM: 240 x 11 bits + Character generator ROM 128 x 18 x 12 bits (128 display characters: fixed 2, variable: 126) + 240 display positions (10 rows X24 columns) + 12dot x 18-dot character resolution + 16 different character sizes + Eight character colors + Eight color for character and frame background + Halftone contro! signal output; selectable for individual characters + Vertical direction fade-infade- ‘out control + Fringe function + Synchronous polarity selector for H-syne and V-sync input Oscillator Frequency + S:MHz to 8:MHz external crystal oscillator ‘+ Maximum 8-MHz CPU clock Operating Temperature Range + 25°C to +85" Operating Voltage Range + 45V to 55V Package Type + 42:-pin SDIP a4 dune 1996 KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION BLOCK DIAGRAM Po.0-Po7 Pio-Pi7 RESET > porto pont INTo-INT3 test TT TT Xin —e| MAIN pata BU Xour= | 086 L] twers Le 1 our [ AandB f= TB sow =, PORT VO and INTERRUPT SDAO =e} FC-BUS CONTROL, SOAO =") SERIAL 10 U }— tock soni =| =| tweno [> 7 oson —of OsCour «| EG osc T syne — a Pui Vayne SAM8 CPU BLocK Ved «| ON- owe Nee | osrLAY COUNTER | — capa oso = LI LI agate — iwait [= pwno vco 8x8 ROM (2208) prepyte oe eee ape ef texB Row @2ie)| | REGISTER FLE fu fe Paw eee aoce—e| aoc eo Fe pwns = pw [oe prune SAM BUS CS pws LI LI port2 ports P20-P27 P3.0-P35, Figure 1. KS88C3208/3216 Block Diagram dune 1996 42 SAMSUNG ELECTRONICS. PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER PIN ASSIGNMENTS 2.6 /PWMO 2.7 PWM 3.0 /PWM2 3.1 /PWMS P3.2/PWM4 3.3 /PWMS P34/7A P3518 0,0 /ADCO 0.1 /ADC! 0.2 /ADC2 0.3 /ADC3 Vss Po.4 (INTO POS INTI PO.6 /INT2 PO.7 NTS Pio. Pia Piz P1.3 (OSDHT U © 10 KS88C3208 11 KS88C3216 12 jg 42-PIN SDIP (Top View) 18 16 7 18 19 © noooooooon ooo 8 P2.5/SDA1 P24 /SCLI P23 /SDA0 P22 /SCLO P21 [TOOK 20/70 PA.7/CAPA pis Yoo RESET Xour Xin Test oscour oscn P1.S/Vsyne P14 /H-sync Volank Ved Vgreen Volue Figure 2 KS88C3208/3216 Pin Assignment Diagram »—[ nose Figure 3. Pin Circuit Type 1 (RESET) Voo | IN/OUT ‘OPEN = DRAIN ouput DISABLE Vss INPUT —— ENABLE DATA 09 IN/ouT oureuT DISABLE INPUT Figure 5 Pin Circuit Type 3 (P1.0-P1.7, OSDHT, H-sync, V-sync, CAPA) SAMSUNG dune 1996 46 ELECTRONICS. PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER Vg DATA O——# ourPuT Figure 6. Pin Circult Type 4 (Vblue, Vgreen, Vred, Vblank) IN/ouT ara >> iNpuUr ++ NOTE: Circuit type 6 can withstand up to 10-vat loads. Figure 7. Pin Circuit Type 5 (P2.7, P3.0-P3.5, PWM1, PWM2-PWMS, TA, TB) IN/OUT DATA +4 Vss INPUT DIN NOTE: Circuit type 7 can withstand up to 5-volt loads. IN/ouT para —[>o—| Vss INPUT ——_—_«} INT NOISE FILTER NOTE: Circuit type 8 can withstand up to 10-volt loads. Figure 8 Pin Circuit Type 6 (P0.0-P0.3) Figure 9. Pin Circult Type 7 (P0.4-PO.7, INTO-INT3) PSANsun ELECTRONICS: 47 dune 1996 KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION ADDRESS SPACES OVERVIEW The KS8803208/3216 microcontroller supports two types of address space’ — Internal program memory (ROM) — Internal register file A 16.bit address bus and an 8-bit data bus supports program memory and data memory operations. A separate 8-bit address bus and the 8-bit data bus caryaddresses and data between the CPU and the register file. ‘The KS88C3208 has a &-Kbyte and KS88C3216 has a 16-Kbyte mask-programmable ROM. An extemal memory interface is not implemented. ‘There are 272 general-purpose data registers in the internal register file. These registers can serve as either a source or destination address, or as accumulators for data memory operations. Sixteen 8-bit registers are used for CPU and system control. For Peripheral functions, there are 29 control registers, 13 data registers. In addition, there is a 240-byte area for on-screen display (OSD) video RAM. PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. (DECIMAL) 65,535 NOT USED KS88032089216 16-KBYTE PROGRAM MEMORY AREA 8-KBYTE PROGRAM MEMORY AREA INTERRUPT VECTOR AREA Figure 10. KS88C3208/3216 Program Memory Map Instructions can be fetched, or data read, from the ROM. The KS88C3208 has a 8-Kbyte mask- programmable program memory (OH-1FFFH). KS88C3216 has a 16-Kbyte mask-programmable program memory (OH-3FFFH) ‘The reset address in the ROM is 0100H. ‘The KS88 interrupt structure can support up to 127 vectors. (The KS88C3208/3216 uses eight vectors.) The first 256 bytes of the ROM (OH-FFH) are reserved for the maximum number of vector addresses. You can allocate Unused locations as normal program memory. Be careful however, to avoid overwriting vector addresses stored in this area. dune 1996 48 SAMSUNG ELECTRONICS. PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER REGISTER ARCHITECTURE Internal Register File Register Paging Concept ‘As shown in Figure 12, when the Upper nibble of the PP register is ‘The upper 64-byte area of the The addressable area of the ; internal register file is logically 256-byte register file is logically es eis ve extended to create the set 7 and extended into four 256-byte pages floss 'S eaten oh page 0. set 2 address spaces (pages 0-8). Only page 0, page 1 "0001B', page 1 is the selected and a small section of page 2 are Gestinalion. The lower nibble of ‘The upper 32-byte area of sett is used, however, for the standard further divided into two register KS88C3208/3216 implementation. Borea suis Gage delnion eoeeeeree meee || neces tere en addressing: when the lower nibble Inadatton, the basic 256-yte—_atwaye pails to page 0 The 1s 00008: paged is the slectod register space of the register page pointer and favor ribo 2 bogie pave tis KS88C3208/3216 is expanded addressing mode restrictions ite eotee reason ese into separately addressable 256- support register addressing for w source register page, byte pages: ages 0-2. Following a reset, the page ‘These extensions into separately _Register Page Pointer (PP) Peeiay on eaten Pane! Adéressabl register e18, Barks, hp cayys architecture supports _[unper abble re always UOOOEY, ined implementation of the logical expansion of the automatically selecting page 0 as om ph physical 256-byte register file in both source and destination, To — Select bank instructions (S80 UP t0 16 separately addressable select page 1 as the source or and $81) register pages. Page addressing _—_destination register page, you is controlled by the register page must modiy the register page — Register page pointer (PP) pointer, PP, DFH). Only two pointer values accordingly. = ttc pages are implemented in the Because only page 0 and page 1 Aaressing mode restrictions KSagcaz08/6216 microcontroller: are used in the KSGBC3200/3216 Page 0 is used as general- implementation, only pointer Ce ee purpose register space and page —_vaiues 00008" and 00016" are space is thereby expanded rom + contains a 240x 11-bit areafor ged 256 bytes to 1120 bytes. The the on screen display (OSD) KS88C3208/3216 can access 579 Video ROM registers in this 1120-byte space. priorities of interrupt levels, they C>A, and"101B' would select C are organized into groups and >B > A. The functions of the other subgroups by the interrupt logic. IPR bit settings are as follows: Three interrupt groups are defined for the IPR logic (see Figure 19). — IPR.O controls the relative ‘These groups and subgroups are priority setting of IRQO and used only for IPR register priority IRQX interrupts. en — IPR.2 controls interrupt group B. — Interrupt group B has a Group A IRQO, IRQ1 GroupB —1RQ2, IRQS, Grou subgroup to provide an addtional proty relationship GroupC —IRQ6, IRQ7 between for interrupt levels 2, 3, and 4. IPRS defines the Bits 7, 4, and 4 of the IPR register possible subgroup B control the relative priority of relationships. interrupt groups A, B, and C. For — IPR.6 controls the relative example, the setting '001B' would priorities of group C interrupts. INTERRUPT PRIORITY REGISTER (IPR) FFH, Set 1, Bank 0, RW. usp} 7 6 | 5 ]|4]/3a fea 0 Jue GROUP PRIORITY: 07 04 01 UNDEFINED B>C>A ASB. B>A>C C>A>B C>B>A = A>C>8 = UNDEFINED oo o1 10 14 oo O40 10 fe LL crowr 0 = IRQO > IOI 1 = IRQt > 1ROO GROUP B 0 = IRQ2 > (IRO3, IRO4) 1 = (IRQS, IRQS) > 1ROZ ‘SUBGROUP B 0 = IRQS > ROS 104 > IRQS Not used for Kseacs20a/3216 GROUP c = IRQS > IRQT = IRQT > IROS Figure 18. Interrupt Priority Register (IPR) it vector address always begins at an even- ‘numbered ROM location from OOH-FFH. NESTING OF VECTORED INTERRUPTS. You can nest a higher priority interrupt request while a lower priority request is being serviced To do this, you must follow these steps: 1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR), 2. Load the IMR register with a new mask to enable the higher priority interrupt only. 8. Execute an El instruction to enable interrupt processing (a higher priority interrupt willbe processed if t occurs) 4. When the lower-prority interrupt service routine ends, restore the IMR to its original value by returning the previous mask from the stack (POP IMR). 5. Execute an IRET. Depending on the application, you may be able to simplify this procedure to some extent, INSTRUCTION POINTER (IP) ‘The instruction pointer (IP) is used by all KS88-series microcontrollers to control optional high-speed interrupt processing called fast interrupts. The IP Consists of register pair DAH and DBH. The IP register names are IPH (high byte, IP15-1P8) and IPL. (low byte, 1P7-IPO) FAST INTERRUPT PROCESSING ‘The feature called fast interrupt processing lets designated interrupts be completed in approximately six clock cycles instead of the usual 22 clock cycles. Bit 1 of the system mode register, SYM.1, enables fast interrupt processing while SYM.2— SYM44 are used to select a ‘specific level for fast processing Two other system registers ‘support fast interrupts: — The instruction pointer (IP) holds the starting address of the service routine (and is later used to swap the program counter values), and — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS’ (FLAGS prime). NOTE For the KS88C3208/3216 microcontroller, the service routine for any one of the seven interrupt levels (IRQO-IRO4, ROS, or IRQ7) can be designated as a fast interrupt. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1. Load the start address of the service routine into the instruction pointer. 2. Load the level number into the fast interrupt select field 3. Write a "1" to the fast interrupt ‘enable bit in the SYM register. Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing, the following events oceur: 1. The contents of the instruction pointer and the PC are ‘swapped, 2. ‘The FLAGS register values are written to the dedicated FLAGS’ register. 3. The fast interrupt status bit in the FLAGS register is set. 4. The interrupt is serviced. 5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are ‘swapped back. 6. The content of FLAGS’ (FLAGS prime) is copied automatically back into the FLAGS register. 7. The fast interrupt status bit in FLAGS is cleared automatically Programming Guidelines Remember that the only way to enable or disable a fast interrupt is to set or clear the fast interrupt enable bitin the SYM register (SYM), respectively. Executing an El or DI instruction affects only normal interrupt processing. Also, if you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends. (Please refer to the programming tip on page 4-8 for an example.) dune 1996 4-28 SAMSUNG ELECTRONICS. PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [° PROGRAMMING TIP — Programming Level IRQO as a Fast Interrupt This example shows you how to program fast interrupt processing for a select interrupt level — in this case, for the timer 0 (capture) interrupt, INTO: Lo TOCON.#52H Lo P2CONL,#02H Low IPH.#T0_INT Lo SYM,#02H el FAST_RET: TO_INT. (Fast service routine executes) Lo TOCON,#52H vP T.FAST_RET Disable TOOVF interrupt Enable TO interrupt Capture mode; trigger on rising signal edges Select fosc /256 as T0 clock source Set P2.0 to capture input mode IPH < high byte of interrupt service routine IPL < low byte of interrupt service routine Enable fast interrupt processing Select IRQO for fast service Enable interrupts IP < Address of TO_INT (again) Clear TOINT interrupt pending bit

    You might also like