Stream and Block Ciphers

Stream Ciphers and block ciphers are two categories

of ciphers used in classical cryptography.
Stream and Block Ciphers differ in how large a piece
of the message is processed in each encryption
operation.
Stream ciphers encrypt plaintext one byte or one bit
at a time.
Block ciphers encrypt plaintext in chunks. Common
block sizes are 64 and 128 bits.
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 Stream Cipher
Stream Cipher – encryption of bits
Often pseudorandom generators
Simple and fast
Not very secure
RC4, A5/1
Inspired by the one time pad (OTP)
A one-time pad uses a keystream of
completely random digits. The keystream is
combined with the plaintext digits one at a time
to form the cipher text.
http://en.wikipedia.org/wiki/Stream_cipher
2
 Block Ciphers
Block Cipher is a symmetric key cipher operating on
fixed-length groups of bits, called blocks, with an
unvarying transformation. A block cipher encryption
algorithm might take (for example) a 128-bit block
of plaintext as input, and output a corresponding
128-bit block of cipher text. The exact
transformation is controlled using a second input —
the secret key.
Short explanation
DES, 3DES, AES, IDEA,TEA,XTEA
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 Symmetric Key Crypto
Stream cipher  based on one-time pad
Except that key is relatively short
Key is stretched into a long keystream
Keystream is used just like a one-time pad
Block cipher  based on codebook concept
Block cipher key determines a codebook
Each key yields a different codebook
Employs both “confusion” and “diffusion”

Part 1 
Dti = date and time
 update
extend key
permutation
initialize shuffle
permutation permutation
Probability of recovery of plaintext from 224 ciphertexts vs. byte position
Entropy Source
- shared by all cores Detect when
- RS-NOR latch settled, and
becomes metastable store output
when input
De-asserted
- Output settles to 0 or 1, RS-NOR
depending on thermal latch
Noise
- Feedback helps reach
Metastable state Negative
- Output detects when feedback
settled, stores result,
reasserts input Entropy Source
http://electronicdesign.com/learning-resources/understanding-intels-ivy-bridge-random-number-generator
 DRNG output fed to all processors
hardware instruction-level access
ps://software.intel.com/en-us/articles/intel-digital-random-number-generator-drng-software-implementation-guide
- Output is biased
due to feedback
- 800 MHz clock
Conditioner
outputs 256 bits
every few
microseconds
Expand rate using
NIST SP800-90
PRNG to rate of
800 MBps
 Built-In
Self Test

Health tests are basic, ad hoc, but detect RNG failure

Output zero with carry zero on failure (can't read a 0)