LATCH UP

ABSTRACT: Latch-Up is a condition in which a low impedance path gets

formed between VDD and Ground, and there is a direct current flow between
VDD and Ground which might result in a complete failure of the chip.

INTRODUCTION:

Now let us discuss the Latchup situation with a basic example of an inverter
circuit.
● While manufacturing a CMOS device, we can see a lot of p-n junction
formations.
● These p-n junctions might result in a lot of parasitic elements like
diodes, transistors.
● Parasitic means which is unwanted, at the same time unavoidable.

As you can see these pnp and npn transistors are parasitic transistors which
are getting formed while manufacturing the CMOS inverter.

-Sonika M
 LATCH UP
● If we observe carefully, if the transistors formed by the parasitics are
ON, there is a direct path for current to flow from Vdd to gnd.

● This would cause the short circuit.

● But while manufacturing the device, it is made sure that these p-n
junctions are reverse biased.
● So, that all the parasitic elements are OFF and they do not hamper the
normal functioning of the circuit.
● But still there are many ways in which these parasitic elements can be
turned on.

We discuss a few ways in which these parasitic transistors can be triggered.

➢ Let us see what happens if i/p, o/p > VDD

➔ For a pnp transistor, the p region is more positive than the n region.
➔ Therefore, the base-emitter junction of the pnp transistor is forward
biased.

➔ Therefore, this pnp transistor turns ON.

● Now if you see the collector of this pnp transistor is connected to
the base of the npn transistor.

-Sonika M
 LATCH UP

➔ Therefore the collector current of this pnp transistor directly flows into
the base of the npn transistor hence turning it ON.
➔ Now, both the transistors are turned ON, because i/p,o/p>VDD
➔ So now there is direct current flow from VDD to GND.

➢ Similarly, if i/p or o/p < GND,

➔ If you see base-emitter junction of the npn transistor,

you will see that the n-region is more negative than the p-region turning this
base-emitter junction of npn transistor forward bias, hence this turns the npn
transistor ON.
➔ Now again the collector of this npn transistor is connected to the base
of this pnp transistor,

➔ Therefore, the collector current flows into the base terminal of the pnp
transistor, turning this ON as well.
➔ And current can flow from VDD to GND, causing a short circuit.

-Sonika M
 LATCH UP
Why is this phenomenon called Latch-Up?

➔ If you see, the collector of the npn transistor is connected to the base of
the pnp transistor.
➔ Collector of the pnp transistor is connected to the base of the npn
transistor.
➔ Hence these 2 transistors are forming a circle. These are feeding each
other. So, current will see a direct path from VDD to Ground.

➔ Even if you remove the disturbance at the input or output pin, because
it has become self-sustaining.
➔ Basically it has latched-up. That’s why the term Latch-Up.
➔ Simply, latch-up is nothing but the formation of SCR- Silicon
Controlled Rectifier.

-Sonika M
 LATCH UP
● If you closely see, our transistors are forming the same structure as
SCR.
● This Anode is nothing but VDD, Cathode is nothing but GND.
● If there is voltage applied at this GATE terminal, this voltage should be
enough to turn the Base-Emitter junction of pnp forward bias.
● Hence the pnp transistor turns ON.
● Its collector current will flow through the base of the npn transistor,
turning it ON as well.
● Hence there is a direct current flow from anode to cathode.
● So now if you stop the supply at GATE terminal, this has become
self-sustaining.
● Basically this has become latched-up.
● So, current will keep flowing from anode to cathode.

LITERATURE:
Problem Statement: Basically CMOS is where we have both pmos and
nmos. So, in such structures where pmos and nmos sit closer together, close
to each other, what happens is base and emitter get coupled unintentionally
forming the structure of SCR/Thyristor.

-Sonika M
 LATCH UP
Cause of this issue/problem: In such structures of CMOS, where pmos and
nmos sit closer together, close to each other, what happens is-
● You can see p-substrate in which n-well is there.
● In n-well, pmosfet is there.
● Then in p-substrate, nmos is formed.

● So, in n-well, because of parasitics, if you see there is pnp type of BJT
is formed and in p-substrate, npn type of BJT is formed.
● These are connected in such a way that they are coupled with each
other.
● Base and Emitter are coupled.
● None of these connections are intentional.
● But, due to parasitics, they are formed that way.
So, a simpler diagram would be- 2 BJTs connected back to back. This is
what we call SCR/Thyristor.

❖ Formation of this SCR structure is nothing but “Latch-Up”.

-Sonika M
 LATCH UP
Effect of this Latch-Up:
What is the problem with this?
The problem with this one is- There are 2 things.
1. Current
2. Resistor
● 1st thing, current is like noise. If this doesn’t come up, no latch-up
situation.
● 2nd thing is, this noise is not in our control. If Rnwell is not high enough,
the product of ixRnwell won’t be high enough to turn ON BJTs.

OVERVIEW:

● Usually there is no current in this circuit .

● But there could be a small unwanted noise from anywhere (because of
coupling capacitor or friction from elsewhere) that translates itself into
some current. If it gets induced due to whatever reason, this current ‘i’
gets multiplied with Rnwell . So you get iRnwell (some voltage).
● If this voltage is higher than Vte of BJT1(Q1), then BJT1(Q1) turns ON,
and there is a collector current that flows through Rsub and gets
multiplied by Rsub.
● If that product of collector current and Rsub (i.e voltage drop) is higher
than Vte of BJT2(Q2), then BJT2(Q2) turns ON, and there is a current
that flowing through Rnwell and gets multiplied by Rnwell resulting in
more Vte.
● Thereby, magnitude of current keeps increasing, Vte keeps increasing.

Hence, after sometime, what happens is- “ ” path becomes a

non-resistive path, more conductive path.

-Sonika M
 LATCH UP
➔ Earlier it was a very resistive path. Now it forms a conductive path.
➔ There would be a direct conducting path between Vdd and GND.
➔ This results in a large amount of current that would flow, which we call
it as “Leakage”.
➔ In extreme cases, it can break down the circuit because, huge amount of
current is going to flow through this unintentionally uninterrupted
(without anything that is stopping it).
➔ So, in no amount of time, huge heat gets generated and results in opens
and circuits getting burnt.

CONCLUSION:
“Latchup” is “a situation where a resistive path is converted into a conductive
path, leading to huge amounts of leakage, thereby heat, thereby circuit
breakage”.

-Sonika M