ms IEEE TRANSACTIONS ON CIRCUTTS AND S¥STEM I EXPRESS BRIEFS, VOL. 70, NO. 6, JUNE Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling Mina Raouf and Somayeh Timarchi? Abstract—The new generation of electronic circuits based on spintronic technology have drawn the attention of researchers, in recent years due to thelr remarkable features, including low= power consumption, non-volatility, and compatibility with the ‘CMOS technology. However, these circults usually rely on the pre= ‘charge sense amplifier (PCSA), to read the state of the magnetic ‘tunnel junctions (MTJ). The major disadvantage of the PCSAS is the high sensitivity of these circuits to inputs scheduling, It means that if the inputs are not applied to the circuit exactly in the ‘specified time, the generated output will not be Valid. This issue ‘causes a serious problem in the ripple carry adders due to their ‘carry propagation. In this brief, a novel structure is proposed ‘which is based on removing MTS from carry propagation path by ‘adding a post-processing unit. The proposed post-processing unit ‘makes the spintronie adders invulnerable to inputs scheduling. ‘The proposed adder in this brief occupies at least 29% less area. also offers 40% lower carry propagation delay, and 37% lower owerdelay product compared to the efficent state of the art Index Terms—Spintronic, magnetic tunnel junction, low-power, fullradder, ripple carry adder, cascadable adders. I, INTRODUCTION ETAL-OXIDE semiconductor (MOS) circuits suffer from high static power consumption because of the ‘exponential increase in the leakage currents of transistors (1) (21, Gl, (41, (5). (6), [7]. To overcome this problem, spin- tronic devices, such as magnetic tunnel junction (MTD), have CoFeO (10) separated by a thin insulator layer, placed to 2 hheavy metal strip [10]. Depending on the relative magnetic orientation of the ferromagnetic layers, an MTJ is in either parallel (P) or anti-parallel (AP) state [13], [14]. An MTJ in the parallel state exhibits lower electrical resistance than the MTJ in the anti-parallel state [10], (15] Tn recent years, the hybrid MTJ/CMOS technology has been exploited in various sequential circuits including flip- flops [11] and combinational circuits such as full-adders (6), [71 13}, [16]. Among the mentioned circuits, full-adders are fundamental units because addition is the basic operation in the computation units [3], [4]. Also, it is employed in some types of multipliers [17]. Despite the great properties, all the previous hybrid MTJ/CMOS full-adders suffer from high power consumption and high delay in carry propagation (6), [7] The circuits used for reading the MTJ status are usually based on pre-charge sense amplifier (PCSA). One of the draw backs of the PCSAvts their sensitivity toward inputs timing. If the inputs are not applied to the circuit when clock is low (Pr charge phase), the result may not be valid in output (18). This disadvantage severely limits the use of spintronic adders in the implementation of ripple carry adders due to the prop: of the carry digit. In nipple carry adder, the carry biti ated in each stage, and then it is transferred to the next sta Due to this issue in spintronic adders based on PCSA, the camry propagation in other stages may produce invalid output In tis brief, a non-volatile full-adder with a post process unit is designed and simulated to gencrate carry bit that is not ‘vulnerable to input scheduling. So, the proposed method is di ‘and implementation of hybrid MTJ/CMOS circuits causes distance reduction between memories and arithmeticMogic units; thereby decreasing the delay and power consumption for data transfer {10}, [11], (12). MTJ is the intrinsic element in the hybrid MTJ/CMOS circuits. An MTJ consists of two ferromagnetic layers (c.g., Manuscript received 15 November 2022; revised 16 December 2022 accep 12 Iansary 2023, Das of publication 18 January 202; date of eu. foot version & June 2023, Ths bef was recommended by Associate EAitor €.W. Sham. (Corresponding author: Somayeh Tmarchl) “The authors aze wth the Faculty of Electrica Engineering of Electonics, Shahid Behesht University, Tehran 1983968811, Iran (e-mail: Ssimarchi @sbu a.) Color verions of one or more figures in this anicle ae available at ‘nplib org/101109/TCSTL.2023 3237835, ‘igi Objet Identifier 10.1109/TCSIL.2023 3237885 ‘+ Removing MTJ cells from carry propagation path by Proposing a postprocessing block te make the full ele insensitive to the inputs scheduling Reduction of delay and power consumption compared to the state of the arts non-volatile full-aiders duo to removal of unnecessary MTJs and also using fixed MTs, «+ Ability to implement cascade adde in-memory computing The rest of this brief is organized as follows. Section reviews the spintranic. basics as well as existing non-vol. sl 3 hybrid MTJ/CMOS full-adders. ‘The ae hybrid MTICMOS Tl adder is explmed in gon OS® 5 for realization of me BE. Pea! ws it perma, tt repbcaotediston "us IEEE persion 1870 © 2 Te jeelece ty pacaanunpivdernl fe we wlan ‘Aumorzed cans use lied to. A. Engineering Colage.Downioaced on Fabrar 20,2024 a 11.0880 UTC Fem IEEE Xoo. i a[RAOUF AND TIMARCHI: NON-VOLATILE AND HIGH-PERFORMANCE CASCADA SPINTRONIC FULL-ADDER m1 3 Fig. 1. Structure ofa magnetic tunnel junction (10) Section TV presents the simulation results and discusses the ‘comparison of the proposed non-volatile hybrid MTW/CMOS full-adder with the existing designs. Finally, Section V con: cludes this brief TL RELATED WORK. A. Spintronic Technology TJ is the basic clement of spintronic memory and logic circuits. As shown in Fig. 1, an MTS is comprised of a thin oxide barrier (e.g., MgO [10]) sandwiched by two ferromag- netic (FM) layers (¢.g., CoFeB [10]). ‘Based on the relative orientation of the FM layers, an MTJ hhave two possible states, parallel and anti-parallel 19}. In par- allel mode, MTJ shows a lower resistance (Rp) than that inthe anti-parallel mode with the resistance of Rap [19]. The diffe tence between Rp and Rap is called tunnel magnetoresistance (TMR) ratio that is given by the equation (1). aw B. Review of the Previous Hybrid MTJ/CMOS Full-Adders In [6], an MTJ-based spintronic full-adder has been “The full-adder presented in [6] employs PCSA for reading the status of the MTJs and other inputs (.c., those inputs not stored in the MTJs) are directly applied to the PCSA Circuit, making the circuits sensitive to the timing of the inputs, ‘Also, as mentioned earlier, the circuit presented in (6) stored only one of the inputs in the MTJs, not enabling the circuit to be switched off to reduce the static power consumption since the circuit is not completely non-volatile. in [24], 2 completely non-volatile full-adder. has been designed and simulated. In the proposed design in [24] all inputs are stored in the MTJs causing the full-dder to be completely non-volatile, As a result, wheneves the circuit not ‘of any external com- a circuit area overhead. i Tn (17), similarly wo (241, the PCSA is directly used for reading the status of the MTJs and calculating the carry, cre- ‘ating a circuit sensitive to the timing of the inputs. In the proposed design in (17] by sharing MTJs the tolal number of the MTJs is reduced resulted in & lower power consump tion and area overhead, Anyhow, despite the aforementioned ‘outcomes, this circuit has two disadvantages: First, the use of ‘Authorized eansed use itd to: 8. A. Eng PCSA for reading the status of the MTJs, which led to the cir cuits sensitivity tothe timing of the inputs. Second, the use of the MTs for storing the carry, which results in the increased power consumption and circuit area overhead. Th {16}, the voltage division method was used for reading the status of the MTJs. This method requires fewer MTIs, d and a resulting in a reduction in the circuit area overhe considerable decrease in the power consumption. However, it ‘causes a noticeable increase in the static power consumption Of the circuit, which is not acceptable in the battery-based ystems, Moreover, the use of the voltage division method for reading the status of the MTJs causes a permanent flow through the MTJs which in turn bring several problem as road disturbance [8] sty (7) jforthe first time, the carry, instead of being stored in the MTs, was applied to the circuit through CMOS transistors. ‘As mentioned in [7], the carry is an intermediate signal that doesn't need to be stored in the non-volatile way. Since the cary is an intermediate signal and does not need to be stored the MTJs, by using the method proposed in (7] the is still fully non-volatile. The only disadvantage of the proposed in [7] is the use of PCSA for reading the the MTJs and hence the sensitivity of the circuit « of the inputs III. PRoPOsED FULL-ADDER ‘As mentioned earlier, one of the disadvanta based circuits is their sensitivity to the input’s scheduling If the inputs are not applied to the circuit simul and. at the zero level of the clock signal (pre-charge phase! the produced result at the output may not be valid. On the ‘other band, carry is generated by a full-adder in the Ripple (Carry Adder structure, and then transferred to the next full- f Considering this issue, in the PCSA-based spintronic “invalid output maybe generated. The circuit shown in Fig. 2 is proposed to address this problem. In this circui the main input operands (A and B) are initially proce ‘Then, the intermediate signals (S and C) are generated ba: ‘on the inputs. By utilizing these signals and the carry of th previous level (G), the sum and the output carry (Cox) a generated and transferred to the next level. Sin only enters the post-processing unit in the propos: the propagation delay of the carry does not affect the circuit performance, The proposed circuit also uses $ recon urable MTI cells and 2 fixed MTJ, which has 4 reconfigurable ‘MT cells less than the best available circuit presented in [7]. Moreover, given that the majority of the power is consumed to configure the MTJs, the proposed circuit consumes less power than the previous circuits (7), ‘Table I shows the truth table of the various part of the sed circuit, According to Table I, the logical functions ff the Cot and Sum are given by the equations (2) and (3): Cou = Ci SC @ Sum = Cr S+E 6-8 @ where C and $ are given by equations (4) and (5). CaAB @ S=Aos o the Based on the equations (2) and (3), the structure of post-processing block circuit will be as shown in Fig. 3 ineaing Calon Downloaded on Fobrury 20,2084 a 1105 80 UTC rom EEE Xplor, Restictons applyTREE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 6, JUNE 2023 According to the proposed structure, this circuit can be used to implement a Ripple Carry Adder with any timing of input operands without the need (o set special time scheduling for input operands. IV, SIMULATION RESULT AND ANALYSIS The proposed circuit was simulated by the HSpice soft- ware using the 32am CMOS transistors model and the MTJ ‘model presented in [20]. The specifications of the MTJ are provided in Table IT. The supply voltage is considered to be 1Y in all simulations. The existing circuits had been sim- ulated with different technologies, i.c., the MFAs presented in (6}, [17}, 18}, (24), [25], and (7), [16] had been simulated ‘with CMOS 28nm, CMOS 40nm, and CMOS 32nm, respec- tively. However, to have a fair comparison, all existing circuits were optimized to have the best latency, and simulated using ical input patterns under the same conditions using 32nm technology. functional simulation of the proposed including outputs and intermediate at inputs, The C; input is applied to the ond delay in the “Evaluation” phase esistance of the proposed circuit to the inputs ‘As shown in Fig. 4, not only does the proposed form well in these conditions, but it also changes the outputs accurately even when the C; input changes ia the evaluation phase, B. Comparison With Previous Work ‘Table II represents the simulation results of the proposed fully nonole MEA and pavios Works prone a 7), (16), (17), (19), (24), (25), AAs shown in Table TI, the proposed full-adder is nom volatile, Thus, the proposed full-adder can be turned oft when not needed which results in reducing the static power con sumption, Moreover, the proposed tull-adder has the Least sum delay, carry propagation delay, powerlelay product, and static power consumption compared with the other non-volatile full-adders, ‘The equivalent number of unit-sized transistors (UST) is ‘considered for area comparison, This metric is widely used ‘Authorized lensed use limited fo S. A. Enginoaring College. Downloaded on February 20,2024 at 11:06:50 UTC trom IEEE Xplore, Restctions applyee retin: SIMULATION ResuLts oF HYBRID MTJ/CMOS FULL-ADDERs WiTH 32-8 CMOS TECHNOLOGY a7] [rr oT pay [4 25 f16)_] (71 Propose 0 0 0 o | 0 16, 4 8 1 44 9s | ss 50 880, s31_| ses s00 5.0 21 [49 [49 200% | 120% |_120% | 120% 1978 773_|_1572_[196.1 1669 446 | 1523 [1632 4723 | 3623 |_402.1_ [135.5 13.7 216 | 167_[ 183 Bisa] 2848 | 4876 [2a ‘WateW) | 408.0 [3403 [3848 [117.0 PDP) 279 | 835 | 266 Fully Non-volatil Yes |" No_ | No Ls Yes | No_ | Yes ae No | No | No TABLE IV RESULT OF MONTE-CARLO SIMULATIONS ‘Wirt 32-NM CMOS TecHNoLocy Fig. 4 Transient simulation ofthe proposed MFA considering all possible combinations of inputs A, B, and Ci. to compare the area of the designs with different technolo- gies [11]. As shown in this table, the proposed circuit occupies 29% to 62% less area than highest- and lowest-area MFA due to using fixed MTJ and fewer reconfigurable MIs and also switch- Parameien, Min [Avg | Mie MiVewitching time(s) | 1.6 [1.8 [21 Sum (ps) | 389 | 65.1 | 1023 Delay |“ carry(o8) [63 | 7.1_| 135 ‘Average (OW) [76.1 | 99.8 | 168.5 power -Pyaumic ow) [31 [38 | 76 Stic @W) | 234.1 | 9712 | 3210 Wate (uW) [71.2 [95.7 [161.1 circuits, and consume 45% to 88% lower dynamic power due to employing fixed MTJ and less reconfigurable MTJ, as well as the absence of an active path between the VDD and the ‘ground, similar to the circuit proposed in [16]. The proposed Circuit in this brief also has 37% to 91% lower power delay product (PDP). As Table II shows, the MTJ-based full-adder consume ‘more average power than the CMOS-based full-adder due to the write operation of MTJs [11]. However, in applications where the inputs have low switching activity or the system is idle for a long time, static power is dominant and the superiority of MTJ-based circuits is evident (7), (131, (171 ce ea Soe ets 4 C. Impact of Fabrication Process Variation on the Performance of the Proposed Circuit ‘of spintronic circuits is their vul eS5 variation. Monte-Carlo tioned in [16], [19]. Then, 1000 simulations were performed. The results of these simulations are given in Table IV. As Table IV s! influence the functionality of the proposed circuit, but it causes slight changes in the power consumption and PDP of the [proposed circuit, This occurs duc to the fact that slight changes, {in circuit parameters, especially the thickness of the MT insu ation layer, led to a significant change in the MTJ resistance, Qws, fabrication process variation does notTABLE V eRrORMANCH OF THE B,16, AND 32-Brt RIPPLE CARRY ADDER TweLEMENTED UsING PROPOSED FULL-ADDER WITH 32-NM CMOS TecHINOLOGY Bi 165 328 Implementation _|CM03| Proposed [CMOS|Proposed|CMOS| Propose Average (awy| 783 | 15.6 [1566 | 16262 [3045 | 3272.5 Dynamic (uW)| 73.8.| 29.6 [147.6 ami 73. Power "Suic(aw) [45 {21 | 9.0 264 |_87 Waites) | =| 73.6 [= =| 30654 of cmos | 224 | 704 | aa8 396-2816, ‘Area ust [1326 | 2664 [ i938 3774 | 10656; Maximom Delay GS) [931.2] 666 [1641.6 fa3sa]_293.9 ppp @)__ [72.9 255: 943.4 | 9299 | "Non-vol ‘No [Yes LN yes and thereby, changes the current passing through the MTJ and the power consumption of the circuit. D. n-Bit Ripple Carry Adder Implementation ‘Table V shows the result ot block, the and as a result, it has 5% to Y. ConcLusion Spintronic circuits have drawn the attention of many researchers in recent years, Full-adders are one of these cir- ‘cuits. A cascaded spintronic full-adder was proposed in this brief. The circuit proposed in this brief uses a post-processing, tunit to generate the final output, and therefore, itis not sen- sitive to the scheduling of the inputs, and can be utilized to implement the Ripple Carry Adders with a different number of inputs, The simulation results reveals that the proposed circuit occupies at least 29% le lower carry propaga- REFERENCES [I N.S. Kim eal, ‘Leakage current’ Moore's law meets static * Computer, vol. 36, 0.12, pp. 68-75, Dee. 2003, oi 10,1109/me 2003. 1250885. [2] A Amirany, M, H, Mosiyer, and K. Jafai, “Bioinspired nomotatile ‘nd low-cottspa-based bit per cell memory” presented at the 25th It. Comput. Conf. Comput. $oc., Tehran, Iran, 202, pp 1-7 (9) He Niser and 5, Timarchi, "Low-power and fast full adder by tiploring new XOR and XNOR gues" IEEE Trans. Very Large Scale Inegr (VISI) St, vo. 26, 00.8, pp. 1481-1493, Aug, 2018, oi: 10.1109 2018.2820999. [4] S. Timarchi,P. Ghayour, and A. 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