FOR MTE EXAMINATION (COMPUTER ORGANIZATION)

Unit 1: Memory
Mainly Cache Numerical Problems will be asked.
References
https://www.gatevidyalay.com/direct-mapping-cache-practice-problems/
https://www.gatevidyalay.com/fully-associative-cache-practice-problems/
https://www.gatevidyalay.com/set-associative-mapping-practice-problems/
T1: Problems 5.9 to 5.14
R1: Solved Example 8.3 and 8.4
Related sections from Hamacher 5th Ed. (T1): 5.1, 5.4, 5.5.1, 5.5.2, 5.5.3
Related sections from Hamacher 6th Ed. (R1): 8.7.1 and 8.7.2
Note: Assignment 1 and Quiz 1 will be given from above unit.

Unit 2: Processor Datapath and Control

References

1. T1: Chapter 7 Basic Processing Unit: Upto section 7.5.1

2. Lecture 17, 18, 19 and 20 in Week 4 from the below link

https://nptel.ac.in/courses/106105163

Note: Assignment 2 will be given from above unit.

Unit 3: Pipelining
References

1. T1: Chapter 8 Pipelining: 8.1, 8.2, 8.3 excluding dynamic branch prediction, 8.4 and 8.6.

2. Problems from https://www.gatevidyalay.com/pipelining-practice-problems/

3. Students may refer following lectures from nptel link Week 11.

Lecture 53 -- Slide 1-6

Lecture 55 and 56

Lecture 57 --- Slide 34-37

Here, above Point 3 is not mandatory, but it can be used as a supplement. More specifically, you
should be able to answer following questions after preparation.

a. Various Pipelining Hazards by giving examples.

b. Solution for various hazards with examples. Delayed Load solution for data hazard is not there in
textbook, it is discussed in nptel lecture 56.

c. Influence on instruction sets.

d. Different type of pipelining numerical taken by instructors.

Note: Quiz 2 will be given from above unit.

T1. Carl Hamacher, Computer Organization, McGraw Hill (5e).

R1. Carl Hamacher, Computer Organization and Embedded Systems, McGraw Hill (6e)