Solutions , VLSI-11, Spring -2020 Final Exam. EE382M.8: VLSHIl Final Exam May 13, 2020 Qualitative Questions (2 points each) (20 Points} Problem 1: Answer the following questions using these SYMbOls ONLY: @ Value goes up > Value stays the same W Value goes down 4. If Fin thickness in a double gate MOSFET increase, the subthreshold slope will 2. With technology scaling, the DRAM capacitor value 3. SRAM bitcell access transistor with lower Vt, the read stability will 4. For supply sealing below Minimum Energy point, total power will 5. With Compute-in-Memory, the computational bandwidth 6. With Vcc scaling, the switching threshold of a dynamic logic gate will 7. With SRAM wordline underdrive (WLUD) technique, the dummy-read stability will 8. With staggered power gate activations, the \ergy required to switch the power gates 9. With technology scaling, the sensitivity of body biasing to Vt modulation Keb bE EEE 10. With technology scaling, the effectiveness of transistor stacking for leakage reductionEE382M.8: VLSI Final Exam May 13, 2020 Problem 2: Clocking 20 Points 40 x oy ee | 20 SE tops aotsope ey oT m, i Flip op A |S] Teomb_AB, Ops oer a ea 20! ie Az Fp Fope | Teob_ 8c, 6ops = ik one aoe [ Wat | aot ios Flip Fp ¢ be Lae ST All flops, Teetup= 40ps, Teq= 20p8 Thold= 10pe ‘The buffer delays and interconnect delays for a clock tree are as shown in the above figure. What is the ‘Maximum frequency (Fmax) for the correct operation? Show all your calculations. The combinational logic delays and the flip flop timing parameters (setup, hold, Tcq) are mentioned above. Path @ Cita > CLkg through Teomb_AB Path @)CLKR> CLke through Tcomb-Be Patn@) Tskew_ng = Static time difference between Clg & CLKA 4 a Rest of the clock path common berwech = 26- = e-30 = —rops | ist of Clx, won't contribuke fo skew Tyitteap = lops Yor Max delay : Tetk_ngt Tskew_ng 7% Teqt Tcomd ag + Tsut 2° Titer “. Tetx-ag lops % 204 Bo+4o420 ps Teuk-AB 7 1 TOPs Paty @: Tskew-Bc = Static Hme difference between Clk & Clk (30430) - Clo+20) [Fest of the path commen | = 3ops. Tyitter-Bc =lops Max. delay i Ww Teax.ac + Trew Be 7/ Tegt Scomp. gor Tsu +2- Tilted fe Tetk-pe% 20+ 60 +40+ 20-30 Tere-we % Nops Take Mox (Trav an Taw a Mavl170 1o\ ne.FE382M.8: VLSI Final Exam ‘May 13, 2020 Problem 3: SRAM 20 Points Log ld, 1 fin device I=K (Vgs-vt) aan vos=1V 100nA\ Ignore column mux resistance Sense Amp offset= 100m ‘The High-density (HD) SRAM bitcell above has all single fin transistors. The timing diagram for clock and ‘wordline signal is shown above. For transistor parameters, use the Logtld)-Vg graph data and I-V relationship mentioned above. What is the maximum frequency for the successful operation (at 1V) of the above SRAM column having 101 bitcells/column? Write your approach/assumptions and show all the calculations (15 points) For covrect SRAM opevalion: Avg, 77 5A Offset 7, 1oomV Capacitox discharge > T= egy. => dt Car AVBL E Teffectve. Teffective = Tread -C Treae Worst Case leakage due to unselected cells on the same column, Btoring opposite dal Cy-1) Teak = 100 % loo nA = IOLA Tread = Taccess -transistot @ Vgs= 0-8¥ Liv- 0-2 ogi], Read current is sek by access hransistoy as it is tn Sakuation YegionEE382M.8: VLSHI Final Exam May 13, 2020 Te KCVgs-vt) «k= 1o0-uA W=VE Pssuming Sub-loveshold slope oF Gomi/dec, Zorders of Current change ENL2GOXS 2 O1BV + k= 100A U-0- ls “Read Current @\gs=0 4 = JOO MA .C0-g- 0-19) Vv O+$2V = 15+6)418 “. Tefiective = 75-61 -10 = ¢s-ciun ce dk = loonie! oy = Joo x \g8 . SS-Gixjor@ Gs-ei% = IB2xI0 sec dt =o-S.Teycle Las Pev ming waveform) “, Teycle = 3-04 x10 see Fmay ») Mention at least one approach to improve the maximum frequency without changing the bitcell or sense amplifier design. (5 points) » 2) Reduee number of bitcells on the column, veducey Car Word line boost to increase vead curren): need to be 4 careful not lo cause 4 ead failure, %) Cross coupled bitline keepers to minimize bitline \eakage due te ungelecied cells.£E382M.8: VLSH-II Final Exam May 13, 2020 Problem 4; Interconnect coupling 20 Points In the following circuit, interconnect coupling can occur; if it does, assume that the “attacker” can cause a VDD/2 “glitch” on the “victim”. Assume unit delays for all inverters, pass gates, jam structures (latches) and interconnect for the following circuit. Also assume a unit delay for both setup time and hold time for this simple edge-triggered FLIP-FLOP. Finally, assume transistor t's to be VDD/4 and all inverters and jam structures trip points to be VDD/2. (15 points) 8 aK = m2 ° so or cu CLK [07 A tor B mM eo nfo Flipped n2 ofa Frippedl no ATT ee our LLL Re + lippect) | b. Mention one design modification (except shielding) to fix the above issue (5 points) —> Move the dotted invevtevs to the nodes as shown, Maxing sure Flip-Flop inpuk is net driven by a pass -gote.FE382M.8: VLSIll Final Exam May 13, 2020 Problem 5: Short questions 20 Points a) Mention at least two ways to mitigate the charge sharing noise in dynamic logic. ') Keeper addition 2) Secondary precharge 3) add inpw dependent intermediate, node pull up device +b) Mention at least two design approaches to achieve Near threshold Voltage (NTV) operation of CMOS circuits. \) Lew Ve transistors 2) Moid hign stacked gates 3) Avoid minimum sized standard cells 4) Avoid pass bansisley logic S) Special bitcells tolerant to low voltage operation c) Mention at least two ways to implement shielding for mitigating the interconnect coupling noise \) Physical 2) Temporal 2) Logical 4d) Mention at least two techniques to perform Compute-in-Memory (CIM) operations in RAMS. Y) Polse width modwhred word lines 2) Palse amplittde modulated word lines , 3) y— =a —)— ~~ bothiney 4) Tum cells.