ARM Cortex M4 Timers

Dr. K. Vasanthamani
Timers

• Programmable timers can be used to count or time external

events that drive the Timer input pins.
• Contains six 16/32-bit GPTM blocks and six 32/64-bit Wide
GPTM blocks.
• Can be configured to operate independently as timers or event
counters, or concatenated to operate as one 32-bit timer or one
32-bit Real-Time Clock (RTC).
• Timers can also be used to trigger μDMA transfers.
Timers
• 16/32-bit operating modes:
• 16- or 32-bit programmable one-shot timer
• 16- or 32-bit programmable periodic timer
• 16-bit general-purpose timer with an 8-bit prescaler
• 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz
clock as the input
• 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
• 16-bit PWM mode with an 8-bit prescaler and software-programmable
output inversion of the PWM signal
Timers
• 32/64-bit operating modes:
• 32- or 64-bit programmable one-shot timer
• 32- or 64-bit programmable periodic timer
• 32-bit general-purpose timer with a 16-bit prescaler
• 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz
clock as the input
• 32-bit input-edge count- or time-capture modes with a16-bit prescaler
• 32-bit PWM mode with a 16-bit prescaler and software-programmable
output inversion of the
• PWM signal
Timers
• Count up or down
• Twelve 16/32-bit Capture Compare PWM pins (CCP)
• Twelve 32/64-bit Capture Compare PWM pins (CCP)
• Timer synchronization allows selected timers to start counting
on the same clock cycle
• ADC event trigger
• User-enabled stalling when the microcontroller asserts CPU
Halt flag during debug (excluding RTC mode)
• Ability to determine the elapsed
Timers
• Count up or down
• Twelve 16/32-bit Capture Compare PWM pins (CCP)
• Twelve 32/64-bit Capture Compare PWM pins (CCP)
• Timer synchronization allows selected timers to start counting
on the same clock cycle
• ADC event trigger
• User-enabled stalling when the microcontroller asserts CPU
Halt flag during debug (excluding RTC mode)
• Ability to determine the elapsed between the assertion of the
timer interrupt and entry into the interrupt service routine
GPTM Module Block Diagram
Timers – Operating Modes
1. One-Shot Timer Mode.
2. Periodic Timer Mode.
3. Periodic Snapshot Timer Mode.
4. Wait-for-Trigger Mode.
5. Real-Time Clock Timer Mode.
6. Input Edge-Count Mode.
7. Input Edge-Time Mode.
8. PWM Mode.
9. DMA Mode.
10. Synchronizing GP Timer Blocks.
11. Concatenated Modes.
One-Shot mode
One-Shot mode
(1) the start values in the GPTMTAILR and GPTMTAPR registers
are loaded into the Timer A and its Prescaler.
(2) Then the timer begins the count-down by first decrementing 1
from the Prescaler.
(3) Until the Prescaler is 0
(4) the GPTMTAPR is reloaded to the Prescaler
(5) the free-running counter begins its count-down operation.
(6) The current value of the free-running counter can be obtained
from the GPTMTAV register
One-Shot mode
(7) this value is compared with 0.
(8) If it is equals to 0, re-do decrementing 1 from the Prescaler
and then free-running counter until the free-running counter gets
0.
(9) For a periodic timer, the start values are reloaded from the
GPTMTAILR and the GPTMTAPR registers into the timer and
continue for the next cycle.
(10) For one-shot mode, the TAEN bit in the GPTMCTL register is
reset to 0 to stop the timer’s operation.
One-Shot mode
(7) this value is compared with 0.
(8) If it is equals to 0, re-do decrementing 1 from the Prescaler
and then free-running counter until the free-running counter gets
0.
(9) For a periodic timer, the start values are reloaded from the
GPTMTAILR and the GPTMTAPR registers into the timer and
continue for the next cycle.
(10) For one-shot mode, the TAEN bit in the GPTMCTL register is
reset to 0 to stop the timer’s operation.
Periodic mode
Periodic mode
(1) the time-up values are loaded into the GPTMTAILR and the
optional GPTMTAPR registers
(2) the free-running counter starts its increment by 1 action from 0.
The current value of the free-running counter can be obtained from the
GPTMTAV register
(3) and this value is compared with a value in the GPTMTAILR register
to see whether they are equal.
(4) If they are same
(5) A signal is sent to the GPTMTAPV to increment it by 1 and reset
the free-running counter to 0 to restart its increment by 1 action.
(6) Then the value in the GPTMTAPV register is compared with the
value in the GPTMTAPR register (prescaler).
Periodic mode
(7) If they are equal, it means that the time is up and a flag
should be set to report this situation.
(8) For periodic count-up mode, the updated or the same time-up
values are reloaded into the GPTMTAILR and the optional
GPTMTAPR registers to begin the next cycle.
(9) For a one-shot mode, the TAEN bit in the GPTMCTL register
is reset to 0 to stop the timer’s operation.
Timer mode Registers
• The GPTMTAILR and the GPTMTAPR registers:
• These two registers are used to keep the start values (for count-down
mode) and time-up values (for count-up mode).
• The former stores the value used for the free-running counter, and the
latter is for the prescaler.
• The GPTMTAV and the GPTMTAPV registers:
• These two registers store the current values for free-running counter
and the prescaler.
• The software can access these two registers to get the current values
for the free-running counter and the current value for the prescaler in
real time.
Periodic Snapshot Timer Mode
• Similar to the Periodic.
• Only difference is that the start values (for count-down) and the
time-up values (for count-up) are not only stored into the
GPTMTAILR and the optional GPTMTAPR registers, but also
reserved in the GPTM Timer A (GPTMTAR) register and the
GPTM Timer A Prescale Snapshot (GPTMTAPS) register.
• In this way, software can determine the time elapsed from the
interrupt generation to the ISR entry by examining the snapshot
values and the current value of the free-running timer.
• Snapshot mode is not available when the timer is configured in
one-shot mode
Wait-For-Trigger Mode
• When software sets the TAEN bit in the GPTM Control
(GPTMCTL) register, the Timer A is enabled and begins
counting up from 0 or down from its preloaded value.
• If the TAWOT bit (Timer A Wait-On-Trigger) in the GPTMTAMR
register is set to 1, even after the TAEN bit is set, the timer does
not start its work, instead it waits for a trigger to begin its
counting actions.
• This operational mode can be used to count the period or the
number of times when an external event occurred to trigger the
timer.
Real-Time Clock Timer Mode
• Both Timer A and Timer B must be concatenated to form a 32-
bit count-up timer.
• The input clock to the RTC is required to be 32.768kHz in RTC
mode.
• The clock signal is then divided down to a 1 Hz rate and is
passed along to the input of the counter.
• When software writes the TAEN bit in the GPTMCTL register to
enable the RTC, the counter starts counting up from 1.
Real-Time Clock Timer Mode
• When the current count value matches the preloaded value in
the GPTMTAMATCHR registers, the GPTM sets the RTCRIS bit
in GPTMRIS register and continues counting until either
(a) a hardware reset occurs or
(b) (b) it is disabled by software by clearing the TAEN bit.
• When the timer value reaches the terminal count, the timer rolls
over and continues counting up from 0.
• If the RTC interrupt is enabled in GPTMIMR, the GPTM also
sets the RTCMIS bit in GPTMMIS register and generates a
controller interrupt
Input Edge-Count Mode
• Configured as a 24-bit or 48-bit up- or down-counter.
• Timer is capable of capturing three types of events: rising edge,
falling edge, or both.
• To enable the timer to work in the Edge-Count mode, the
TACMR bit of the GPTMTAMR register must be cleared.
Input Edge-Count Mode