Interclock Delay Balancing During Clock Tree Synthesis https://solvnet.synopsys.com/retrieve/print/036339.

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Interclock Delay Balancing During Clock Tree Synthesis

Doc Id: 036339 Product: IC Compiler Last Modified: 08/13/2012

Question:

How do I decide which clock domains need interclock delay balancing? Can interclock delay balancing help
reduce setup timing violations?

Answer:

By default, IC Compiler does not perform interclock delay balancing during clock tree synthesis. If a clock
domain is independent of another clock domain, which means there are no timing paths between the clock
domains, skew balancing between the clock domains is not important. If there are timing paths between the
clock domains interclock skew balancing can help to reduce setup timing violations.

Use the report_clock_tree -interclock_timing command to understand the timing dependency

between different clock domains, as shown in the following example:

icc_shell> report_clock_tree -interclock_timing -summary

****************************************
Report : clock tree
Design : ORCA_TOP
Version: G-2012.06-ICC
Date : Mon Jul 9 12:30:16 2012
****************************************
..

Setup
From Clock To Clock WNS CNS NVP Local skew(WNS path)
========== ======== ==== ==== ==== ====================
SDRAM_CLK SD_DDR_CLK 1.910 0.000 0 1.000
SYS_2x_CLK SYS_CLK 0.687 0.000 0 0.000
SYS_CLK SYS_2x_CLK 1.271 0.000 0 0.000

You can also use the report_clock_timing -type interclock_skew -show_clocks command for
more information on the interclock relationship between clock domains in your design.

To enable interclock delay balancing between clock domains during clock tree synthesis use the
set_inter_clock_delay_options, as shown in the following example:

icc_shell> set_inter_clock_delay_options -balance_group "CLK1 CLK2"

icc_shell> clock_opt -inter_clock_balance

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