Design and Simulation of PCI Express Transaction

Layer
Wang Lihua
School of ISE, Shandong University of Science & Technology, Qingdao, China

Abstract--This paper analyzes the architecture and function of credit-based flow control for TLPs. Every request packet
PCI Express Transaction Layer. The author gave the receiver requiring a response packet is implemented as a split
and transmitter flowchart and state transition diagram of transaction. Each packet has a unique identifier that enables
Transaction Layer. The paper designed Transaction Layer IP response packets to be directed to the correct originator. The
core in the System Level with top-down design method, wrote the packet format supports different forms of addressing
Verilog HDL codes to implement Transaction Layer. wrote depending on the type of the transaction. This specification
testbench to verify the correctness of the design module for uses Message Space to support all prior sideband signals, such
function simulation. The codes were simulated by Synopsys VCS. as interrupts, power-management requests, and so on. You
The simulation results show that the designed IP core meets the could think of PCI Express Message transactions as “virtual
required of the protocol of PCI Express™ Base Specification wires” since their effect is to eliminate the wide array of
Revision 2.0, The design validate its correctness and supports the sideband signals currently used in a platform implementation.
function of PCI Express Transaction Layer.
A. Transaction Layer Packet
Keywords--PCI Express; Transaction Layer; TLP Transactions consist of Requests and Completions, which
are communicated using three kind of packets（Posted，
I. INTRODUCTION
Non-Posted and Cpl）. Figure 1 shows a high level serialized
PCI Express is a high performance, general purpose I/O
view of a TLP, consisting of a TLP header, a data payload (for
interconnect defined for a wide variety of computing and
some types of packets), and an optional TLP digest. Figure 2
communication platforms. PCI Express have three discrete
shows a more detailed view of the TLP：The Fmt and Type
logical layers: the Transaction Layer, the Data Link Layer, and
fields provide the information required to determine the size of
the Physical Layer. Each of these layers is divided into two
the remaining part of the header, and if the packet contains a
sections: one that processes transmitted information and one
data payload following the header. The Fmt, Type, TD, and
that processes received information. PCI Express uses packets
Length fields contain all information necessary to determine
to communicate information between components. Packets are
the overall size of the TLP itself. The Type field, in addition to
formed in the Transaction and Data Link Layers to carry the
defining the type of the TLP also determines how the TLP is
information from the transmitting component to the receiving
routed by a Switch.
component. As the transmitted packets flow through the other
layers, they are extended with additional information necessary
to handle packets at those layers.
Figure 1 Serial View of a TLP
II. TRANSACTION LAYER
The upper Layer of PCI Express architecture is the
Transaction Layer. Its primary responsibility is the assembly
and disassembly of Transaction Layer Packets (TLPs). TLPs
are used to communicate transactions, such as read and write.
The Transaction Layer is also responsible for managing
Figure 2 Generic TLP Format

978-1-4244-4507-3/09/$25.00 ©2009 IEEE

B. Handling of Received TLPs
This section describes how all Received TLPs are handled
when they are delivered to the Receive Transaction Layer from
the Receive Data Link Layer, after the Data Link Layer has
validated the integrity of the received TLP.
C. Virtual Channel (VC)
The VC mechanism provides support for carrying,
throughout the fabric, traffic that is differentiated using TC
labels.
The foundation of VCs are independent fabric resources
(queues/buffers and associated control logic). These resources
are used to move information across Links with fully
independent flow-control between different VCs. This is key
to solving the problem of flow-control induced blocking where
a single traffic flow may create a bottleneck for all traffic
within the system. Traffic is associated with VCs by mapping
packets with particular TC labels to their corresponding VCs.
D. Transaction Ordering
Table 1 defines the ordering requirements for PCI Express
Transactions. The rules defined in this table apply uniformly to
all types of Transactions on PCI Express including Memory,
I/O, Configuration, and Messages. The ordering rules defined
in this table apply within a single Traffic Class (TC). There is
no ordering requirement among transactions with different TC
labels. Note that this also implies that there is no ordering
required between traffic that flows through different Virtual
Channels since transactions with the same TC label are not
allowed to be mapped to multiple VCs on any PCI Express
Link. For Table 1, the columns represent a first issued
transaction and the rows represent a subsequently issued
transaction. The table entry indicates the ordering relationship
between the two transactions.
TABLE 1 ORDERING RULES SUMMARY
E. Ordering and Receive Buffer Flow Control
In order to obtain higher efficiency ,Flow Control (FC) is
used to prevent overflow of Receiver buffers and to enable
compliance with the ordering rules, there are six types of
information tracked by Flow Control for each Virtual Channel:
Posted Header（PH）、Posted Data（PD）、Non-Posted Header
（NPH）、Non-Posted Data（NPD）、Completion Header
（CplH）、Completion Data（CplD）.Each Virtual Channel
maintains an independent Flow Control credit pool. The unit of
Flow Control credit is 4 DW for data.
III. SYSTEM ARCHITECTURE AND DESIGN
PCI Express system architecture is made up of three
module: Receive layer、Configuration space and Transmit
layer，as shown in Figure 3.
There are eight VC in Receive layer: VC0-VC7，among
them VC0 is necessary，and others are optional.Each VC
have two modules: Receive Buffer and Controller. Receive
Buffer was divided into six parts in order to store PH、PD、
NPH、NPD、CplH and CplD respectively，header stored
no more than 128 credits，data stored no more than
2047 credits. The size of credits is indicated by FC
credits.Controller implement the function of FIFO、FC and
Sequencing（ordering）.There must be sequence strictly to
the packet of Posed and Cpl,according to the rule of transmit
ordering.
 respectively，all of them are used to configure Arbitrator
configure register, such as to configure VC arbitrator mode .

G. Flowchart and state transition diagram

Figure 4 shows Receiver flowchart, there are four
sub-flowchart:（a）is read flowchart， in this flowchart it is
first to judge pnpc_rd is read_P、read_NP or read_Cpl TLPs
at initial state，if pnpc_rd is 3’b100 then set read_p to start
flowchart (b) and (c) which transmit PH and PD.Length
Figure 3 Diagram of Transaction Layer design
register will record the remainder data in order to judge
F. Module、Signal and Time sequence whether the data completely transmit. When flowchart (b)
Transmit Layer added VC Arbitration and Digest module and (c) are finished, Rx_rd_st will return to initial
to compare with Receive layer. Transmit Layer is not only state.When Data Link Layer transmit packets, Frame
ordering for Posed and Cpl packet, but also detect Flow Synchronous signals will send, flowchart (d) start to receive
Control. data at the same time,St1 will judge next state is P、NP or
Cpl TLP by judge pnpc_wr .
1)Interface Signal to Software Layer and handshake
Sequence rules: desc_n[127:0] indicate the VCn transmit
header and data; data_n[127：0] indicate the VCn Receive
header and data. Rules of Handshake in Header File transmit
and receive: the sender set req_n to indicate RTS (Request To
Send)，the Receiver receives the request then set ack_n；
Rules of Handshake in Data file transmit and receive：the
sender set dfr_n to indicate the beginning of data transmit, and
set ws_n to inform Receiver wait when Receiver is busy in
the data transmit process，next data will be send until ws_n
Figure 4 Receiver Flowchart
clear，it is time to clear dfr_n which inform receiver data send
Then the header and data shall be written. Length Register
finished when the last 1DW data was sent.
is to judge whether data are completely transmission . Write
2)Interface Signal to Data Link Layer and handshake NP、Cpl TLPs and P TLPs roughly as the same.
Sequence rules: desc_data [31：0] are TLP signal which come
The transmitter flowchart is similar to receiver flowchart,
from Data Link Layer, The corresponding part of Fram
as shown in Figure 5.
represent frame header . BlockT indicate Replay state of Data
The only different between transmitter flowchart and
Link Layer, and also indicate to pause the transmit TLP. FC
receiver flowchart is the former needed to add in flow control,
credits n indicate the FC credits value which include
so pnpc_rd also depends on the flow control. if c_ph[7] is 1
cred_alloc_p, cred_alloc_np, cred_alloc_cpl, cl_p, cl_np,
shows the other side is already full.cl_p stands for CredAlloc
cl_cpl that needed transmit or refresh. vc_reqn is set when
of P；and cc_p stands for Credits Consumed of P.Flowchart
VCn needed transmit data to DLL, vc_ack_n is set when
(d) is virtual channel flow. In the initial state, if the data link
Arbitrator permit this request ,when VC received vc_ack_n
layer is not block and vc_req is valid,now_vc value will update
,then set vc_get_n . When last data was sent vc_get_n will be
to next_vc value , and choose next channel. The selection of
cleared at the same time, and then inform Arbitrator to end the
channel is decision by arbitrate mode. Unnecessary vc may be
VC permission. Its configure register include conf_addr,
chosen owing to the arbitrator support look-up table, so we
conf_data_i, conf_data_o, conf_wr, conf_rd are configure
must to judge whether the vc_req_n of this channel is 1 or not
address 、 data in 、 data out 、 read and write signal
at this moment. vc_get_n will clear when the virtual channel
data transmission the last 1DW, and let vc_arb return to initial
state. Before the arbitration we should configurate vc registers
in order to choose the mode of arbitration.
Figure 5 Transmitter Flowchart
IV. SIMULATION
We used Synopsys VCS to simulate.
Figure 6 Transmitter virtual channel simulation diagram
Figure 6 shows the transmitter VC simulation waveform:
part a,receive software layer 10 P TLPs, 20 DW data; part b,
receive 1 NP TLP; part c receive 1 Cpl TLP and 20 DW data;
part d send P TLP to the data link layer; part e send flow
control; part f update flow control data , and send P-TLP; part
g send Cpl; part h send NP finally. The signal changes in
accord with the design requirement of transmitter.
Figure 7 Receiver virtual channel simulation diagram
Figure 7 shows the Receiver VC simulation waveform:
Part a received P、NP and Cpl TPLs, when Software Layer
was idle, then transmit them to Software Layer; Part b,
prevent data transmission to Software Layer, when Software
Layer was busy; part c send P、NP and Cpl TPLs after block
Cancellation. The signal changes of design meets the
requirements of receiver.
V. CONCLUSION
Transaction Layer design is an important part in PCI
Express design. We designed Transaction Layer in the System
Level with top-down design method, and wrote the Verilog
HDL codes to implement it. we wrote testbench for function
simulation. The simulation results show that the designed can
achieve the basic function of PCI Express Transaction Layer,
Meet the protocol of PCI Express™ Base Specification
Revision 2.0. Through Transaction Layer design we can
further implement the PCI Express IP Core, it is also important
for improve equipment transmission bandwidth .
REFERENCES
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2006.12.20
[2] MA Ke-jie .Design and Research of PCI Express bus Switch IP Core.
Shandong University .2007.6.
[3] PLD Applications, PCI Express Expert Core Reference Manual,
2006-02
[4] Michael D.Ciletti, Advanced Digital Design with the Verilog HDL,
Prentice Hall/Pearson, 2005.01.