U 2022 SCHEME —BCS302 MODULE 3 Basic Structure of Computers and Machine Instructions and Programs Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance -Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement. Machine Instructions and Programs: Memory Location and Addresses, Memory Operations, Instruction and Instruction sequencing, Addressing Modes. Text book 2: 1.2, 1.3, 14, 1.6, 2.2, 2.3, 24, 2.5 3.1 Computer Types: Computer is a fast electronic calculating machine which accepts digital input, processes it according to the internally stored instructions (Programs) and produces the result on the output device. ‘The computers can be classified into various categories as given below: & Micro Computer vw Laptop Computer v Work Station Super Computer Main Frame vvw Hand Held » Multi core Micro Computer: A personal computer; designed to meet the eomputer needs of an individual, Provides access to a wide variety of computing applications, such as word processing, photo editing, e-mail, and internet. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Laptop Computer: A portable, compact computer that can run on power supply or a battery unit, All components are integrated as one compact unit. It is generally more expensive than a comparable desktop. It is also called a Notebook. Work Station: Powerful desktop computer designed for specialized tasks. Generally used for tasks that requires a lot of processing speed. Can also be an ordinary personal computer attached to a LAN (local area network). Super Computer: A computer that is considered to be fastest in the world. Used to execute tasks that would take lot of time for other computers. For Ex: Modeling weather systems, genome sequence, ete Main Frame: Large expensive computer capable of simultaneously processing data for hundreds or thousands of users. Used to store, manage, and process large amounts of data that need to be reliable, secure, and centralized. Hand Held: It is also called a PDA (Personal Digital Assistant). A computer that fits into a pocket, runs on batteries, and is used while holding the unit in your hand. Typically used as an appointment book, address book, calculator and notepad. Multi Core: Have Multiple Cores ~ parallel computing platforms. Many Cores or computing elements in a single chip. Typical Examples: Sony Play station, Core 2 Duo, i3, i7 ete. 3.2 Functional Units: A computer in its simplest form comprises five functional units namely input unit, output unit memory unit, arithmetic & logic unit and control unit. Figure 3.1 depicts the functional units of a computer system A.Tnput Unit: Computer accepts coded information through input units, which read the data. The primary input device is typically a keyboard. Whenever a key is pressed, the corresponding letter or digit is automatically translated into its coresponding binary code and transmitted over a cable to either the memory or the processor. Many other kinds of input devices are available, including Mouse, Joystick, Tracker ball, Light pen, Digitizer, Scanner ete. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,2. Memory Unit: Memory unit stores the program instructions (Code), data and results of computations ete. Memory unit is classified as; Primary /Main Memory and Secondary /Auxiliary Memory. Primary/Mai memory: The largest and slowest unit is referred to as main memory. It is a semiconductor memory that operates at electronic speed. Run time program instructions and operands are stored in the main memory. It is faster than secondary storage (like hard drives or SSDs) but loses its content when the power is turned off. The memory contains a large number of semiconductor storage cells, each capable of storing one bit of information. These cells are rarely read or written as individual cells but instead are processed in group of fixed size called words. CPU/PROCE SOR Figure 3.1: Basic Functional Units of a Computer The number of bits in each word is often referred as the word length of the computer. Typical word lengths range from 16 to 64 bits. Data are usually processed within a machine in units of words, multiple of words, or parts of words. When the memory is accessed, usually only one word of data is read or written, Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Addresses are numbers that associates each word location. A given word is accessed by spe ng its address and issuing a control command that starts the storage or retrieval process. The main memory is classified again as ROM and RAM. ROM (Read Only Memory) holds system programs and firmware routines such as BIOS, POST, 1/O Drivers that are essential to manage the hardware of a computer. Memory in which any location can be reached in a short and fixed amount of time after specifying its address is called RAM (Random Access Memory). It is also termed as Read/Write memory or user memory that holds run time program instruction and data. The small, fats RAM units are called caches. While primary storage is essential, it is volatile in nature and expensive. Secondary /Auxiliary Memory: Secondary memories are non volatile in nature. Tt also stores large amount of data and programs particularly for information that is accessed infrequently at cheaper cost. Example: Magnetic disks and tapes, optical disks(CD-ROMs), SD card, Pen drive, Hard disk etc 3. Arithmetic and logic w ALU consist of necessary logic circuits like adder, comparator etc., to perform computer operations of addition, multiplication, comparison of two numbers ete. Suppose two numbers located in the memory are to be added, they are brought into the processor, and the actual addition is carried out by the ALU. The sum may then be stored in the memory or retained in the processor for immediate use. When operands are brought into the processor, they are stored in high speed storage elements called registers. Each register can store one word of data, Access times to registers are somewhat faster than access time to the fastest cache unit in the memory hierarchy. 4. Output Units Computer after computation retums the computed results, error messages, ete. via output unit to the outside world. The standard output device is a video monitor, LCD/TFT monitor. Other output devices are printers, plotters ete. Some units such a graphic displays, provide both an output function and an input function Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.S.Control Unit: Control unit co-ordinates activities of all units such as the Memory, ALU, Input and Output units by issuing control signals. Control signals issued by control unit govern the data transfers and then appropriate operations take place. The actual timing signals that govern the transfers are generated by the control circuits. The timing signals are the signals that determines when a given action is to take place. Data transfers between the processor and the memory are also controlled by the control unit through the timing signals. ‘The operations of a computer can be summarized as follows: 1. The computer accepts information in the form of programs and data through input unit and a set of instructions called programs are stored in the main memory of computer. 2. The CPU fetches those instructions sequentially one-by-one from the main memory, decodes them and performs the specified operation on associated data operands in ALU. 3. Processed data and results will be displayed on an output unit. 4. All ivities pertaining to processing and data movement inside the computer machine are governed by control unit. 3.3 Basic Operational Concepts: The activity in a computer is governed by instructions. To perform a given task, an appropriate program consisting of a list of instructions is stored in the memory. Individual instructions are brought from the memory into the processor, which executes the specified operations. Data to be used as instruction operands are also stored in the memory. A typical instruction might be Add LOCA,RO This instruction adds the operand at the memory location LOCA to the operand in a register in the processor RO, and places the sum into register RO. The original contents of location LOCA are preserved, whereas those of register RO are overwritten. Execution of this instruction requires several steps. First, the instruction is fetched from the memory into the processor. Next, the operation to be performed is determined by the control unit. The operand at LOCA is then fetched and added to the contents of RO. Finally, the resulting sum is stored in Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,register RO. Afier operands have been loaded from memory into processor registers, arithmetic or logic operations can be performed on them. Load LOCA.RI Add R1,RO For the above example, the first of these instructions transfers the contents of memory location LOCA into processor register R1, and the second instruction adds the contents of register RI and RO and places the sum into RO. This destroys the contents of memory location register RI as well as RO, whereas the original contents of memory location LOCA are preserved. For Load and Store instructions, transfers between the memory and the processor are initiated by sending the address of the desired memory location to the memory unit and asserting the appropriate control signals. The data are then transferred to or from the memory. Figure 3.2 shows how the memory and the processor can be connected, It also shows some components of the processor that have not been discussed yet. The interconnections between these components are not shown explicitly since we will only discuss their functional characteristics. In addition to the ALU and the control circuitry, the processor contains a number of registers used for several different purposes. Instruction Register (IR): It holds the instruction that is currently being executed. Its output is available to the control circuits, which generate the timing signals that control the various processing elements involved in executing the instruction, Program Counter (PC); It is another specialized register. It contains the memory address of the next instruction to be fetched and executed. During the execution of an instruction, the contents of the PC are updated to correspond to the address of the next instruction to be executed. It is customary to say that the PC points to the next instruction that is to be fetched from the memory. In addition to the IR and PC, Figure 3.2 shows General-Purpose Registers RO through Rn-I, often called processor registers. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Control n General Purpose Registers Figure 3.2: Connections between the processor and the memory MAR and MDR: Finally, two registers facilitate communication with the memory. These are the Memory Address Register (MAR) and Memory Data register (MDR). The MAR holds the address of the location to be accessed, The MDR contains the data to be written into or read out of the addressed location. Operating Steps: Programs reside in the memory and usually get there through the input unit. Execution of the program starts when the PC is set to point to the first instruction of the program. The contents of the PC are transferred to the MAR and a Read control signal is sent to the memory. When the addressed word (in this case, the first instruction of the program) has been fetched from the memory it is loaded into register IR. At this point, the instruction is ready to be decoded and executed. Instructions such as Load, Store, and Add perform data transfer and arithmetic operations. If an operand that resides in the memory is required for an instruction, itis fetched by sending its address to the MAR and initiating a Read operation. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,When the operand has been fetched from the memory, it is transferred from MDR to the ALU, After operands have been fetched in this way, the ALU can perform a desired arithmetic operation, such as Add, on the values in processor registers. The result is sent to a processor register (MDR). If the result is to be written into the memory with a Store instruction, it is transferred from the MDR to the memory, along with the address of the location where the result is to be stored, and then a Write operation is initiated. At some point during the execution of each instruction, the contents of the PC are incremented so that the PC points to the next instruction to be executed. Thus, as soon as the execution of the current instruction is completed, the processor is ready to fetch a new instruetion, In addition to transferring data between the memory and the processor, the computer accepts data from input devices and sends data to output devices. Thus, some machine instructions are provided for the purpose of handling 1/0 transfers. Normal execution of a program may be preempted if some device requires urgent service. For example, a monitoring device in a computer-controlled industrial process may detect a dangerous condition. In order to respond immediately, execution of the current program must be suspended. To cause this, the device raises an interrupt signal, which is a request for service by the processor, The processor provides the requested service by executing a program called an interrupt-service routine, Because such diversions may alter the internal state of the processor, its state must be saved in the memory before servicing the interrupt request. Normally, the information that is saved includes the contents of the PC, the contents of the general-purpose registers, and some control information. When the interrupt-service routine is completed, the state of the processor is restored from the memory so that the interrupted program may continue. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.3.4 Bus structure When a word of data is transferred between units, all its bits are transferred in parallel, that is, the bits are transferred simultaneously over many wires, or lines, one bit per line. A group of lines that serves a connecting path for several devices is called a bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes. The bus thus consists of three sets of lines used to carry address, data, and control signals. The simplest way to interconnect functional units is to use a single bus, as shown i Figure 3.3. Figure 3.3 Single Bus-structure All the units are connected to this bus. Because the bus ean be used for only one transfer at a time, only two units can actively use the bus at any given time, Bus control lines are used to arbitrate multiple requests for use of the bus. The main virtue of the single-bus structure is its low cost and its flexibility for attaching peripheral devices. Systems that contain multiple buses achieve more concurrency in operations by allowing ‘two or more transfers to be carried at the same time, This leads to better performance but at an increased cost. Bus operation: The bus consists of three sets of lines used to carry address, data, and control signals. /O device interfaces are connected to these lines, as shown in Figure 3.4 for an input device. Each VO deviee is assigned a unique set of addresses for the registers in its interface. When the processor places a particular address on the address lines, it is examined by the address decoders of all devices on the bus. The device that recognizes this address responds to the commands issued on the control lines. The processor uses the control lines to request Read or a Write operation, and the requested data are transferred over the data lines. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Address tines Data tines bi | Contnal lines Aiko Central looenlee cvreuis regions imtertace ond vo. Input device Figure 3.4 Bus connections to the Input device When 1/0 devices and the memory share the same address space, the arrangement is called memory-mapped VO. Any machine instruction that can access memory can be used to transfer data to or from an /O devi For example, if the input device in Figure is a keyboard and if DATAIN is its data register, the instruction Load DATAIN, R2 reads the data from DATAIN and stores them into processor register R2 Similarly, the instruction Store R2, DATAOUT sends the contents of register R2 to location DATAQUT, which may be the data register of a display device interface. The status and control registers contain information relevant to the operation of the /}O device. The address decoder, the data and status registers, and the control circuitry required to coordinate VO transfers constitute the device’s interface circuit, Drawbacks of the Single Bus Structure: The devices connected to a bus vary widely in their speed of operation. Some electromechanical devices are relatively slow, such as printer and keyboard. Other devices like magnetic or optical disks are considerably faster, Memory and processor uni ‘operate at clectronic speeds, making them the fastest parts of a computer. Efficient transfer mechanism thus is needed to cope with this problem. Dr. Ciyamala Kushbu §, AP/ISE, CMRIT, Bengaluru.Solution: A common approach is to include buffer registers with the devices to hold the informs ional n during transfers. Another approach is to use two-bus structure and an ad transfer mechanism. For example: Let us consider the transfer of an encoded character from a processor to a character printer. The Processor sends the character over the bus to the printer buffer. Since the buffer is an electronic register, thus transfer requires relatively litle time. Once the buffer is loaded, the printer can start printing without further intervention by the processor. The bus and the processor are no longer needed and can be released for other activity. The printer continues printing the character in its buffer and is not available for further transfers until this process is completed. Thus, buffer registers smooth out timing differences among processors, memories and 1/O devices. They prevent a high speed processor from being locked to a slow I/O device during a fers. This allows the processor to s sequence of data trans citch rapidly from one device to another, interweaving its processing activity with data transfers involving several HO devices. 3.5 Performance : The most important measure of the performance of a computer is how quickly it can execute programs. The speed with which a computer executes programs is affected by the design of its instruction set, its hardware and its software, including the operating system, and the technology in which the hardware is implemented. Because programs are usually written in a high-level language, performance is also affected by the compiler that translates programs into machine language. For best performance, it is necessary to design the compiler, the machine instruction set, and the hardware in a coordinated way. The total time required to execute the program is elapsed time is a measure of the performance of the entire computer system, It is affected by the speed of the processor, the disk and the printer. The time needed to execute a instruction is called the processor time. In Figure 3.5, the elapsed time is tote. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Peinter Disk Program te Figure 3.5: User program and OS routine sharing of the processor Just as the elapsed time for the execution of a program depends on all units in a computer system, the processor time depends on the hardware involved in the execution of individual machine instructions. This hardware comprises the processor, cache memory as a part of the processor and the memory which are usually connected by the bus as shown in the Figure 3.6. Bus Figure 3.6: Processor Cache Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Let us examine the flow of program instructions and data between the memory and the processor. At the start of execution, all program instructions and the required data are stored in the main memory. As the execution proceeds, instructions are fetched one by one over the bus into the processor, and a copy is placed in the cache later if the same instruction or data item is needed a second time, it is read directly from the cache, The processor and relatively small cache memory can be fabricated on a single IC chip. The internal speed of performing the basic steps of instruction processing on chip is very high and is considerably faster than the speed at which the instruction and data can be fetched from the main memory. A program will be executed faster if the movement of instructions and data between the main memory and the processor is minimized, which is achieved by using the cache. For example:~ Suppose a number of instructions are executed repeatedly over a short period of time as happens in a program loop. If these instructions are available in the cache, they can be fetched quickly during the period of repeated use. The same applies to the data that are ‘used repeatedly. 1 Processor Cloc! Processor circuits are controlled by a timing signal called clock. The clock defines the regular time intervals called clock cycles. To execute a machine instruction the processor divides the action to be performed into a sequence of basic steps that each step can be completed in one clock eyele. The length P of one clock cycle is an important parameter that afifects the processor performance. Processor used in today’s personal computer and work station have a clock rates ‘that range from a few hundred million to over a billion cycles per second. 3.5.2 Basic Performance Equation: Let *T” be the processor time required to execute a program that has been prepared in some high-level language. The compiler generates a machine language object program that corresponds to the source program. Assume that complete execution of the program requires the execution of N machine cycle language instructions. The number N is the actual number of instruction execution and is not necessarily equal to the number of machine eyele instructions in the object program. Some instruction may be executed more than once, which in the case for instructions inside a program loop others may not be executed all, depending on the input data used. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Suppose that the average number of basic steps needed to execute one machine cycle instruction is $, where each basic step is completed in one clock cyele. If clock rate is *R” cycles per second, the program execution time is given by Equation 1 is often referred to as the Basie Performance Equation. We must emphasize that N, S & R are not independent parameters, Hence, changing one, may affect another. Introducing a new feature in the design of a processor will lead to improved performance only if the overall result is to reduce the value of T. 3.5.3 Clock Rate: Clock Rate R is inversely proportional to the Clock performance P where, (2) tis measured in Cycles per second. These are two possibilities for increasing the clock rate *R’. L. Improving the IC technology makes logical circuit faster, which reduces the time of execution of basic steps. This allows the clock period P, to be reduced and the clock rate R to be increased. 2. Reducing the amount of processing done in one basie step also makes it possible to reduce the clock period P. However if the actions that have to be performed by an instructions remain the same, the number of basic steps needed may increase. cts all aspects of the processor's operation equally with the exception of the time it takes to access the main memory. The value of T will be reduced by the same factor as R is increased. 3.5.4 Performance Measurement: It is very important to be able to access the performance of a computer, Computer Increase in the value *R” that is entirely caused by improvements in IC technology affe designers use performance estimates to evaluate the effectiveness of new features. Hence measurement of computer performance using bench mark programs is done to make comparisons possible, standardized programs must be used. ‘The performance measure is the time taken by the computer to execute a given bench mark. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.Initially some attempts were made to create artificial programs that could be used as bench mark programs. But synthetic programs do not properly prediet the performance obtained when real application programs are run. A non-profit organi ion called SPEC- system performance Evaluation Corporation selects and publishes bench marks. The program selected range from game playing, compiler, and data base applications to numerically intensive programs in astrophysics and quantum chemistry. In each case, the program is compiled under test, and the running time on a real computer is measured. The same program is also compiled and run on one computer selected as reference. The ‘SPEC’ rating is computed as follows. __ Running time ont hereference computer SPEC rating = ‘Running time onthe computer under test 3) If the SPEC rating = 50, it means that the computer under test is 50 times as fast as the UltraSPARC-10. This is repeated for all the programs in the SPEC suit, and the geometric mean of the result is computed. Let SPEC, be the rating for program ‘i’ in the suite, The overall SPEC rating for the 1 SPEC rating = ¢ seg e Where ‘n’ = number of programs in suite, Because the actual execution time is computer is given by , measured, the SPEC rating is a measure of the combined effect of all factors affecting performance, including the compiler, the OS, the processor, the memory of computer being tested. Machine Instructions and Programs 3.6 Memory Locations and Addresses ‘The memory consists of many millions of storage cells, each of which can store a bit of information having the value 0 or 1. It is organized in such a way that a group of n bits can be stored or retrieved in a single, basic operation. Each group of n bits is referred to as a word of information, and n is called the word length. The memory of a computer can be schematically represented as a collection of words, as shown in 3.7. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,a [pe oe te a op - Figure 3.7: Memory words Modern computers have word lengths that typically range from 16 to 64 bits. If the word length of a computer is 32 bits, a single word can store a 32-bit signed number or four ASCII- encoded characters, each occupying 8 bits, as shown in Figure 3.8. A unit of & bits is called a byte, Machine instructions may require one or more words for their representation sab I [eee Te] LE sign tity = ofr poste munters a. fr egnive umber (@) A signed integer rd AScIE ASCIL asc Asc characier character’ == character, «character (0) Four characters Figure 3.8 Encoded information in a 32-bit word Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Accessing the memory to store or retrieve a single item of information, either a word or a byte, requires distinet names or addresses for each location. It is customary to use numbers from 0 to 2'~ 1, for some suitable value of k, as the addresses of successive locations in the memory. Thus, the memory can have up to 2* addressable locations. The 2'addresses constitute the address space of the computer. For example, a 24-bit address generates an address space of 2” (16,777,216) locations. This number is usually written as 16M (16 mega), where IM is the number 2°” (1,048,576). A 32-bit address creates an address space of 2” or 4G (4 giga) locations, where 1G is 2" Note: Commonly used notations are K (kilo) for the number 2" (1,024), and T (tera) for the number 2, 3.6.1 Byte Addressability A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits. It is impractical to assign distinct addresses to individual bit locations in the memory. The most practical assignment is to have successive addresses refer to successive byte locations in the memory. This assignment used in most modern computers is known as Byte Addressability Byte locations have addresses 0, 1, 2,.... Thus, bits, successive words are located at addresses 0, 4, if the word length of the machine is 32 with each word consisting of four bytes 3.6.2 Big-Endian and Little-Endian Assignments There are two ways that byte addresses can be assigned across words, as shown in Figure 39 (2) Big-endian assignment (©) Lttle-endian assignment Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Figure 3.9: Byte and word addressing The name big-endian is used when lower byte addresses are used for the more significant bytes (the leftmost bytes) of the word. The name little-endian is used for the opposite ordering, where the lower byte addresses are used for the less significant bytes (the rightmost bytes) of the word. In both cases, byte addresses 0, 4, 8,..., are taken as the addresses of successive words in the memory of a computer with a 32-bit word length. These are the addresses used when accessing the memory to store or retrieve a word. 3.6.3 Word Alignment The word locations have aligned addresses as they begin at a byte address that is a multiple of the number of bytes in a word. Hence, if the word length is 16 (2 bytes), aligned words begin at byte addresses 0, 2, 4,..., and for a word length of 64 (23 bytes), aligned words begin at byte addresses 0, 8, 16, 3.6.4 Accessing Numbers, Characters and strings ‘A number usually occupies one word, and can be accessed in the memory by specifying its word address. Similarly, individual characters can be accessed by their byte address and strings by successive byte addresses. 3.7 Memory Operations Both program instructions and data operands are stored in the memory. To execute an instruction, the processor control circuits must cause the word (or words) containing the instruction to be transferred from the memory to the processor. Operands and results must also be moved between the memory and the processor. Thus, two basic operations involving the memory are needed, namely, Read and Write. The Read operation transfers a copy of the contents of a specific memory location to the processor. The memory contents remain unchanged. To start « Read operation, the processor sends the address of the desired location to the memory and requests that its contents be read. The memory reads the data stored at that address and sends them to the processor. The Write operation transfers an item of information from the processor to a specific memory location, overwriting the former contents of that location. To initiate a Write operation, the processor sends the address of the desired location to the memory, together with the data to be written into that location, The memory then uses the address and data to perform the write. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.3.8 Instruction and Instruction sequencing A computer must have instructions capable of performing four types of operations: + Data transfers between the memory and the processor registers metic and logic operations on data + Program sequencing and control /O transfers 3.8.1 Register Transfer Notation Possible locations that may be involved in transfer of information from one location in a computer to another are Memory locations, Processor registers, Registers in the I/O subsystem, Eg: R2 — [LOC] Here the contents of memory location LOC are transferred into processor register R2. R4— [RIA IR3] Here, the contents of registers R2 and R3 are added and their sum is placed into register RA. This type of notation is known as Register Transfer Notation (RTN). 3.8.2 Assembly-Language Notation The notation to represent machine instructions and programs is assembly language. Eg: MOVE LOG.RI Here, the contents of LOC are unchanged by the execution of this instruction, but the old contents of register R2 are overwritten. ‘The second example of adding two numbers contained in processor registers R2 and R3 and placing their sum in R4 can be specified by the assembly-language statement Add R4, R2, R3 In this case, registers R2 and R3 hold the source operands, while R4 is the destination. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,3.8.3 Basic Instruction Types General two-address instruction has the format, Operation Source, Destination Eg: Load R2,A #Contents of R2 is moved to memory location A Add R2,R3 # Contents of R2,R3 are added and stored into R3 General three-address instruction has the format, Operation Sourcel, Source 2, Destination Eg: Add Ri,Rj,RK _/ Contents of Source Registers Ri, Rj are added and stored into Destination Register RK. General one-address instruction has the format, Operation Operand Operand may be source or destination depending upon the operation Eg: Load A # Copies the content of memory location A into Accumulator Store A # Copies the content of Accumulator into memory location A. 3.8.4 Instruction Execution and Straight-Line Sequencing Let us consider the task C= A + B, implemented as CHA IB] Figure 3.10 shows a possible program segment for this task, We assume that the word length is 32 bits and the memory is byte-addressable, The four instructions of the program are in successive word locations, starting at location i, Since each instruction is 4 bytes long, the second, third, and fourth instructions are at addresses i +4, i +8, and i+ 12. The processor contains a register called the program counter (PC), which holds the address of the next instruction to be executed. To begin executing a program, the address of its first instruction (i in our example) must be placed into the PC. Then, the processor control circuits use the information in the PC to fetch and exes instructions, one at a time, in the order of inereasing addresses. This is called straight-line sequencing. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,During the execution of each instruction, the PC is ineremented by 4 to point to the next instruction. Thus, after the Store instruction at location i + 12 is executed, the PC contains the value i + 16, which is the address of the first instruction of the next program segment. Address “Coments Figure 3.10 A program for C — [A}+1Bl. Exccuting a given instruction is a two-phase procedure. In the first phase, called instruction fetch, the instruction is fetched from the memory location whose address is in the PC. This instruction is placed in the instruction register (IR) in the processor. At the start of the second phase, called instruction exeeute, the instruction in TR is examined to determine which operation is to be performed. The specified operation is then performed by the processor. This involves a small number of steps such as fetching operands from the memory or from processor registers, performing an arithmetic or logic operation, and storing the result in the destination location, 3.8.5 Branching Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,The branch instruction loads a new address into the program counter. As a result, the processor fetches and executes the instruction at this new address, called the branch target, instead of the instruction at the location that follows the branch instruction in sequential address order, A conditional branch instruction causes a branch only if a specified condition is ion is not satisfied, the PC is incremented in the normal way, and the next instruction in sequential address order is fetched and executed. satisfied. If the con Let us consider the task of adding a list of n numbers as shown in Figure 3.11 Branch_if_[R2|>0 LOOP This is a conditional branch instruction that causes a branch to location LOOP if the contents of register R2 are greater than zero. This means that the loop is repeated as long as there are entries in the list that are yet to be added to R3. At the end of the nth pass through the loop, the Subtract instruction produces a value of zero in R2, and, hence, branching does not occur. Instead, the Store instruction is fetched and executed. It moves the final result from R3 into memory location SUM, Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,‘ ou eae we Comte fe n—8 [Add R2,R2,R3 Figure 3.11 A program for adding n numbers. 3.8.6 Condition Codes Recording the required information in single big is called condition code flag. Four commonly used flags are, N-Negative WSet to 1 if the result is negative , otherwise cleared to zero 0. Z-Lero #Set to | if the result is Zero , otherwise cleared to zero 0. V-Overflow #Set to | if the arithmetic overflow oceurs, otherwise cleared to zero 0. C-Carry #Set to | if the result has carry , otherwise cleared to zero 0. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,3.9 Addressing Modes The different ways for specifying the locations of operands in an instruction are known as Addressing Modes. Name ‘Assembler syntax Addressing function Immediate # Value Operand = Value Register Ri BA=Ri Absolute (Direct) LOC EA= LOC Indirect (Ri) EA=[Ri] (LOC) EA= [LOC] Index X(Ri) EA=[Ri]+X Base with index (Ri, Rj) EA = [Ri] + [Ril Base with index —_X (Ri, Ri) EA= [Ri] +[Ri]+X and offset Relative x(PC) EA =[PC]+X Autoinerement «Rit EA = [Ri]; Increment Ri Autodecrement (Ri) Decrement Ri; EA = [Ri] BA = effective address Value = a signed number Figure 3.12: Addressing modes L.Immediate mode: The operand is given explicitly in the instruction. Syntax: #Value Example : Move #200, RO This instruction places the value 200 in register RO. Clearly, the Immediate mode is only used to specify the value of a souree operand, Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,The operand is the contents of a processor register; the name of the register is given in the instruction Syntax: Ri Example : Move R2, RI This instruction moves the content of Register R2 to Register RI 3.Absolute or Direct mode: The operand is in a memory location; the address of this location is given explicitly in the instruction, Syntax: LOC Example: Move LOC, R2 This instruction moves the content in memory location LOC to Register R2 4.Indirect mode: The efiective address of the operand is the contents of a register that instruction, Syntai ®) Example: Add (R1),RO ‘Add (RI), RO Main memory B RL B Register Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.Figure 3.13: Indirect addressing To execute the Add instruction in Figure 3.13, the processor uses the value which is in register RI, as the effective address of the operand, It requests a read operation from the memory to read the contents of location B. the value read is the desired operand, which the processor adds to the contents of register RO and the resultant sum is stored in RO. S.Index mode: The effective address of the operand is generated by adding a constant value to the contents of a register. Syntax: X(Ri) Where X denotes the constant value contained in the instruction and Ri is the name of the register involved. The effeetive address of the operand is given by EA = X + [Ri Example: Add 20(R1),R2 Add 20(R1), R2 1000) 1000 RI 20 = offset 1 1020 Figure 3.14 Indexed addressing In Figure 3.14, the index register, R1, contains the address of a memory location, and the value 20 defines an offset (also called a displacement) from this address to the location where the operand is found. This operand is added to the content in Register R2 and the resultant sum is placed inside Register R2. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,6. Base with Index mode The effective address of the operand is sum of the contents of registers Ri and Rj Syntax: (Ri,Rj) EA=[Ril+ [Rj] Example: Add (R1,R2),R3 Here, the index registers, RI and R2, contains the address of a memory location, which is summed up to give the address to the location where the operand is found. This operand is added to the content in Register R3 and the resultant sum is placed inside Register R3. 7. Base with Index and Offset mode The effective address is the sum of the constant X and the contents of registers Ri and Rj. Syntax: X(RiRj) EA=X+[R#Rjl Example: Add 20 (R1,R2),R3 Here, the index registers, RI and R2, contains the address of a memory location, which is summed up, and the value 20 defines an offset (also called a displacement) from this address to the location to give the address to the location where the operand is found. This operand is added to the content in Register R3 and the resultant sum is placed inside Register R3. 8.Relative mode: The effective address is determined by the Index mode using the program counter in place of the general-purpose register Ri. Syntax: X(PC) EA=X+(PC] Example: Branch > 0 LOOP This instruction eauses program execution to go to the branch target location identified by the name LOOP if the branch condition is satisfied. This location can be computed by specifying it as an offset from the current value of the program counter. struction, the offset is given as a signed number. Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru. ince the branch target may be either before or after the branc9. Auti crement mode: The effective address of the operand is the contents of a register specified in the instruction, After accessing the operand, the contents of this register are automatically to point to the next item in a list, Syntax: (Ri)+ EA = [Rijs Increment Example: Add (R2)+R1 10. Auto-decrement mode: The contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand, Decrement Ri A= [Ri] Example: Add -(R2),R1 Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru,Disclaimer: The notes are prepared for the welfare of 3" Semester Students under VTU 2022 scheme. The contents are taken from the reference book. All rights go to the authors of the Reference Book. Reference Book: Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, Sth Edition, Tata McGraw Hill, Dr. Ciyamala Kushbu S, AP/ISE, CMRIT, Bengaluru.