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    IEEE - An Adaptive Low Power DC-DC Converter Concept For PLL (%1.2)

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    mir.cazasu27

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    © All Rights Reserved
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    AN ADAPTIVE LOW POWER DC-DC CONVERTER CONCEPT FOR PLL CONTROLLED TUNING OF RF CIRCUITS ‘Alan Yeo and Hans Brekelmans, Philips Sound & Vision, Tuner Development Singapore ABSTRACT This paper describes a DC/DC converter intended to generate the required reverse voltage for varicap diodes used in RF resonance circuits. As its primary purpose is use in consumer RF products, the proposed design, operating from SV, was optimized for low cost. Close proximity to sensitive RF eireuluy requires DC/DC converter operation with minimal Radio Frequency Interference Therefore, instead of using a switching type regulator, the proposed design uses a sinusoid signal witha frequency of about 250 kz, that is stepped-up to the required amplitude by an impedance transformation using an LC resonance circuit. A double wave rectifier converts the AC signal to a DC voltage. A basic idea underlying the converter design is that interference can be kept within limits by minimizing the amount of power to be delivered to the loa. 1. INTRODUCTION Modem electronic RF tuners utilize variable capecitance diodes (aricaps) for tuning of filtes and oscillator circuits. The capacitance of such a device varies as a function of the reverse voltage applied across the terminals. Varicaps operated with a reverse bias voltage between 1 and 28V are commonly used in TV tuners, eable converters, cable modems and similar RF consumer products. Limitations of linearity preclude the use of varicaps operating from lower voltages and despite recent progress in the development of so called “low -voltge varicap 4 aie Hal diode (Ref-1}, use of 30V varicaps is still stte-ofthe-an. Yet the steady trend towards lower supply voltage causes the 30V for varicap tuning to representa growing burden for circuit design. DCIDC conversion is one way of solving this problem. As reverse biased varicaps only take a very small leakage current, most of the current delivered by the DC/DC converter is consumed by the PLL tuning system itself. Low power consumption therefore was pursued by minimizing the tuning current requirement of the PLL tuning synthesizer. This in tuen was done by making the converter an integral part of the tuning system, This paper describes the basic idea, experimental results and the practical implementation, 2. DCIDC CONVERTER CONCEPT Figure 1 shows a typical PLL tuning system constituting of, amongst others, an IC with a reference divider, programmable divider, phase detector and charge pump. An amplifier OA together with a number of passive components forms the PLL. loopfiter. Current pulses from the charge pump ae integrated in capacitor C, across which the tuning control voltage Vt is built Up in the range 0.5 to 28V. As combining transistors with high breakdown voltage and high cut-off frequency pose contradictory IC technology requirements, the part of the amplifier that actually handles the 28V ‘tuning voltage is confined 0 a single transistor. A simple pull up resistor R connected to a 33V supply rail allows tuning voltage up to at Teast 28V. The IC itself is supplied from, fr instance, +SV. +900 OF 2.5-200 From toca! — Os Figure 1 Conventional PLL tuning synthesizer with separate tuning supply (0-7908-4971-8/97/810.00 © 1997 IEEE 128 transformer] osu Teen 5-260 atl fet H acto Tr Figure 3 Transformer /rectifercircut Figure 2 depicts the proposed DCIDC converter synthesizer combination. The entire tuning system now operates from a single +5V supply voltage. The extemal +33V supply has been replaced by a transformer rectifier block which is detailed in ‘Figure 3. The block comprises a step-up transformer followed by ‘a double-wave rectifier. The PLL synthesizer IC is extended with three new functions: a current comparator circuit built around amplifier OA2, a fixed frequency waveform synthesizer and a multiplier. The waveform synthesizer creates a near-sinusoid signal from the erystal reference using a ROM table and a D/A ‘converter. The multiplier varies the amplitude of the sinusoid signal sent into the primary of the transformer as a function of the comparator OA2 output signal, The transformation ratio IN, Figure 3, is chosen such that the peak-to-peak primary drive signal amplitude will nt exceed the TC supply voltage range. Hence, no saturation will occur even ‘when the maximum tuning voltage is required. Adaptive feedback control is achieved by sensing the amount of current I, lowing though the tuning transistor T and comparing, it to a reference curtent Ip. Any differential error is used to modify the sine-wave amplitude in a direction that attempts to restore the equilibrium I, = Ig When the PLL isin a stationary condition, the current will be equal to the external cUTTEnt Ina 129 ‘save forthe base curent into T and any leakage eurenis flowing ito the varicaps connected to Vi. AS these currents are very small the load current Ig in stationary condition willbe almost equal (0 lag - Hence, the vollage Vde generated by the DC/DC converter will be above the actual Vt by a fixed amount equal t0 Totes R, ‘The operation of the DC/DC converter synthesizer combination depicted in Figure 2 can be further illustrated by an assumed change of tuning frequency. Such a change is initiated by an teration of the PLL. programmable divider ratio. When the der ratio change results in the PLL tuning up (requiring an increase in Vt), part ofthe Ina Current will be needed to charge the loopfilter capacitor C. This current will consequently not flow into the wning transistor T. The current comparator, recognizing a lowering of current from the DC/DC converter part, will raise the converter drive level, Reversibly, when tuning down, the current through the transistor Twill be the sum of the current lig plus @ capacitor de-charging current, effectuating a lowering ofthe drive level ‘The overall power to be delivered by the DC/DC converter strongly depends onthe Current Iigg. Minimizing power handling fof the converter is predominantly a matter of reducing lpg The Tas Adaptation to actual PLL current requirement of the Figure 3 47m Banos LO from Tuner 2 8 | PLL synthesizer Sax] TSASSI? Figure 4 Experimental circuit concept is essential to minimizing power consumption. The control loop allows the quiescent current hy to be set to a much lower value as compared to the standard PLL application in Figure 1. In the lates, up to 1.5 mA will flow at low tuning voltages. Reducing the eurent by increasing the pull-up resistor R leads toa loss of tuning speed at the upper end. The adaptive Dehavior of Figure 2 will ensure that tuning supply current is ‘generated when itis needed, while returning to a low quiescent level when the tuning transient has died out. Henee, no loss in tuning speed is suffered. OF course, the transformer / rectifier and the available AC drive level must be able to deliver the surplus curent needed during tuning transients 3. EXPERIMENTAL RESULTS Verification ofthe proposed concept was done using the control circuitry according Figure 4. A PLL synthesizer IC (TSASS12) with an external tuning transistor QU is used. With an ‘operational amplifier ICI (LM324) the current through QU is, ‘compared with a reference current ly set with the potentiometer I (500 k2). The output signal of ICI controls the drive level to the step up transformer KI by varying the forward transconductance ofthe a dual gate MOS FET MI (BE904) aver its gate 2 volge. An external generator VI delivers a sinusoid ‘AC signal. The shielded transformer KI with a 1:13 voltage transformation ratio (47H, 8 mH) followed by a double wave rectifier D1, D2 (BAVIOS) converts the AC signal into a DC voltage Vdc. Figures 5 present results of transient response,

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