MAXIM Serial-Output, 250ksps 12-Bit ADC General Description peie anelog-to-digital convert Chat achieves a 250k samoles per second (kSPS) mong rate by combining afas tacinold (0 4us max acau'sion tre}, a3 Sus ADC, and a buried-zerer volt age felerence. The deve also saves space with seria ‘SO pack ly and reference decouping capacitors ate the anternal components needed. The CLOCK input ea Stiven from an exotral dvided-down microprocessot lock or ram the seriaclock outputo® a microcontaler The MAXI76 works wth ¥5V and 12V to T5V supply vvtages 148m typ power ass\paton The MAX176's.wie sail interface works wth general purpose sarialte-parallel converters, auch as the TAHCS05, ae well as with digtal signal proceasars anc microcontrollers. is Sie sora inertace i uly Com ibe with SPI, QSPI and Microwre”™ inertace stan ards, Applications Telecommuricaione ta-Signal Processing (Ds trad Signal Processing ustral Data Aequison Functional Diagram Maxim with T/H and Reference Features ¢ 12-81 Resolution and Linearity, 4 0.415 Track/Mold Acqui 4 3.518 Max Conversion Time 4 250ksps Sampling Rate 4 SPI, QSPr- and Microwire "-Compatbie Serial Output 4 SV input Voltage Range + On-Chip Voltage Reference Low Power (148m) 4 Easy to Opto: oF Transformer-solate Small-Footprint&-Pin DIP, 16-Pin SO ion Time Ordering Information PART TEMR.RANGE pnvPackace: ERROR NAXITEBCHE OC 10470. 16 Wide SO 1 NALI7EBCD OCI TOS 1 rs tera contd ons page. Pin Configurations oneew oF 6 amare |" oxim integrated Progucts 1 Call toll free 1-800-998-8800 for free samples or literature.MAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference ABSOLUTE MAXIMUM RATINGS seo1@ GD 03¥'0+7Y Operating Temperature ages Weave wdavean ast le” ocw700 aiseNS HN Man.e 46000 vase ‘ita nt tage to GND 23%, voo v9) _MAKITENGR ssciriase Bia Outer vtage ONC B5VNE0 S03V StrageTenpectve Range Ct sioe Cina Power Dasoson Ta = 1706) {cad empureure sig, 1036) cae Sihn Mame I arate Oa some 7D). 727m {me SO ime 9S2~NC above o7OC) 762m Sn CERO (oomle SDT abow V7). ho ELECTRICAL CHARACTERISTICS (Y= 488% 140-15 75, fun = RF HARTGE ren = Mr MARY. T= TT PARAMETER smoot | ‘CONDITIONS wn oe wax | uns ‘ADCACCURACY eshte Guvarteed moroione orien z Be snoieean tines) | owe, | ATinto Tine | MAXI7EBC eo Inara enna Noe 1 anaes se Tee wserreany erent Nerinearty tt) | DML | waazen — u a ee Maxr76 58 et rr ws 2 | se fet Teraco| 08 sone FulSeae enor) re | ie_| “ise FullScaeTerpoo (Note) seausrgrelwence dt a pom'c {ANALOGINPUT rou Votage Range eg] 0 ngu Capactinee Wot 8) o | or INTERNAL REFERENCE [Wier Oupuvotags [aw S00 si [—W \VREF Ouiput Tempco INote 6) peers — 3° | ppm poe aKITE Ent sao | Ome oa 0d < 77 |Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Figure 2 MAXI76 Anata Equvaion Creat Burst Mode Figuee 2 ilusvates the ting relationship between the Convert sia, lock. ang ata wavelorms when bo MAKI 76 operates i burs! made. Corvor stats sing ‘cage causes to itemal rackMold (TH) crcut 0 hold ‘he analog nput vatage ard intates ine conversion The Tiiteture a track mode atorhe 13th Faling cockedge. \When burst mode is used, clock edges typically appear after convert slats rising edge. Thus, Figure 4 shows the recommended placement o clock’ faling sege aller he sing edge of convert star, this placement ‘ensures iat the sera output sleacing high bit appears at the frst fling clock edge alter conver! start rises ‘The convert stat Io clock skew specticaton, tSc1 diclales the suggested positoning of clock’s faling edge. No problem accurs If clock’s faling edge ap ppeats earlier than suggested. he serial cata stream is Simpy delayed by a clock cycle. Note, however, that a high-speed clock edge accurrngwithin40ns of convort star's ring ego could cause a small inaccuracy in tho sampled voltage. This © due fa the ground bounce induced by he clock edge speed: Each bit ofthe serial dala steam appears ater a clock faling edge. Since hare ave (2 datains and ore leading hgh a, at east 13 ang clock edigos are needed to sit fut these bs. Fsing edgos are usualy used to strobe the serial data into a ogister Pay allenton to the cick: tordata delay (ipa) sposiication at the highost clock maxim aN 28 wet - | eo “| Irequane'es when using @ ising clock edge to strobe a cata into a register, Extra clock pulses por anew conver stat rising edge have na ellect onthe corwerter eraion. Continuous-Conversion Mode Flour 5 shows tne timing relationship between the con vert stan. clock, and Gata waves when the MAX176 IS operaies in continuous-conversion mode. AS nthe burst mode, convent star's ring edge paces the TH rout in hed mode and iiiates the conversian. Hore Sis, the Tathfaling clack edge puts the T/H in Wack In. continuous-conversion mode, convert stan!s ising ledge must be conecily past oned uth respect lo clone s faling edges to satsly Ine sco and Igor spec tcatons (Figute6). These spetiicatens must be met ire serial data sreamhighbl sto appea alter Ine frst tang clock edge One caution: Angh-speed clock ange may cause found bounee. Fine sing edge of convor sir wilh fone of a clack adgo, ne voage stored nthe TM may be sight inaccurate because oh ground bounce ‘A conversion period ol 18 clack cycles minim i re ‘ommended. Most system wil be T6 cycles since such ‘counters are mare corenon. Extra clock pulses between ‘conversions fave no elfeci. tthe clack frecuency 1s below 2 6Mbiz, a minum period of 14 cycles can aso be use 9LLXVNMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Fuad MAR Teng gue NAXITS Teng Coranous Mose maxim-Output, 250ksps 12-Bit ADC with T/H and Reference oot a we ai wasn a ss apeaaie ree anne mae rosy espa cees (Cotindous feos ° re fonee Upper and Lower Clock Frequencies It's poseble to operate the MAX'76 at clock ratos up to 4Hz (aM or the military vorson) and down to ToOKH2 (orboth the commercialand military devices). The wer Clock imi i necessary because of tho mternal TH (crew ts cr00p. Connection to Standard Serial Interfaces The MAX176 serial interlace is fully compatible with SPL land Nerowire stancara! sera interfaces Common i plemertations of thase interfaces im microprecessors {uPs) limit ne MAX 1765 ‘rvoughaut fate. the WP sry ‘Sant keep up wih the seta dala steam. The Motorola {GSPI imtertace can nandlo tre MAKI76's 250keps ‘conversion rate. SCK from the MCEBHC 16 (shown 1s Figure 7) can operate athe MAXI T's Mle maxsmum clock rate. (Output Coding and Transfer Function Data ouiput fom the MAX%76 ia in 14os-comploment format The frst bt appearing at DATA is always "igh, ‘ollowed by the 12 data a's rveried most sigh flea i (ASB) fest 0 for postive analog inputs. 1 for negative followed by the remaining Peninverted 11 data Bis) Figure & snows the MAX176 nominal vanser function Code vanstions occu ralvay between successive inte ‘ger LSB vakies: one LSB = TOVMA096 ~ 2 4am Applications Information Offset and Full-Scale Adjustment In appications were the offset and tul-seale ranges havo o be adjusted for the ADC. use Figure 9 ercut This circu allows. adjustment of botn the offset and fulkseale (gain) eros. Adust the offsot fest. Apaly MAXIM gare 7 MARTTE Connected 9 OSA inetace V2LSB (1.22mV) al the analog input and adlust he mpilie’s olfeat unt ne da) output code changes between 0000 0000 0000 ansta000 000.0001 Changes: inthe ¥5Y supply alfect ho offset adjustment shanty Signiicant supply vanaton is expected, comect a rele fence 19 FS m place of he ¥5V suRpy To adjust the negative fullscale range, apply -FS + 112138 -2 499394, remembering he ampilier hasa gain of appronmately 2) at the analog input. and adjust RO luni Ihe output code changes between 1000 0000 0000 ‘and 1000 0000 0001. Once this adlustment ss made, re Positive ful-scale reading wil be cictated by te nlogra Foninearity (INL) specication thus, eacsng mal be no Ture’ away rom the optimal value than the maxi am INL spoestcaton, Te value ol potentiometer RS can be increased inorder tadecrease ne cxcuts current eansumpton However increasing tis resstorvaise decreases tne adjustment sensitiily when nthe mide range pat AS, andcauses felatvely large changes mn te op amp's output when al ‘thor endo he pot range. Adding a votage divider atthe noninvering input allows ‘wider input volage range. See the Driving the Analog Input section for eeommendes op aps forts ereut Figure 10 shows an alemative inverting contguration for ‘gan and ate: agustment ‘Serial-to-Parallel Data Conversion Figure 11a shows a MAXI76 wih a senal-to parallel converter The eralog put is rlerred 0 signal round lathe MAXI76 GND pin The paralel cata outputs are Updated at the conver sian signa’s rising edge. See Figure 116 for tne cout ting,MAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference te Ba a amex : Figs 8 MAXI 76 Transtr Funcion Figure 10 ering Gee and Fal Sate Aastra Faue 8 Nonvaring Ot an Ful Scale Aaron This cutis configueea ta operatein continuous-conver sion mode. However, may ba modiied for burst mode ‘perabon by eantoling the sit eqistor RCKinpurs uth f'signal other han convert start When cortinuns-con Version mode ig used. convert star MUS! go nigh atthe ‘tn ang clock edge to prevert siting of data past he shit register outputs shown, convent star's sng eoge latches te data thathas been seriall loaded nto the two TAHCS96 shit wegsters, Clock Frequency is estreled because othe clock to-data delay (see Electrical Char acteristics); the correct data mus be presert at me SER pin when clack rsing edges strobe the data nto the sv fegisters, The clack Fequency is nus imted to 3 3Mb2 for the Commerc al version of the MAKIT6, unless the (GocK sigral to He shi regstrs is delayed or invert This limtation also accounts or the 20ns shiiweqster setup time Note that for clock fequersces above 2iguin2, och corversen requres 19 clock cycles or more to alow sufficient TIM acquision ta. 18 oF 16 ‘lack pulses ooeut between each convert start pulee. ts ‘orcut sil function, but the data at the shit eoqster {uiputsis shited up one wo postions, respectively. so ‘hal the MSE appears athe top shit 69 stor OE oF OF ‘ouput Figure 11 Hustates the timing "or ths Shit re. ister crout, imSerial-Output, 250ksps 12-Bit ADC with T/H and Reference MAXIM —— 9ZIXUNWMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Figure 12 3 vie taco to Paral Pot Using Trev On In que 12's circu, the clack and conver star signals fare generated by an |CMT240 tmerieonverter, alowng Stana-alone MAX176 operation. The ICM7240 provides convert start pulse ‘or every 16 clock cycles {Genovates. Dua 0 he ICM7240' uope Iequency bmi this circus clock kequency is 1MH2 maximum. F CON. VSI capactvely leaded wih greater than BODF. Ine maximum allowable conver sia ise-ime spec icaton might be exceeded Using a logic bute ber TOM7240 and CONVST of the MAX176 ele problem Check mat nane of he tmng eharacterstics fare violated wren longo ise irmes occur due 1 capac. tive load ng o! CONVST or CLOCK ‘MAX176 with Opto-tsolators Transcucer outputs often require electrical isolation to separate thecontiololecronics Homnazarcous electrical ondiiens, pronde noise muy. oF Bridge large Ol ferences nground poteniaTeoiaton amputees ypcally qo sed for accompishing ths ae expensive. In ct ‘rere fe signals evertualy conver to a cal orm Its costaffecve to soa the nput usng opto solsers Inasorialdaialnk The MAXI76is deal nthsagpeaton ‘because lugs both TM ampiber and voltage rete fence, and because ois ow power consumption Figure 13a), The ADC resis are fansmiied across a 1S00¥ 'solaion barter provided by three 6N136 opto-sclators, Nate that isolated power musi be provided 19 the cor verter ang the isolated side of the opto-solators TaNosas von slate shi registers are uses to cons 12-bit parallel daia output (For those who preter oven Greater space savings and do not need a TH, Maxir's NUOCI7T combines the MAX:70.thres opto soiatore joad resisiors ma 16-pn DIP package) Figure 1b shows tne timing diagram fo thisanpication Conversion speed limited By ihe delay though the opto-solators With a 140kH2 ccck, conversion lime i ‘oon maximSerial-Output, 250ksps 12-Bit ADC with T/H and Reference 9LLXVIN MAXIM - "MAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Inthe eteut. the 74HC04 invorters must sink the curtent flowing through the opio‘solators. However, maxima ‘vol for these pars 's spectieg for ghter sink curents I the 74HCD4 output resistance is calcuated by avidng VoL max by the sink current used for ths specication {unssresistance svaid up to about 20mA of ark cuter), the resuting vollage can be caleulaled whan the ea ssnks these higher curenis. The same procedure can be ppled to the MAXI76 DATA output - the calculates ‘maximum resstance (2500) 5 vale up to 10mA of sink curent The rise ime of the signal applied to the MAKI76's CONST pin muct be less than 100% (see Electrical Characters), Because thas an oper-calector ou pul. the "92 ime of CONVST's optosoiatoris function fis pulp resistor and any stray eapactance. Min ize this say capacitance 10 ensure a ‘ast enough ise [Aroher consideration is the delays through this circuit ue [pemaniy tote optoseolalors. The arges! dolay between ‘put clock and the appearance of cata atthe lower si tagisar® SER pin. I's caugod by deay tough Me 7aHCOs, te MAXI76s Cockto-dala doky (see Fectical CCharactensics) and te delay tom twooptorsditors. This ‘olay most less than one loc pered fy he setup tine ff the 74HC596), and # determines he fastest allowable ‘lock speed for the creut Filly, noise pickup on the relativey slow opto-counler varsilons can cause false tiggerng atthe converters edge-senstive CONVST npu To avoiding prebiom set the tang edge af stant (aling ecge of carver sian) %0 ‘aceur wen the CONUST input ignares vansitens (© betore clock’s 130 faling edge). Slats faling edge Wiggers the nox convereon. and also causes the pre ‘us conversions resus to appear al the paralel data outputs Physical Layout For best system perlormance, use printea ercut boaras far tho MAXI76 - witewrap Doatds are rot recom mended, The beardlayout hau ensure thal Gia ane analog signa Ines atekept separate, andtnatdigtalines {nat pass undeeneat he MAX T6 package Grounding Figure 14 shows tne racammnanded systom ground con- nections. A sngle-pont analog STAR ground sould be established athe MAXI76 GND pin, Allanaiog-creutry [rounds sould be connected o this STAR grouna. The {round vetuen vo the power supply fom STAR ground Shaua be low impedance lor nose-ee operation. Dig 2 msn cme ET roarurtam aos suPy Figure ta Power Sippy Grounding talorcutry grounds must be connected to the Agia supply common. Al ground pins of the smalloutine version of the MAXI7B should connect 10 the STAR groune Power-Supply Bypassing The MAXI76's high-speed comparator ts sonsiive 10 high-requency nasesnthe Vop ane Vss power supplies Byoass these Supplies tothe analog STAR qrour with IWF and 1O,F capacitors wi minimum lead length or supply.naigo Yojecton. I the +SV power Supply 1 very noisy, connect small resistor (1010 to fit external reise Figura 14), Internal Voltage Reference The MAXITG has an onvchip reference with a bulfered ane temperature-compensated uriec-zener diode, lasertnmmed to “SV 40.4% I oufout is comected 16 the VREF pn and algo tives the mternal DAC. This Output can be used as a relerence voliage source for fner components, andl can sik up to Sma Decouple VREF with alow ESR 10yF capacitor in parallel vath a O.1NF capacitor Driving the Analog Input ‘Te input signal connections to AIN and GND should tbo as short at possible fo minimize nose pickup Ihe leads must be long, use sheided cables The ADC ‘analog input fargo 's nominaly *5¥. Howover, the {3nalog input can Be ctven to =15V with no damace To the eevee maximSerial-Output, 250ksps 12-Bit ADC Because the MAX176 includes a TM, the chive require ments ofan op amp connected AN a ss etical than these fora successive-approximation ADC without 2'T/M" The ampli, however must provide cart wth fn ampitude dependenton to sgralievel al AIN(Figue 2), Ako, te ample’ Dandwadh shouldbe sullen to hanale the iequerey of he sora applied to The MAXEOD and OPO7 wore wel at lower equencies. For Iigherrequency operation. the MAX#27 and OP27 ate sulable choices. The alloned input froquercy range is ited by te 250ksps same rae of he MAKA7E. Thus, tha: maxcmum sinusoal input frequency allowed 16 Zeit. Higher roqaoncy signals cause aliasing BOD. lems uniese undersamping fezhniques are used Dynamic Performance egrepees sarping capably and 250KH%2 thought rake the MAX'76 dba for widebare s.gralafocess ng ‘To suppor these and olnertelated appicatons, Fast FunerTranstom (FFT) fest techniques re used to guar antoe the ADC's dyramc frequency response, cistortion nd noise athe fated thoughout Speciicaly. ts ‘oles apalyig alow astorton sine wave tothe AD! Tnput an tecotcing the agal cowerson Faults ft & speciied im. The datas then analyzed using an FET ‘algorthm which determines ts spectra content. Conver Son ertors ae hen seen as spectra elements outside ne fundamental np requency. Figure 19 shows an FFT plot AADC have tractonaly been evaluated by specications Such a8 zero and ‘ullsealo oor inegtal nenineariy INL) an liferestialnonineanty (ONL). Such parame terse wel} accepted tr spacing peonance mth DG and siowy varying signals, bul are less useiu in signalprocessing appicatone wirere Ihe ADC's pact tn he system tanstrlungten iste man concern Tre sigatieance of various OC ators does nt tansiate wel tothe dynam cate, 9 diferent tests are requred ‘Signal-to-Noise Ratio and Effective Number of Bits ‘The sgnalto-nolse plus distarion rato (SAN + D) isthe atioof the landamentalinpiarequency's RMS amide {othe RMS ampltude ofa other AD cutout signals. he cuiputbendisimitedtoftequercies aboveDC and below ‘ne-hal ine AD sample (converson) rate. This includes ‘lslortion ae well as noise components Maxim with T/H and Reference ‘Tne tneoctical minimum AID nose s cause by quantize lion ettar and ig'a drect result ofthe ADC's resolution SNR = (602N « 1 76}08, where Ns fe numer ol bis Dl resolution. A pertect 12:bit ADC can. therefore, dono better than Peas, By tanspesing the equation that convents resolution 10 SNA. we can, fom tha measured SHR, celetrine the flective resolution, or eflecive ruber of Bis, the ADC provides: N= (SNR 1 76)8 02. Total Harmonic Distortion Total harmonic distortion she aio the RMS sum ofa harmonies of the inp signal (in the Frequency band labove DC and below ona-hal the sample rate) to The funcamental tel This sexpresced ae We? VST WaT Vn? ys ‘where V1 is the fundamental IMS apace and Veo VN {re the ampltudes of he 2nd through Nth harmonies, Peak Harmonic or Spurious Noise Peak harmonic (or spurious) noise isthe ratio of tne fundamental BMS amplitude to re amplitude ofthe ret largest special companent(nine requency band above [DC and below one-hall the sample rte)" Usualy ns peak occurs at same harmonic ofthe input frequency Buri the ADC is exceptional near itmay occu” only at random peak nthe ADC's notge Hoo! THO = 20109 soa Figo 16. WANIPEFFT Pal 0 9ZLEXUWMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Ordering Information (continued) PART TEMP. RANGE PrepacKace EREOR TOOTTEAEPA_40Cto 86 ORE DP v2 Chip Topography maxim