54

FPGA controlled Sinewave Inverter with RMS control and THD minimisation
Avilesh Pranish 2480685

The University of Auckland

Department of Electrical and Computer Engineering

Part IV Project Report

FPGA controlled Sinewave Inverter with
RMS control and THD minimisation

By

Avilesh Pranish
2480685
Project Group 54

Project Supervisor Mr. Nihal Kularatna
Second Supervisor Mr. Abbas Bigdeli

Project Partner Mr. Andrew Vareed
Avilesh Pranish 2480685 2
Declaration of Originality

This report is my own unaided work and was not copied from nor written in
collaboration with any other person.

Signed: _______________________________________
Acknowledgements

I would like to acknowledge the following people for their immense contribution
during the course of this project

Mr. Nihal Kularatna, Project Supervisor,
for his in-depth knowledge of power electronics and digital systems; and
motivating us in times of great despair.

Mr. Abbas Bigdeli, 2
nd
Supervisor,
for his assistance in the digital design of the project and quick response to
all our questions and requests for FPGA development boards.

Mr. Grant Sargent, Technical Manager,
for his valuable technical assistance with oscilloscopes and digital
equipment.

Mr. Andrew Vareed, Project Partner,
for his understanding and hard work throughout this project.

My Family
for their support and understanding throughout this challenging and
demanding period.

Abstract

The drop in cost of digital control devices such as Field Programmable Gate Array
(FPGA) and Digital Signal Processing (DSP) device has led to commercially
attractive means of developing low component count, digitally controlled low power
inverters. .Inverters are devices which convert DC to AC voltage, thus being an
attractive means of energy during power failures, where a DC source such as a 12V
battery can be used in the conversion process to 230V
rms
. However, the presence of a
load causes a voltage drop and waveform distortion(harmonics) leading to poor
performance and system degradation.

Thus, a method of control must be established which is namely the form of RMS
control or Voltage regulation to ensure that the voltage does not drop, and Total
Harmonic Distortion minimisation, which ensures the output waveform is a clean
signal, where the
waveform distortion is at a minimum.

This report outlines the development of a Sinewave Inverter controlled by an FPGA,
where algorithms used in control are described in detail. The results of
experimentation and testing of the Individual modules are described. The project led
to the development of a push pull Inverter Scheme with a FLEX 10K
EPF10K70RC240-4
found on the UP2 development board used as a proof concept FPGA control device.
The FPGA device was used to drive the power stage by PWM signals and an analysis
of the output via a feedback was used to develop algorithms to manipulate the PWM
signal for control.

Voltage regulation was achieved, however due to time constraints only the
relationship between THD and Pulse Width through analysis in the frequency domain
was established. The THD calculation focussed on utilisation of fundamental and the
average RMS values to work out the degree of harmonic distortion.

Table of Contents

1.0 Introduction..............................................................................................................6
1.1 Objectives ............................................................................................................6
1.2 Design Specifications...........................................................................................7
1.3 Division of Tasks .................................................................................................7
2.0 Background..............................................................................................................8
2.1 Inverters ...............................................................................................................8
2.2 Uninterrupted Power Systems..............................................................................8
3.0 Overview of the System...........................................................................................9
4.0 Digital Design ........................................................................................................10
4.1 FPGA Utilised in Design ...................................................................................10
4.2 Pulse Width Modulation ....................................................................................10
4.21 Overview......................................................................................................10
4.22 PWM Generation Algorithm........................................................................11
4.23 PWM Timing Algorithm..............................................................................12
4.24 PWM Ratios.................................................................................................12
4.3 Total RMS Calculation ......................................................................................12
4.31 Overview......................................................................................................12
4.32 RMS Template Matching Algorithm...........................................................13
4.33 Considerations in the Development of the Total RMS Block .....................13
4.34 RMS Resource Use......................................................................................14
4.35 RMS Algorithm Flowchart ..........................................................................15
4.4 Pure Sine Wave Template..................................................................................16
4.5 Zero Crossing Algorithms..................................................................................16
4.51 Overview......................................................................................................16
4.52 Zero Crossing Algorithm.............................................................................17
4.6 Total Harmonic Distortion (THD) .....................................................................18
4.61 THD Calculation..........................................................................................18
4.62 Fundamental RMS Calculation....................................................................18
4.63 Real Number Representation.......................................................................19
4.64 Fundamental RMS calculation.....................................................................19
4.65 Simulated Results for Fundamental RMS Calculation................................20
4.67 Fundamental RMS Resource Usage ............................................................20
4.68 Total Harmonic Distortion Final Calculation ..............................................20
4.7 Extra Functionality.............................................................................................21
4.71 Safety On and Off Push Buttons..................................................................21
4.72 Status LED Sequence...................................................................................22
4.73 Temperature Protection................................................................................22
5.0 Overall Digital Design Flowchart ..........................................................................23
6.0 Power Stage Design ...............................................................................................24
6.1 Power Stage .......................................................................................................24
6.2 Half Bridge Driver .............................................................................................24
6.3 MOSFET DRIVER MC34152........................................................................24
6.4 Push-Pull Inverter ..............................................................................................24
6.5 Power Filter........................................................................................................25
6.6 Voltage Sampler.................................................................................................25
6.7 Analogue-to-Digital Conversion........................................................................25
7.0 Results23
7.1 Test Equipment ..................................................................................................26
7.2 Voltage Regulation ............................................................................................26
7.3 Total Harmonic Distortion.................................................................................28
7.4 Output Waveform from Filter............................................................................30
7.5 Inverter Efficiency .............................................................................................30
8.0 Future Improvements.29
9.0 Conclusions............................................................................................................32
10.0 References............................................................................................................33
11.0 Appendices...........................................................................................................34
11.1 Appendix A Discrete Fourier Transform......................................................35
11.2 Appendix B Prototype Photos.......................................................................37
11.3 Appendix C FPGA Modules.........................................................................38
1.0 Introduction

This report outlines the design of a Sine wave Inverter and the utilisation of an
FPGA as a control device to reduce Total Harmonic Distortion and to control the
RMS value of the output waveform. The report details the digital design aspect of the
project and presents the laboratory results of the prototype and the future
improvements of the design.

Section 2 outlines the background of on Inverters, the different schemes and the
functionality.

Section 3 gives the overview of the system and details the function of the individual
modules of the overall system.

Section 4 describes in detail the digital design aspect of the project, outlining the
Algorithms, tables and simulation results.

Section 5 describes the overall digital design in the form of a flowchart, outlining the
processes involved in calculation and control.

Section 6 gives a summary of the Power Stage design.

Section 7 presents the results of laboratory tests of the Individual modules and the
graphs outlining the control relationship between Pulse Width and the respective
control.

Section 8 and 9 present the conclusions and possible future improvements to the
project.

1.1 Objectives

To develop a prototype inverter that has the capacity to supply power outputs
in the order of 200VA with an FPGA controlled -system.

To implement algorithms to calculate accurately the Root Mean Square (RMS)
and Total Harmonic Distortion (THD) of the Inverter output.

To regulate the RMS output voltage and to minimise the total harmonic
distortion, to optimise hardware resources on the FPGA.

To give recommendations on further improvements of the system.

1.2 Design Specifications

Output Voltage: 230 V
RMS

Input Voltage: 12-15 V
DC

Maximum Input Current: 16.7 A
DC

Maximum Output Current: 0.87 A
AC

Power Output: 200 VA

1.3 Division of Tasks

As dictated by the nature of the project and distinction between the power stage and
the control stage, the tasks were categorised into Digital design and the Power Stage
design. The Power filter and Voltage sampler stages were used from previous
projects as advised by the Supervisor.

The two design modules were developed in parallel and tested in individual modules
for functionality. After the testing phase of the individual modules, the focus had been
on integration and functionality of the system on the whole.

Therefore, due to the nature of the task undertaken, the focus of this report is on the
digital design of the project.
2.0 Background

2.1 Inverters

Electricity as an energy source allows conversion between forms[11]. The two main
forms of Electricity are Alternating Current, AC, and Direct current, DC. These forms
are utilised by Power Converters to convert between the two forms and also to step up
the energy level. The common types of Power Converters are namely DC to DC, AC
to AC, which namely convert levels, either step up or step down converters; and AC
to DC, DC to AC, which converts the form of energy as well.

Power Inverters fall into the DC to AC category; their major applications are in
Emergency Power supplies as a result of situations such as Power failures[11]. The
DC source is in the form of a battery. The application name termed to this form of
Power Converters is Uninterrupted Power Supplies; and is commonly referred to as
UPS.

However, due to power quality problems associated with Inverters namely in the form
of Harmonic distortion and Voltage regulation, the need for a control device arises in
the Inverter Design. The reduction in price of Digital Signal Processing chips (DSP)
and Field Programmable Gate Arrays (FPGA) has led to the consideration of these
devices as Control for the Inverters.

This project aims to utilise an FPGA device to act as the control segment for inverter
system. The FPGA is utilised for the generation of the Pulse Width modulated signal
to drive the Mosfets in the Inverter and to carry out feedback operations to regulate
the voltage and to improve the wave shape, thereby reducing Harmonic distortion.

2.2 Uninterrupted Power Systems

There are mainly three types of Uninterrupted Power Supplies, UPS, which are
discussed in term in the paragraphs that follow

Off-line: are also termed standby or backup mode inverters. They are turned on
when a power failure is detected. The switching time of these devices are very
important, is one of the weak points, however they are cheaper than On-line
Inverters[11].

On-line UPS: is always connected to the load via a battery, the battery is charged
continuously via the mains power supply. This scheme is most preferred as the battery
is always charged, therefore utilised for critical applications[11].

Hybrid UPS: this scheme has the functionality of the On-line and Off-line schemes, at
normal periods it directs the mains power supply to the load while simultaneously
charging the battery by converting the mains supply power to DC power. During a
power failure, the battery voltage is converted to AC and supplied to the load. This
scheme has a quick response time and produces clean output[11].

3.0 Overview of the System

The essential components of the sinewave inverter system are shown in Figure 1
below. The Field Programmable Gate Array (FPGA) device is used to produce a train
of pulses corresponding to the required sinewaves energy at respective intervals by a
method called Pulse Width Modulation. The Power Stage driven by the train of pulses
is used to convert the 12V DC to 230V
rms
AC so as to drive the load of 200 watts.
However, the presence of the load and architecture of the power stage introduces
harmonics, which are unwanted frequency components and random noise into the
system, producing a sinewave of low quality, which is harmful to the hardware. Thus,
outlining the need for a feedback loop to act as a control mechanism to minimise
these unwanted terms.

Upon the need for such a mechanism analogue to digital conversion (ADC) device is
used to input digital samples to the FPGA. However, the output voltage from the
power stage is in the order of 230V
rms
, whereas the ADC has a voltage tolerance of 0-
5volts. Hence, a voltage sampler in the Isolator stage is used to reduce the output
voltage so as to allow processing by the ADC device.

The low pass filter is utilised to filter out signals above the tenth harmonic and also to
reduce the phenomenon of aliasing and to improve the accuracy of the ADC. The
method of control utilised by the FPGA is the adjustment of the train of pulses in
accordance to the Total Harmonic Distortion (THD) present in the output sinewave
from the Power stage. The calculation of the THD involves the computation of
average root mean square (RMS) of the output sinewave, obtained by method of
superposition as opposed to traditional multiply and accumulates techniques; and the
fundamental RMS calculation obtained by means of Discrete Fourier Transform.

Figure 3.1 shows the block diagram of the FPGA controlled Sinewave Inverter

4.0 Digital Design

4.1 FPGA Utilised in Design

The University Program UP2 Development Kit was used as a proof concept FPGA in
the digital design [3]. The kit features the FLEX 10K
EPF10K70 which has 3,744 logic

elements, 70,000 typical gate and a total of 18,432 Ram bits [1]. The resource usage
throughout the report is given as percentage on the basis of these values. The board
has on board clock of 25.175 MHz; two dual digit, seven segment displays,[3]
expansion slots all utilised in the system design to interface with other modules.
The two dual digits, seven segment displays [3] were programmed in manner to show
the overall status of the system.

4.2 Pulse Width Modulation

4.21 Overview

The pulse width modulation (PWM) technique was used to control the switching
action of Mosfets in the power stage. The PWM signal was to have a period of 50Hz
corresponding to the sinewaves period. A square wave of 50Hz was also generated so
as to control the inversion of the second half of the cycle of the sinewave in the Power
Stage. This was necessary as the FPGA is only capable of producing digital signals,
essentially a high and low signal.

The manner in which the pulses were generated was that the 50Hz sine wave was
categorised into sixteen different segments; the amplitude of the sinewave in that
segment was determined by the width of the PWM signal corresponding to that
segment. The amplitude for the negative regions of the sinewave was treated as the
same as the positive region due to its symmetry as the second half is inverted in the
Power Stage. The figure 4.2 on the next page shows the how the timing ratio of the
pulses was determined using the triangle waves. The PWM train of pulses was
composed of 16 distinct pulses, thus a triangle wave of 800Hz was used to calculate
the duty cycle of individual pulses[13]. This ratio which represented the sine wave
ratio then formed the basis of Lookup table which was used to regulate the voltage.

The duration of the pulses determine the amplitude of the output signal for that
respective interval. Thus, on the basis of this relationship, the collective duration of
the pulses can be used to control the RMS value and the THD value of the output
signal. However, the RMS and the THD of the output signal must be analysed and the
pulse duration must be varied accordingly to establish this control, these are discussed
in the sections that follow.

Figure 4.2 Generation of the PWM ratios using triangular waves [13]

4.22 PWM Generation Algorithm

Essentially, for this task a Modulo counter of 2048 was used as the period controller
of the PWM signal. This counter was triggered by the positive edge of clock and reset
to zero as the value of 2048 was achieved. Furthermore, as sixteen distinct pulses
were needed in the PWM signal, the counter was treated as sixteen distinct segments
of 128. Therefore, by setting a single bit output high or low with respect to the count
value, the duty cycle control was achieved. With this approach the duty cycle was in
the order of 0.8% control.

The square wave was generated using the same counter as during the testing phase of
the PWM and Square wave pulse, the use of different counter indexes led to latency
between pulses. Thus, as synchronisation is essential between the pulses to produce
the positive and negative halves of the Sine wave, a single counter index was used
namely 2048. The table below shows the resource usage of the two algorithms, the
PWM had a more complex code structure to cater for Lookup table pointers and more
distinct individual pulses in comparison to the Square wave, thus utilising more logic
cells.

Resource Usage Resource Usage
(Logic Cells) (%)

PWM generation 102 2 %
Square wave generation 27 0.7 %

Table 4.1 PWM Resource usage on the Flex10k70RC240-4 device

4.23 PWM Timing Algorithm

The clock frequency of the Flex10k70 FPGA device is 25.175MHz [1], whereas the
frequency of Sinewave is 50Hz. Thus, the FPGA clock must be divided in a manner
to accommodate this requirement without using a lot of hardware resources. For this
purpose two techniques were considered namely the use of Counters and in built
frequency dividers. Frequency divider however allows division in multiples of two, in
comparison to Counters, it does not save hardware resources significantly, as shown
by the table below, and thus counters were used as it is more accurate.

Resource Usage with Period achieved
PWM code (without Lookup tables) (Hz)
(Logic Cells)

Counter 65 50Hz
Frequency Dividers 62 49.4 Hz

Table 4.2 PWM Timing Resource Usage

4.24 PWM Ratios

The following duty cycles were used
as the Sine wave Ratio and the basis
for the regulation of Voltage.

Pulse 1 & 8 54.5%
Pulse 2 & 7 72.7%
Pulse 3 & 6 84.9%
Pulse 4 & 5 90.9 %

Figure 4.2 PWM pulses

4.3 Total RMS Calculation

4.31 Overview

The Root Mean Square of a discrete signal is given by the equation below [12]

|
.
|
\
|
=

=
N
n
n y
N
RMS
1
2
) (
1

where
N is the number of samples

This equation involves the use of two main operations namely the square root [4], and
the multiply and accumulate (MAC) operation. Both of these operations are very

resource demanding in digital design [2]. Therefore the template matching approach
is used as it does not involve the use of both these operations. The scheme is in
essence is an assignment of RMS value with respect to difference between the
amplitudes of a Pure Sine wave sample and the incoming wave sample value[2].

4.32 RMS Template Matching Algorithm

This approach involves the utilisation of Lookup Tables stored in the Read Only
Memory. A set of quantised values from the ADC for a full cycle of pure sine wave
of RMS 230V is stored in memory.

Using the principle of superposition, the RMS value is treated on a sample by sample
basis, upon detection of the zero crossing point of the incoming signal; the Average
RMS calculation is started. The deviation between each incoming sample and the
respective pure sine value is calculated. Essentially, if the incoming sample is greater
than the pure sine sample, it is said to have positive deviation and if it is smaller than
it is termed negatively deviated.

On the basis of this relationship, the RMS value is considered as varying linearly with
respect to the incoming samples deviation. Another lookup table is stored in the
ROM which outputs the RMS value associated with the deviation. In accordance to
the resolution of the ADC, which is eight bits, a total two hundred and fifty- five
deviation values are stored, taking into account the sign bit.

4.33 Considerations in the Development of the Total RMS Block

The Average RMS block is dependent on the deviation of the incoming sample point
from the Pure Sine wave value for that particular instant in time, however, in the
actual design of the block certain factors must be carefully considered. The main
stand off is between accuracy and hardware resource on the FPGA.

As the algorithm is based on the amplitude difference (deviation), consideration must
be given to use deviation in terms the nearest 8, 4, 2, 1. These values were considered
as division by these terms to achieve the Lookup Table Index would mean just a shift
by the respective power of two. The lower values such as produce a 2 and 1 produce
very accurate result by comparison, however, at the cost of more memory elements.
After thorough testing the deviation of 1 was used in the design. The table below
summarises the tests carried out. Thus, the deviation and the corresponding RMS
value is stored in a Lookup table. The table and the graph below, shows the accuracy
and deviation relationship.

Deviation Resource Usage in RMS Memory Average Error
Calculation Block (LEs) (%) (%)

8 350 (9.3 %) 1.4 % 6.8 %
4 372 (9.9 %) 2.7 % 3.7 %
2 370 (9.8%) 5.5 % 2.2 %
1 355 (9.4%) 11 % 0.2 %

Table 4.3: Accuracy vs. Resource Use

0
2
4
6
8
10
12
(%)
LE Memory Error
8
4
2
1
ELEMENT
DEVIATION
FPGA Resource Usage
8
4
2
1

Figure 4.3 Accuracy vs. Resource Use graph

The results in the table show the results obtained through simulation, the system was
tested by means of a lookup table which acted as the incoming quantised values,
taking into consideration the ADC resolution and voltage span.

Test Equations Actual Calculated using Error
Value Template Matching ( % )

) 2 (sin 2 230 t 230 230 0 %
)] 14 sin(
7
1
) 10 sin(
5
1
) 6 sin(
3
1
) 2 [sin( 2 230 t t t t + + +
248.94 249 0.2 %
)] 18 sin(
9
1
) 14 sin(
7
1
) 10 sin(
5
1
) 6 sin(
3
1
) 2 [sin( 2 230 t t t t t + + + +
250.25 250 0.09 %

Table 4.4: RMS system block test simulation results

4.34 RMS Resource Use

Resource Usage Memory Usage
(Logic Cells) (%)

Average RMS Block 495 (13 %) 12.2 %

Table 4.5 RMS Algorithm Resource Usage

4.35 RMS Algorithm Flowchart

ncoming
Data from
ADC
Average RMS Calculation
Zero Crossing Detection
Block
Enable signal flag from
Zero Crossing Detection
Vin
GND
Vref
B1
B8
Sign
ENB
A/D Converter
Signal from Voltage Sampler
No
Read Only Memory
Pure sine
wave
Template
LUT
ncoming sample value is
compared with sine wave
template and deviation is
calculated
yes
On the basis of deviation, the
RMS value for the respective
sample is read from LUT
RMS
Deviation
LUT
At the end of the each sample ,
Average RMS is updated
End of sampling period, Average
RMS is used for Regulation and
THD calculations

Figure 4.4 : Average RMS Process Flow

4.4 Pure Sine Wave Template

The Sine Wave Template is utilised for the Average RMS calculation block.
Essentially, as a sampling rate of 200s is utilised in the system, 100 samples points
are stored as a Lookup Table in the Read Only Memory. Furthermore, to save
hardware resources a quarter of the values can be stored and the remainder of the
samples can be worked out through symmetry. The Pure sine wave values were
calculated in Microsoft Excel taking into consideration the resolution and the output
from the voltage sampler stage.

4.5 Zero Crossing Algorithms

4.51 Overview

The RMS calculation is based on the deviation of an incoming sample from a pure
sine wave sample for that instant in time. For this reason a full cycle of pure sine
wave sample values are stored in ROM. However, the incoming wave and the pure
sine must be synchronised to reduce erroneous calculations as shown in figure 3,
where a phase difference between the waves is present. A method of achieving this
synchronous is to find the zero crossing point of the incoming wave as the pure sine
wave sample values begin from the zero crossing point as well.

Figure 4.5 : The need for the zero crossing algorithm

.

(Logic Cells) (%)

Zero Crossing Block 132 4 %

Table 4.6 Zero Crossing Algorithm Resource Usage

4.52 Zero Crossing Algorithm

Figure 4.6 - Zero Crossing Algorithm Flowchart

The algorithm for the zero crossing point detection involves the use of two registers,
to store the values of the previous and current samples respectively. The Lpm_FIFO
megafuntion is utilised to act as a queue to store the current sample and output it upon
receiving the next incoming sample. A comparison between the registers is carried out
to check for the change in the sign bit, essentially from negative to positive, as
described in the flowchart. The figure below illustrates how the waves should be from
a calculation perspective both starting from zero. The Zero Crossing block is the
interface with the ADC as it receives the digital values. Thus, a counter is used to
synchronize the incoming at a sampling rate of 200us. Moreover, a clock was needed
for the operation of the ADC device in free running mode which was in the order of
640 kHz. The table below shows the resource usage for the Zero Crossing Block

4.6 Total Harmonic Distortion (THD)

4.61 THD Calculation

The Total Harmonic distortion is a means of measuring the distortion present in the
signal due to the new frequencies introduced into the signal by the power stage and
the load. These frequencies occur in multiples of the frequency of the input signal, for
instance a 60Hz signal will have harmonics at frequencies 120Hz, 180Hz, 240Hz and
continues in this manner. Essentially, is a measure of the quality of the shape of the
output from the Power Stage.

The Total Harmonic Distortion can calculated using the formula [8]

% 100 1 %
2

|
|
.
|
\
|
=
fund
total
RMS
RMS
THD

where

fund
RMS - fundamental RMS component

total
RMS - total RMS value of the signal

The
total
RMS value of the signal is calculated as described in section 3.3, however the
fundamental component is calculated as described in the algorithm described in the
next subsection.

4.62 Fundamental RMS Calculation

The fundamental RMS is the only component that is required by the THD formula,
thus this can be achieved by using the Discrete Fourier Transform (DFT). The
derivation of the formula is discussed in Appendix A.

Resolving this equation into terms of complex terms [5]

(
(
(
(
(
(
(
(
(
(
(
+ + =
8
7
6
5
4
3
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
1 ) 1 ( X
x
x
x
x
x
x
x
x
i i i i i i

Separating the Real and Imaginary terms [5]

8 6 5 4 1 Real
2
1
2
1
2
1
2
1
) 1 ( x x x x x X + + =

8 7 6 4 3 2 Imaginary
2
1
2
1
2
1
2
1
) 1 ( x x x x x x X + + =

The addition of the magnitude of the real and imaginary terms gives the square of the
magnitude of the fundamental component required by the THD calculation.[5]

4.63 Real Number Representation

The calculation for the fundamental RMS has a
2
1
term which has to multiplied by a
power of 2 as real numbers cannot be synthesised in hardware. Hence, the decimal
value of
2
1
which is namely, 0.707106, rounded to six decimal places, was multiplied
by a power of 2 and values achieved were tested in the Fundamental calculation block
for accuracy. The value decimal value of 45 was chosen as it produced fairly accurate
results. The value of 45 was achieved by multiplying the decimal value of
2
1
by 64,
which is an equivalent of a shift to the left by 6 in binary. Therefore, to balance the
equation, the non
2
1
coefficient terms were shifted to the left, thus allowing the
calculation of the fundamental RMS component.

4.64 Fundamental RMS calculation

For this calculation, the terms which did not have
2
1
were shifted to the left by 6 to
balance the equations. Two Adders were used, namely for the Real and Imaginary
terms. Three distinct sets were utilised in the calculation and the average of the closest
two was taken. A constant Multiplier was also utilised for multiplication with the
2
1

term which when shifted left represented the decimal value of 45.

The figures on the next page show some of the simulated results.

2
Fund.Img
2
Fund.Real
2
l Fundamenta
RMS RMS RMS + =

4.65 Simulated Results for Fundamental RMS Calculation

Test Equations Calculated Error
values ( % )

231.07 0.43 %

232.25 0.97 %

231.43 0.62 %

Table 4.7 : Calculations of the fundamental RMS component and error based on deviation from actual
fundamental of 230V

4.67 Fundamental RMS Resource Usage

(Logic Cells) ( % )

Fundamental RMS Block 1569 41 %

Table 4.8 : Resource Usage for Fundamental RMS calculation

4.68 Total Harmonic Distortion Final Calculation

Following the Fundamental RMS component calculation and the Average RMS
calculation as described in section 2.2, the Total Harmonic Distortion can be
calculated. Due to time constraints, this stage in the digital design could not be
reached, however, the relationship between harmonics and increasing the Pulse
Widths by a common ratio and the removal of individual pulses from the PWM
waveform was investigated, these are discussed in the Results section. The analysis of
this testing was done in the frequency domain. A control algorithm was not developed
but the analysis of the frequency domain and Individual Pulse relationship will lead to
an establishment of a control algorithm. On the basis of this Algorithm, the following
paragraphs outline a proposition to control THD.

) 2 (sin 2 230 t
)] 6 sin(
3
1
) 2 [sin( 2 230 t t +
)] 10 sin(
5
1
) 6 sin(
3
1
) 2 [sin( 2 230 t t t + +

The formula has a square root function, which is very resource demanding [4].
However, on the basis of the highest and lowest voltage subjected to the system and
their respective fundamental RMS values, a Lookup Table can be used to store the
Pulse Width Ratios based on the division of the Average and fundamental RMS
values.

However, as there would be two separate Algorithms trying to change the PWM
signal, the THD control could first be executed, upon completion of the THD control
within an acceptable range, flag could be set to allow the Voltage Regulation
Algorithm to regulate the voltage. The THD Algorithm executing first to work a ratio
at which the THD is at minimum is more suitable as change to the Pulse Width Ratio
after the Regulation Algorithm will affect the RMS value of the pulses.

Figure 4.7 Proposed THD control Algorithm

4.7 Extra Functionality

4.71 Safety On and Off Push Buttons

All the modules are driven by a counters for the purpose of delaying the on board
clock which runs at 25.175 MHz [7] and in the calculation blocks to use a clock set at
the sampling rate namely 200s. These modules also have allowance for a Clear
signals which sets the counters to 0, where no signals are generated from FPGA and
none of the Calculations are executed, thus sets the Power Stage at rest as well.

Consequently, the two Push Buttons on the UP2 development board [7], are
configured to set the Clear flag to logic 0 to start the system and the other Push
Button to set the Clear flag to logic 1 to start the system. The push buttons were
referred to us as Enable and Clear with respect to the modelled functionality of the
button. The block is used as a safety measure as the output is in the order of 150Vrms,
which is quite hazardous. Therefore, the default state of the system is at logic 0 to
keep the system at Off status.
THD
LookUp
Table
PWM
Control
Variables
% 100 1 %
2

|
|
.
|
\
|
=
fund
total
RMS
RMS
THD

The Push buttons are active low, therefore by default they are both set to logic 1 and
when pushed down and released go back to the logic 1. Thus, a separate module was
developed to set a signal to logic 0or logic 1 and maintain this state till the other
Push Button was pressed. This module utilised three logic elements on the
FLEX 10K
EPF10K70 device [7].

4.72 Status LED Sequence

The two dual digit, seven segment displays [7] on the development board are also
configured to correspond to the status of the system. On the basis of the whether the
system is ON or OFF, which corresponds to whether the Clear signal is high or low,
the displays are configured. When the system is at rest, at which the Clear flag is high,
the displays show a stationary figure eight each. However, as the Enable push button
is depressed setting the Clear flag low, a Chaser circuit is assumed by the two seven
segment displays.

Essentially, the LED module is a modelled as a Modulo counter, at the respective
states of the counter, the different segments of the seven segments are set to off and
on, corresponding to the state of the Chaser Circuit. At the Clear state, the counter is
set to zero. The Module is driven by a clock frequency set at human visibility, as the
aim of this module to show the user the status of the system. The module utilises 55
logic cells on the FLEX 10K
EPF10K70 device[7].

4.73 Temperature Protection

The role of this circuit is to prevent damage to the Power Stage as a result of
overheating. The temperature protection circuit produces logic 1, above the threshold
temperature, in accordance to this; the temperature input is via an input pin on the
expansion slot on the UP2 development board [7] to the FPGA. Upon receivable of
the Temperature input, the Clear flag is set high, causing the system into the Off
state. Moreover, the seven segment displays [7] show a flashing T each to show that
the system is experiencing overheating.

5.0 Overall Digital Design Flowchart

Figure 5.1 Overall digital design flowchart

6.0 Power Stage Design

Due to the nature of the project, the tasks were mainly allocated according to digital
design and Power Stage design. Thus, this report focuses on the digital design, the
Power Stage is discussed in brief for the purpose of completeness. The Power Stage
design is detailed in my colleagues report. The following section summarises the
power stage design undertaken by my colleague.

6.1 Power Stage

This module was designed to utilise the PWM signals from the FPGA stage to drive
the Mosfet switches. The output from the Power Stage is from the Mosfets driver that
is utilised to drive the respective switches to produce in each half a cycle of a Sine
wave. The PWM pulse train had to be amplified from 3.6V as it was a digital output
to 12V so as to drive the Integrated Circuits in the Power Stage.

6.2 Half Bridge Driver

The IR2151, which is a self-oscillating half-bridge MOSFET driver, was utilised to
produce two channels of the 50 Hz pulses which were out of phase with respect to
each other. The chip also has a dead band to prevent damage to the Mosfets.

6.3 MOSFET DRIVER MC34152

The MC34152 devices are drivers designed for Power Mosfets, which have a totem
pole outputs which capacity to source about 1.5A. Due, to the quick switching times,
low power consumption and low cost, these drivers were chosen.

6.4 Push-Pull Inverter

This was the inverter scheme utilised in the Power Stage. It is composed of a centre-
tapped transformer, the primary voltage in order of 15Vdc. Two Mosfet switches
control the voltage across the primary winding . The switches are operated with
respect to the PWM signals, on the basis of the positive and negative half of the Sine
wave.

The major advantage of this inverter scheme is that only one switch in series conducts
at a time, a critical factor when the DC input into the inverter is a low voltage battery
The down side of this scheme is its low efficiency ~ 75% and physical bulk .

6.5 Power Filter

The output from the Transformer is in the order of 50Hz, similar to the rectangular
pulses from the FPGA. The rectangular pulse have to be filtered to extract the 50 Hz
sine wave. A third order low pass passive filter was utilised for this purpose.
The filter was designed to supply 1A at 230 V
RMS
and a cut-off frequency of 800 Hz.
The 800 Hz cut-off frequency was namely the carrier frequency of the PWM control
signals that control the MOSFET switches. The output of the filter is shown in the
Results section.

6.6 Voltage Sampler

The voltage sampler is utilised for scaling the voltage from the output of the Power
Stage so it can be quantised by the ADC. The criteria is to ensure that the output
waveform is distortion free so as to prevent erroneous calculations in the FPGA. The
voltage sampler also has a isolator to prevent damage to ADC and FPGA, this
provided via an opto-coupler. The circuit diagram for the Voltage sampler is in the
Appendix. An Anti-Aliasing filter was used to ensure that the input into the ADC was
distortion free.

6.7 Analogue-to-Digital Conversion

The Analogue to Digital Converter device is used to quantise the values from a
continuous signal into discrete samples so it can be processed by the FPGA.
The ADC0804 analogue-to-digital converter was used in the design, it is a CMOS 8-
bit parallel successive approximation converter.

The parallel configuration ADC was chosen due to the parallelism of the FPGA . The
parallel device ensured that the last value was always on the output bus of the ADC.
The ADC was configured to operate in the Free Running Mode, to reduce control
complexity in the FPGA.

7.0 Results

7.1 Test Equipment

The following laboratory equipment was utilised in the testing phase of the system,
the functionality of each block was tested and relationships were investigated.

Power Supply - Topward Dual Tracking DC Power Supply

Oscilloscopes - Agilent 54621A 60MHz
Agilent 54622D 100MHz (Mixed Channel)

Multimeter - Agilent 344001A Digital multimeter

Load - 7, 15, 25, 40, 60, 75 and 100 Watt, 240V bulbs

7.2 Voltage Regulation

Voltage vs Load
0
0.2
0.4
0.6
0.8
1
1.2
0 20 40 60 80 100
Load (W)
N
o
m
i
n
a
l

V
o
l
t
a
g
e

(
V
)

Figure 7.1 : Voltage drop with Increasing Load

The graph above depicts the normalised fall in voltage on application of Load. The
voltage drops proportionally as the load is increased. This demonstrates the need for
regulation, which can be achieved by increasing the width of the PWM signals by a
common factor. The figure in the next page depicts the voltage after the regulation
process.

Regulated Voltage vs Load
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0 20 40 60 80
Load (Watts)
N
o
m
i
n
a
l

V
o
l
t
a
g
e

Figure 7.2 : Voltage after regulation

The voltage was regulated at a nominal value of 150Vrms due to the characteristics of
the Transformer as it did not step the voltage as expected from 12V to 230Vrms.The
step instead was from 12Vrms to 190Vrms.

Figure 3 shows the common ratio in which the pulses were increased to regulate the
voltage while maintaining the pure sine wave ratio. The percentage is based on the
increase of the last pulse (pulse 4) as it has the longest duration in the no load sine
wave ratio. The use of the bench top power supply also limits the magnitude of the
load regulated as it only the capacity to deliver 6 amperes of current in the parallel
mode. Hence, for this reason the maximum load of 75watts was regulated before the
last pulse reached its duty cycle limit of 100%.

Regulation Pulse Ratios
0
10
20
30
40
50
60
70
80
90
100
0 20 40 60 80
Load (Watts)
P
u
l
s
e

W
i
d
t
h

I
n
c
r
e
a
s
e

(
%
)

Figure 7.3 : Ratio of the increase of the PWM signal to achieve the regulation

7.3 Total Harmonic Distortion

THD vs Load
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80
Load (Watts)
%

T
H
D

Figure 7.4: THD with increasing Load

The graph above illustrates the increase in the percentage of Total Harmonic
Distortion (THD) with increasing load. The no load %THD is in the order of 17.3%,
mainly due to the filter design in the project.
The output after the filter stage produces a Sine wave in which the transition of each
PWM signal is obvious, producing a choppy effect which adds to the %THD.

The graph also clearly shows the increase in the harmonic content by load, hence
requiring the need for THD minimization in the control loop.

Therefore, to investigate the impact of increasing the PWM ratio by a common factor
was first investigated.

Total Harmonic Distortion
0
10
20
30
40
50
1 3 5 7 9
Nth Harmonic

M
a
g
n
i
t
u
d
e

(
D
b
)
27.3%
32%
33.5%
39.8%
46.8%
49.2%
58.6%
71.1%
90.6%
99%

Figure 7.5 Harmonic Spectrum with PWM sine wave ratio

The graph in the previous page is achieved by means of increasing the PWM pulses
proportionally while still maintaining the Sine wave ratio and observing the effect this
in the frequency domain. The pulses are increased proportionally until the 4
th
and 5
th

pulses reach a duty cycle of 100%. However, the frequency spectrum maintains a
general shape even though the pulses are increased proportionally. From a control
perspective, this does not give a significant relationship between harmonics and pulse
width.

However, as the individual sets of pulses are removed from the PWM train of pulses,
a more definite relationship is established.

The removal of the 1
st
and 8
th
pulse increases the 5
th
, 7
th
and 9
th
harmonics. While the
removal of the 2
nd
and the 7
th
; and the 3
rd
and 6
th
produces a decrease in the amplitude
of the 3
rd
harmonic and an increase in the other harmonics. Furthermore, the removal
of the 4
th
and 5
th
pulses causes a significant decrease in the amplitudes of the 5
th
, 7
th

and 9
th
harmonics.

Analysis in the frequency domain of a similar nature will lead to the development of a
scheme to reduce the %THD. At present due to time constraints only the impact of
individual pulses has been investigated.

-5
0
5
10
15
20
25
30
35
40
45
50
1 3 5 7 9
Nth Harmonic
A
m
p
l
i
t
u
d
e
(
D
b
)
Pulse 1
and 8
Pulse 2
and 7
Pulse 3
and 6
Pulse 4
and 5
Sine wave
Ratio

Figure 7.6: Frequency Spectrum showing effect of removing respective pulses from PWM train of
pulses

7.4 Output Waveform from Filter

Filter Output at 15V
-400
-300
-200
-100
0
100
200
300
400
-0.03 -0.02 -0.01 0 0.01 0.02 0.03
Time
V
o
l
t
a
g
e
Pure Sine
b

Figure 7.7 Output of the Sine wave Inverter from the Filter

The graph in figure 7.2 shows the filter output in comparison to a pure sine waveform.
Clearly, the actual output waveform has a sharp drop in the 2
nd
and 4
th
quarters of the
output waveform. This sharp drop is result of the characteristic of the filter design.
Furthermore, the filter must also be redesigned to remove ringing at the peak and
trough areas of the output waveform.

7.5 Inverter Efficiency

0
10
20
30
40
50
60
70
80
0 20 40 60 80
Load (Watts)
E
f
f
i
c
e
n
c
y

Figure 7.8 FPGA controlled Sine wave Inverter Efficiency

The figure above shows the efficiency of the Inverter designed. The efficiency lies in
the range of about 62-73%, which is typical of push pull inverter schemes.

Sampler Output
0
0.5
1
1.5
2
2.5
3
3.5
-0.03 -0.02 -0.01 0 0.01 0.02 0.03
Time (sec)
V
o
l
t
a
g
e

(
v
o
l
t
)
Output

Figure 7.9 Voltage Sampler Output with an application of a 150V
rms
sinusoidal from the Power Stage

ADC Sinusoidal Input
0
0.5
1
1.5
2
2.5
3
3.5
4
0 20 40 60 80 100 120
Sampled by Oscilloscope
V
o
l
t
a
g
e

(
v
o
l
t
)

Figure 7.10 The input pure sine waveform from the a signal generator

ADC Output
0
50
100
150
200
250
300
0 20 40 60 80 100 120
Sample Number
B
i
n
a
r
y

O
u
t
p
u
t

Figure 7.11 Sampled values captured by a 100Mhz mixed signal oscilloscope

The Agilent 54622D 100MHz (Mixed Channel) oscilloscope allowed input of digital
data. Using digital probes the functionality of the ADC was tested.

8.0 Future Improvements

A serial Analogue to Digital converter device can used in place of a parallel
device as it would reduce the cost significantly
The Zero Crossing Algorithm (Section 2) can be made more robust to deal
with the oscillations caused by harmonics. In place of comparison just made
between the current sample and previous sample, few more samples can be
used after the Zero Crossing point to ensure that the next samples are actually
increasing and not oscillating near zero.
A Graphical User Interface can be developed for debugging and showing the
status of the Inverter.
Further investigation on the THD and Pulse Width relationship is required to
develop a control Algorithm
More precision can introduced into the calculation of the average RMS value
and more samples can be used to improve accuracy of results
User designed Multiplication and Division modules can be developed as this
account a high hardware usage on the FPGA.

9.0 Conclusions

FPGA as a digital control device was found to be feasible in Sine wave
Inverter design.
Voltage regulation was achieved at a nominal value of 150V rms due to
limitations of the Transformer used in the system.
Load in the order of 75 Watts was regulated due to the limitation of the Bench
top power supply used as it had the capacity to deliver 6 Amperes of current.
Push pull inverter topology was designed and driven by PWM signals from the
FPGA.
Alternative methods of control Algorithms were utilised to minimise hardware
resources on the FPGA.
Relationship between pulse width and THD was investigated but a control
Algorithm was not developed due to time constraints.
Individual Modules have been completed and tested for functionality, however
due to time constraints, the control loop could not be integrated into the
system.
Appreciation for overall approach to a system design was achieved, in addition
to practical knowledge of oscilloscopes, software tools; signal processing,
computer systems and power electronics design were learnt.

10.0 References

[1] Altera Corporation. Flex 10k Embedded Programmable Logic Device Family
Data Sheet.http://www.altera.com/literature/ds/dsf10k.pdf, January 2003.

[2] Tsang, K.F. Peter. (2003). Field Programmable Gate Arrays Based Control
Loop for Sine Wave Inverters. The University of Auckland, Auckland, New
Zealand.

[3] Altera Corporation. University Program UP2 Development Kit Data Sheet
http://www.altera.com/literature/univ/upds.pdf, July 2003.

[4] Parhami B. Computer Arithmetic: Algorithms and Hardware Designs. Oxford
University Press,Inc, 2000.

[5] Elliot D.F. and Rao R. K. Fast Transforms : Algorithms, Analyses,
Applications. Academic Press, London, 1982.

[6] Arrillaga, J; Bradley D.A, and Bodger P.S. Power System Harmonics. John
Wiley & Sons Ltd, 1988.

[7] Vareed, A. (2004). FPGA based Sine Wave Inverter with RMS control and
THD minimisation. The University of Auckland, Auckland, New Zealand.

[8] Wakileh G.J. Power System Harmonics : Fundamentals, Analysis and Filter
Design, Springer, New York, 2001.

[9] Agilent Technologies. The Foundations of Signal Analysis Application Note
243 . Agilent Technologies, http://cp.literature.agilent.com/litweb/pdf/5952-
8898E.pdf, 2000.

[10] Cimbala. J. M. Fourier Transform, DFTs, and FFTs.
http://me.psu.edu/me82/learning/FFT/FFT.html, October 2003.

[11] Kularatna N. Power Electronics Design Handbook : Low-power components
and Applications. Newnes, Boston, 1998.

[12] de Silva D.I.M, Kularatna N. and Rathnayake. DSP-Based System Produces
Low Distortion Sinewaves for UPS Application. Pages 18 26, USA, May
2000. Power Electronics System Journal (PCIM).

[13] Mohan N., Undeland T. M., and Robbins W. P. Power electronic Converters,
Applications, and Design. John Wiley & Sons Inc., New York, second edition,
1995.

11.0 Appendices

11.1 Appendix A Discrete Fourier Transform

Discrete Fourier Transform Formula

The Discrete Fourier Transform of a discrete signal [10]

for k = 0, 1, 2, ..., N-1.
where
N = total number of samples taken
T = total sampling time
= time increment between samples =
N
T

f
s
= sampling frequency
= frequency increment for output
k = the kth harmonic frequency

The input to the DFT matrix is represented in vector form, which is essentially a data
sequence depending on the number of points, N, used in the calculations [5]

T
)] 1 ( ),..., 2 ( ), 1 ( ), 0 ( [ x = N x x x x

The output is given defined by vector

T
)] 1 ( ),..., 2 ( ), 1 ( ), 0 ( [ X = N X X X X

Therefore the DFT outputs for N = 8 is given by [5]

x ) (
8
1
X(7)
x ) (
8
1
X(2)
x ) (
8
1
X(1)
x ) (
8
1
X(0)
1 2 3 4 5 6 7 0
6 4 2 0 6 4 2 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
W W W W W W W W
W W W W W W W W
W W W W W W W W
W W W W W W W W
=
=
=
=

where
N j
e W
/ 2
=

However as only the fundamental value is needed for the THD calculation, thus the
calculation is reduced by a factor of N. Therefore, a simple matrix multiplication is
required as shown below.[5]
(
(
(
(
(
(
=
) 8 (
) 2 (
) 1 (
) 0 (
) (
8
1
X(1)
7 6 5 4 3 2 1 0
x
x
x
x
W W W W W W W W

where x is the input data sequence

For this reason the Discrete Fourier Transform is used as opposed to the Fast Fourier
Transform (FFT), as the interest of the Algorithm lies in the fundamental RMS
component.

Resolving this equation into terms of complex terms [2]

Separating the Real and Imaginary terms [2]

8 6 5 4 1 Real
2
1
2
1
2
1
2
1
) 1 ( x x x x x X + + =

8 7 6 4 3 2 Imaginary
2
1
2
1
2
1
2
1
) 1 ( x x x x x x X + + =

(
(
(
(
(
(
(
(
(
(
(
+ + =
8
7
6
5
4
3
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
1 ) 1 ( X
x
x
x
x
x
x
x
x
i i i i i i

11.2 Appendix B Prototype Photos

System Setup

Testing with Load

11.3 Appendix C FPGA Modules

The schematic shows the PWM block which consists of the LED block, PWM and
square wave generation blocks, the ON and OFF push button controls.

PWM simulation

Square Wave Simulation


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FPGA controlled Sinewave Inverter with RMS control and THD minimisation

Avilesh Pranish 2480685

EPF10K70 which has 3,744 logic

EPF10K70 device [7].

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