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(Download PDF) High Performance Computing 35Th International Conference Isc High Performance 2020 Frankfurt Main Germany June 22 25 2020 Proceedings Ponnuswamy Sadayappan Online Ebook All Chapter PDF
(Download PDF) High Performance Computing 35Th International Conference Isc High Performance 2020 Frankfurt Main Germany June 22 25 2020 Proceedings Ponnuswamy Sadayappan Online Ebook All Chapter PDF
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Ponnuswamy Sadayappan
Bradford L. Chamberlain
Guido Juckeland
Hatem Ltaief (Eds.)
LNCS 12151
High Performance
Computing
35th International Conference, ISC High Performance 2020
Frankfurt/Main, Germany, June 22–25, 2020
Proceedings
Lecture Notes in Computer Science 12151
Founding Editors
Gerhard Goos
Karlsruhe Institute of Technology, Karlsruhe, Germany
Juris Hartmanis
Cornell University, Ithaca, NY, USA
Bradford L. Chamberlain •
High Performance
Computing
35th International Conference, ISC High Performance 2020
Frankfurt/Main, Germany, June 22–25, 2020
Proceedings
123
Editors
Ponnuswamy Sadayappan Bradford L. Chamberlain
School of Computing Cray, a Hewlett Packard Enterprise Company
University of Utah Seattle, WA, USA
Salt Lake City, UT, USA
Hatem Ltaief
Guido Juckeland Extreme Computing Research Center
Helmholtz-Zentrum Dresden-Rossendorf King Abdullah University of Science
Dresden, Germany and Technology
Thuwal, Saudi Arabia
This Springer imprint is published by the registered company Springer Nature Switzerland AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
Preface
The Gauss Centre for Supercomputing sponsors the Gauss Award. This award is
assigned to the most outstanding paper in the field of scalable supercomputing and
went to:
We would like to express our gratitude to our colleagues for submitting papers to the
ISC-HPC scientific sessions, and the area chairs and members of the Technical Papers
Program Committee for organizing this year’s program.
Emerging Technologies
Guang Hao Low Microsoft, USA
Sriram Krishnamoorthy Pacific Northwest National Laboratory, USA
Mathias Soeken EPFL Lausanne, Switzerland
Robert Wille Johannes Kepler University Linz, Austria
HPC Algorithms
Anne Benoit ENS Lyon, France
Umit Catalyurek Georgia Institute of Technology, USA
Aurélien Cavelan University of Basel, Switzerland
Anshu Dubey Argonne National Laboratory, University of Chicago,
USA
Sascha Hunold TU Wien, Austria
Ananth Kalyanaraman Washington State University, USA
Kamer Kaya Sabancı University, Turkey
Hatem Ltaief KAUST, Saudi Arabia
Veronika Sonigo University of Franche-Comté, FEMTO-ST Institute,
France
Didem Unat Koç University, Turkey
Ana Lucia Varbanescu University of Amsterdam, The Netherlands
HPC Applications
Edouard Audit CEA, France
Xing Cai Simula Research Laboratory, Norway
Carlo Cavazzoni CINECA, Italy
Anne C. Elster University of Texas, USA, and Norwegian University
of Science and Technology (NTNU), Norway
Erwin Laure KTH, Sweden
Erik Lindahl SciLifeLab, Sweden
Hatem Ltaief KAUST, Saudi Arabia
A. Cristiano I. Malossi IBM Research, Switzerland
Organization ix
BoFs Committee
Marc Baboulin Université Paris-Saclay, France
Claudia Blaas-Schenner TU Wien, VSC Research Center, Austria
x Organization
Tutorials Committee
Damian Alvarez Forschungszentrum Jülich, Germany
Katie Antypas Lawrence Berkeley National Laboratory, USA
Rosa M. Badia Barcelona Supercomputing Center, Spain
Pavan Balaji Argonne National Laboratory, USA
Janine Bennett Sandia National Laboratories, USA
Jong Choi Oak Ridge National Laboratory, USA
Dan Ellsworth Colorado College, USA
Kevin Huck University of Oregon, USA
Mozhgan Kabiri Chimeh NVIDIA, UK
Michael O. Lam James Madison University, Lawrence Livermore
National Laboratory, USA
David Lecomber Arm, Arm Ltd., UK
Kelvin Li IBM, Canada
Simon McIntosh-Smith University of Bristol, UK
C. J. Newburn NVIDIA, USA
Dhabaleswar Panda Ohio State University, USA
Ojas Parekh Sandia National Laboratories, USA
Olga Pearce Lawrence Livermore National Laboratory, USA
Christian Plessl Paderborn University, Germany
Harald Servat Intel, Spain
Michela Taufer University of Tennessee, USA
Workshops Committee
Emmanuel Agullo Inria, France
Hartwig Anzt Karlsruhe Institute of Technology, Germany,
and University of Tennessee, USA
Richard Barrett Sandia National Laboratories, USA
Roy Campbell Department of Defense, USA
Florina Ciorba University of Basel, Switzerland
Anthony Danalis University of Tennessee, USA
Manuel F. Dolz Universitat Jaume I, Spain
Nick Forrington Arm, Arm Ltd., USA
Karl Fuerlinger Ludwig Maximilian University Munich (LMU),
Germany
Judit Gimenez Lucas Barcelona Supercomputing Center, Spain
Organization xiii
Proceedings Chairs
Guido Juckeland Helmholtz-Zentrum Dresden-Rossendorf (HZDR),
Germany
Hatem Ltaief KAUST, Saudi Arabia
Contents
Emerging Technologies
HPC Algorithms
HPC Applications
Sparse Linear Algebra on AMD and NVIDIA GPUs – The Race Is On . . . . . 309
Yuhsiang M. Tsai, Terry Cojean, and Hartwig Anzt
multiple clock cycles and is pipelined as well. DPU has shift-registers for meta-
data information that is needed in a later stage or at the end of the Lookup
Pipeline. When a key in the hash table is found equal to the input key and
the entry is valid, a matching flag is captured and stored into the metadata
shift-register.
Result Resolution Unit collects the metadata information and result from
the last mega-stage of Lookup Pipeline, and routes operations to their next hop.
For search operation, it generates the response based on whether a key exists or
not. When insert is performed, this unit also inspects the matching flag. If hash
table insert condition is satisfied, i.e. matching flag indicates the input key is
unique, it issues the operation to the Insert Pipeline with metadata information
such as hash index, slot ID, etc. Otherwise, it generates a response to application
indicating failure.
Each Hash Table Block has an Insert Pipeline. It is triggered when it receives
an operation along with the corresponding metadata information from Result
Resolution Unit or from another PE. It writes the new key-value pair and valid
information directly to its Hash Table Block. The last stage of Insert Pipeline
sends the update data to the next PE according to the rules of Inter-PE Dataflow,
which we will describe below.
Collision Handling Unit. To handle collision, we design our hash table entry
to have multiple slots. Each slot can be allocated to store one key-value pair.
One valid field is associated with each slot to indicate if this slot has valid data
or available for insertion. An operation is performed only when both the key
matches and validity of the slot.
In each PE, only DPU MHTB mega-stage has extra collision handling logic.
Other Hash Table Block mega-stage doesn’t need collision handling because colli-
sion, if any, has already been resolved by the PE which initiates insert operations.
Collision is handled by finding the first available slot to insert. We implement a
parallel collision handling unit, as shown in Fig. 6. That is: we examine all the
slots from a hash table entry at the same clock cycle. This collision handling
logic is an extension on top of the hit/miss detection logic that already presents
in each Hash Table Block. It has s parallel comparators to detect a matching key.
Fig. 6. Parallel collision handling with s slots per Entry. “Hit/Miss/Collision Handling
Logic” outputs the outcome of lookup, and slot ID for MHTB based on operation type.
FASTHash: FPGA-Based High Throughput Parallel Hash Table 13
The slot ID from this stage needs to be recorded into the shift-register because
this information is needed by the Insert Pipeline later on. Given our low collision
rate with H3 hash functions, we expect 2 to 4 slots per entry to be sufficient.
Therefore, it can produce slot ID for insert with O(1) latency.
In order to support perfect hashing with two levels of hash tables, another Hash-
ing Unit is added to each PE for the second level hash table. This Hashing Unit
is placed between the Hashing Unit for the first level hash table and the Data
Processing Unit. Inside this unit, we use a lookup table to store the hashing func-
tions for each entry in the first level hash table. Collision Handling Unit and
Inter-PE Dataflow are removed because they are designed for insert operations.
An error due to relaxed eventual consistency may occur when the following hold
simultaneously: (i) an insert request for a key u is received for the first time;
and (ii) another request of search or insert for the same key u is received within
pt0 + p + t0 cycles. Since, every clock cycle serves p requests, we can bound this
error by finding number of such issues within p2 t0 + p2 + pt0 requests in the
sequence of all requests. Note that it is possible to create large number of such
errors by having a new key inserted and searched in every clock cycle. However,
such cases are unusual in practical setting. Instead, we will assume that there is
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virtues of the “Elixir,” systematically purging the system of those
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CONCLUDING REMARKS.
1. The following table exhibits the ages of three hundred and twenty-six
females, at which they began to menstruate. It is furnished me by Mr. Robertson,
in the North of England Medical and Surgical Journal.
To this list may be added the case related by Madame Boivin, in her account of
a new case of abortion. The subject of this case commenced to menstruate at seven
years of age, and did so regularly after her tenth year.
2. We could record a number of instances where the menses were continued
much beyond their ordinary period, and where, after ceasing some time, they were
resumed with their accustomed regularity; but we shall limit our observations to
one case, and that because it is recent and well authenticated. This case is recorded
in the Ann. Univ. de Med. A female aged ninety-four continued to menstruate from
the fifty-third to the ninety-fourth year. Her relatives were remarkable for their
longevity; she is at present in perfect health.—American Journal of the Medical
Sciences for Feb. 1831.
3. Diaphoretic Powder.
38. Some German poet, whose name has escaped me, says,
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