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1.8.3.1 Sequential Flow
Sequential control flow describes the fundamental movement through a program. Each
instruction contained in the program is executed in sequence, one after another. A signifi-
cant amount of the total code in an application is evaluated and executed in sequential order,
although the individual sequences may be rather short. We capture that notion in the accom-
panying diagram in Figure 1.25, in the following CIC++ code fragment in Figure 1.26, and
in assembler code in Figure 1.27.

Initial

a= 10;
b= 20;
c =a+ b;
Final

Figure 1.25 Sequential Flow Figure 1.26 C / C++ Sequential Flow

MOVE R1, #AH; // puts 10- hex A- into R1


MOVE R2, #14H; JI puts 20 - hex 14 - into R2
,ADD R3, R1 . R2; If .computes R1 + R2 and puts result into R3

Figure 1.27 Assembler Sequential Flow


26 Chapter I The Hardware Side-Part I: An Jn1rod11ction

TI1e execution first assigns voJues lo sevcrnl variables and , then performs an arithmetic
operfttion ()fl the two variat,Jer,;.

·Decision Point J,8-1.l Branrh


A branching construct tenninatcs a sequentlal now of con wi th a decision oint. At such
a point. one of several alternate paths for continued execution is taken ba,icd on t e outcome
of a test on some condition. Graphically, such a construct is seen in Figure 1.28. The branch
Flgu~ 1.28
construct is used to implement an If else, .rwitch, or case statement.
The Branch Construct
The branch may be executed unconditionally, in which case the contents of the PC arc
f/dtt. ,11•l.can replaced by the effective address specified by the operand. Alternately, the branch may be taken
~ditionaJly based on lhe side effecle; of operations perfonned on data or on several different
kinds of comparisons between two variables such as equality, a greater than or Jess than rela-
tionship, a carry from an arithmetic operation, or a variable being equal to or not equal to zero.
/1111 ·, ...,- The conditional infonnation is temporarily held as a collection of bits in aft.a register
CNMfi"- co,k ~ or condition code register. The state of each bit in the register is evaluated and potent1a Jy
cb'1igect following the execution of every instruction. Figure 1.29 lists some of the possible
conditions that may be supported in a microprocessor.

E.lE 0perancf 1 Is gquaVnot fKIUa/ to 0perand2.


Z.HZ The rasuft of the operation Is zero/not zero.
GtGE - Opersnd1 Is greater thBn/gf8ater than or equal to 0perand2.
l.T.lE as.and1 Is less than/less than or equal to Operand2.
V The operation resulted in an ovarlJow-the result Is lat'ger than can be held In the destination.
C. NC The-operation produced a canyhJo cany.
N The result'of the operation i. negative.

Fipftl.29 Typical Condition Codes

_ _Branching alternatives that may be supP9rted in a particular microprocessor are given


10 Figure I .30. ·

F BRJabel uncondltlonal branch tQ the a ~ label


8E label, BNI; label
blanch to the lf)8Clfted label if the equal flag ta aet or not set
BZ label, 8NZ label
branch to t h e ~ label If the zero flag 1a eat or not set
8GTlabel
branch to the fP8Clfled label ff the greater then flag 18 Ht
IJ\I .label " branch to the spedftecf label If the OYerflow flag. la NJ
BC Jabef, BHC'label
branch to the specffled label If the carry flag la aet or not aet
,BNJabel
branch to the 8peclfled lebel If the negative flag la ...

flsure I.JO Typical Branching Instructions

The if-else construct is illustrated with the foll


1.3 l and with assembler code fragments in Figure t~~g•
CIC++ code fragment in Figure

_, If(•• b)
Clld•«

•1acure 1.31 C / C++ if-else


Construct
CMP R2. R1 ·. II _ compare the content$ of R1 and R2, wilsetthe equatffag
·.:BE $1· .· . . · ·.' It it the equal -~~g)~ set jump-to $1
'· . ' • '· , i:· .. '.:' · 11 ·_. '$1 js,a,labe(cteated bY compiler

, ,SUBR3 · R4 -R5 ·. ' ,-~ ':;}{)h.,J ;·<·:@mp~hercit ...and ptrt NJSufts in C


.··. BR$2 · . • , ·\ ;,;;,ti~~l~ ffl t~ by ~ ·,a'f)d~ut·tnult s inc
$1•'.:ADD'R3 :, R4 R5,: " ;:;: :;;;\L\,, .• ,,. / " ·

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Figure 1.32 Assembler if-else Construct


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Stack The addressing variations stem from the fact that one use of these instructions is tc
addres sing impleme nt stacks within memory. (!\ stack is a form of l~~!-in-first-out store wh ich
supports simple dynamic memor~ allocation , that is, memory allocation where the
address to be used to store a data' valu;is n~tkno wn at die time ttie program IS
cornplle d or assembledJ An example °would bea recurstve function, where the dept~.
of recursio n depends on the value of the argument~ stack is usually impleme nte'.'.
as a linear data structure which grows up (an ascending stack) or down (a descend-
ing stack) memory as data is added to it and shrinks back as data is removed. ...1.
stack pointer ho~ -~ e a~dr~s~ otjhe current top of th~ ~eJ!her by-pointing r •
the last valid data item pushed.. ....,._... .,... -- -
onto the stack (a full stack), or by
- .--..,..
vacant slot where the next data item will be placed (an empt}:'_ stack). \
--
pointing to th,

The above descripti on suggests that there are four variation; o~ a ; ta~k, repres~nt·
ing all the combinations of ascending and ·descending full and empty stacks. Th:
ARM multiple register transfer instructions support all four forms of stack:
• FuJl ascendin g: the stack grows up through increasing memory addresses and the
base regi ster points to the highest address containin g a valid item.
.,,,,- • Empty ascending: the stack grows up through increasing memory ad<lresse~ 3.nd
the base register points to the first empty location above the stack.
/ • Full descending: the stack grows down through decreasing memory addres~~s
and the base register points to the lowest address containing a valid item .
., • Empty descending: the stack grows down through decreasing memory addres.)C)
and the base register points to the first empty location below the stack.
C

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