Project 4: Layout design of CMOS circuits

Yuan-Ze University
Department oI Computer Science and Engineering
Copvright bv Rung-Bin Lin, 1999
All rights reserved
Purpose:
This project is to make students becoming Iamiliar with the commercial CAD tools
employed to perIorm Iully customized CMOS circuit layout.
Introduction:
Transistors are created by superimposing various layers oI transistor-Iorming
materials. The sizes oI geometric objects and interrelationship among the objects on
these layers (may be on the same layer) must satisIy some particular constraints such
that the Iabricated transistors can Iunctionally and electrically correct. The constraints
are usually collectively Iormulated as a set oI layout design rules. The purpose oI
layout (also called physical layout or physical design) is to arrange the transistor-
Iorming geometric objects under the constraints oI layout design rules such that the
Iabricated transistors can perIorm their speciIied Iunction. Layout design rules vary
Irom one process technology to another, thus when the same circuit design is realized
by two diIIerent processes, their layouts must be diIIerent.
In this project one is supposed to employ a Iully customized layout design Ilow based
on Cadence tool set to perIorm physical layout oI some basic circuits. (Cadence is a
CAD tool vendor that sells various kinds oI IC design CAD tools such as tools Ior
logic simulation and synthesis, layout design and veriIication, placement and routing,
etc. ) The Iully customized design Ilow is shown in Eigure 4.1. The layout design
process starts Irom the target speciIications. At this moment we have to set a target or
constraint respectively on area, timing and power. Eor example, when a 4-input AND
gate is designed, a target or constraint can be speciIied as Iollows:
(1). area is less than 80um

,
(2). power is less than 2 pico-Watt, and
(3). rise and Iall propagation delays are approximately 1.2 ns and output rise and Iall
times are approximately 0.6ns when input transition time is 0.5ns and output load
is 0.3pE.

Some other constraints about geometric shapes oI a layout may be speciIied. Once
this step is done, it then Iollows transistor circuit schematic design, carried out by
Cadence Composer. The transistor sizes oI p- and n-transistors must be speciIied such
that the desired timing/power target can be reached. Timing and power measurements
can be perIormed by Hspice circuit simulation. II timing and power do not meet the
speciIications, transistor sizes is tuned or circuit schematic is redesigned until the
speciIications are satisIied. Note that circuit simulation is also employed to check the
correctness oI Iunctionality oI a circuit.
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Eigure 4.1. The Iully customized layout design Ilow

Layout design commences once a circuit design is completed. It is carried out by

Cadence Layout Virtuoso Editor. At this moment, transistor-Iorming geometric
objects are sketched under the constraints oI layout design rules. The transistors are
drawn according to the speciIied transistor sizes. AIter layout is completed, layout
veriIication and circuit extraction are perIormed by Dracula tool set. Dracula includes
tools Ior layout design rule check (DRC), layout parasitic capacitance extraction
(LPE), layout parasitic resistance extraction (PRE), and layout versus schematic (LVS)
comparison, etc. DRC, LPE, and PRE are intuitively understandable. Note that LPE
also carries out circuit extraction. LVS is perIormed to ensure that the design
represented by circuit schematic is Iunctionally equivalent to the one represented by
physical layout. This step is very important since an error during LVS usually
indicates that there exists an error in schematics or/and layout oI a circuit.
The most creative task in the design Ilow shown in Eigure 4.1 is the layout task. Some
decisions about the width and locations oI power/ground bus, the placement and
orientation oI transistors, the width oI wires and their routing, etc. have to be made.
Eigure 4.2 shows a layout oI a circuit. The circle on the layout is not a geometric
object Ior the circuit and should be ignored.
Eigure 4.2. A layout
Problem descriptions:
1. Design an inverter with a Iixed-size pMOS (W2um, L1um, aW, b2um) and
nMOS (W1um, L1um, aW, b2um) transistors. One has to Iollow the design
Ilow shown in Eigure 1. PerIorm Hspice simulation prior to layout (i.e., simply

use the circuit design Irom the schematic) and aIter layout (ie., use the circuit
extracted Irom layout) under a Iixed output load (C0.1pE) and an input waveIorm
with a Iixed slope (rise-timefall-time0.5ns).
(a). Compare the source, drain and gate capacitance extracted by LPE to those
calculated in the problem (1) oI the project 2.
(b). Compare the rise/Iall time (T and T) and propagation delay (T and T) Ior
the circuit prior to layout to those Ior the circuit extracted Irom the layout.
2. Minimize the area oI the layout Ior the circuit designed in (1) as much as possible
by reducing the area oI source/drain oI the transistors or re-arranging the transistors.
(a). Compare the area prior to and aIter layout.
(b). Compare the post layout rise/Iall time (T and T) and propagation delay (T
and T) oI this circuit to those oI the circuit extracted in (1).
3. Cascade two inverter circuits designed in (2) to make a non-inverting buIIer.
Measure the rise/Iall time (T and T) and propagation delay (T and T) oI the
buIIer under the same input conditions and output load.
4. Design a 3-input NAND gate such that its rise/Iall time (T and T) and propagation
delay (T and T) are respectively about 0.5ns, 0.5ns, 1.5ns and 1.5ns and its area
is minimized (with a Iixed output load C0.4pE and input rise/Iall times 0.5ns).
Notes:
A tutorial on the design Ilow shown in Eigure 1 can be Iound on the web.
References:
|1|. HSPICE User`s Manual, Meta-SoItware, 1990.
|2|. 'Composer Tutorial, Cadence.
|3|. 'Virtuoso Layout Editor Help, Cadence.
|4|. 'Diva Interactive VeriIication ReIerence, Cadence.
|5|. 'Dracula User Guide, Cadence.