6 BOOLEAN ALGEBRA SS 6.1 INTRODUCTION oe Sinion Boole, an Englishman, bor in 1815, known today as the father : ey Hy igebra, Published his ‘Mathematical Analysis of Logic’, which has Gu wide-spread application in the design of digital computers. Boolean . Age pats ness, the special language of digital logic circuits. In some ways it is - : ee '€ conventional algebra; but in many respects it has significant For expressing logic circuit functions, as well as for analyzing and designing logic Circuits, Boolean algebra provides a mathematical basis which ~ is almost essential for a proper understanding of digital circuits. In this chapter we will study the special rules of Boolean algebra and consider their application in the design of digital circuits. 6.2 BOOLEAN ALGEBRA SYMBOLS We have discussed some of the symbols of Boolean algebra earlier; but, so that you become thoroughly familiar with them, they are being restated here. You must have used these symbols while dealing with problems of conventional algebra; but in Boolean algebra some of these symbols mean something different. (a) Dotsign@) A dot sign(.), which is also the same as (x) indicates a logical product of two terms so connected. A logical product of two terms A and B can be expressedas A x Band is reada$ “Aand B”. This logical product represents an AND operation and the terms so connected are said to be ANDed. It has to be differentiated from the ‘' sign used in conventional algebra, where it represents multiplication of the terms so joined. _ A system having two variables A and B will have a total of four states 4, A, Band Band the following AND combinations are possible: () A+B readas A and B @ scanned with OKEN ScannerDigital Techno 160 ney B readas NOTA and B @ LB read as NOTA and NOTB @ () Plus sign (1) ‘The '+" sign indicates a A the logical sum of terms so connected. For instance i i ‘Aor B. Here it is referred + sents a logical stim and is read as A ‘ os os RaeREOR ‘operation and the terms So joined are said to be ORed, oe owing for OR combinations are possible ina system having two variables A and B. () 4+ Breadas Aor B (2) A+ Breadas A or NOTB @) A+ B readas NOTA or B (4 A+B readas NOTA or NOTB (©) Exclusive-OR @) This sign is used t0 indicate an exclusive-OR operation, which is expressed as A@ Band is read as ‘A exclusive-OR B’. (a) Overtine — This symbol serves a dual purpose. (1) Asa sign of operation it indicates that the terms so overlined are to be complemented, for instance A (read as NOT A). (2) As.a symbol of grouping it indicates that the terms grouped and overlined like A + Bor A~ Bare to be complemented together. The term or terms overlined are said to be negated and the process of complementing is called negation. () Symbol of equality ‘=' ‘The sign of equality ‘=" has the same meaning as in conventional algebra. This sign between two quantities expresses a relationship of equivalence. A= Bis tead as A is equivalent to B. D Symbols of variables Letter symbols such as 4, B, GX, Y, Z, etc, are commonly used to represent variables. (@) Symbols of constants Since variables in digital electronics can exist in two states only, 0 and 1, these are the only numerals used in Boolean algebra. The result of a Boolean function can be only one of these two constants. 6.3 BOOLEAN POSTULATES Boolean algebra is founded on postulates which origi i olean alg iginate from three basic logic functions. These functions are AND, OR and INVERT operations. The truth tables of these three basic logic functions are reproduced in Table 6.1 alongside the corresponding Boolean postulates. @ scanned with OKEN Scannerppotean gedra 161 Table 6.1 Logic function truth table Boolean postulate AND Logical muliplication Alea elie ol o fo a) o-0-0 of 1 Jo @o-1-0 1} 0 Jo @ 1-0-0 a-fisA sl] a @Mi-aed oR Logical addition a[oe [ec of o fo © 0+0-0 oy a a ovr r|o fa Mito-t ty footadidea @rsrea Logical INVERT complementation A A 1 @o-1 1 o an) T= 0 6.4 BOOLEAN LAWS Boolean laws have made it possible to design and analyze logic circuits mathematically. There are several laws of Boolean algebra which will be discussed in the following sections. In making a study of these laws we will refer frequently to truth tables of AND, OR and INVERT logic functions as well as the Boolean postulates in Table 6.1. 64.1 Laws of Intersection We will study the law as its applies to AND logic functions. This law is stated as follows: Aged Lalea : ral ut (a) Aa sigh (b) Fig. 6.1 (a) and (b) @ scanned with OKEN ScannerDigital Techy ology 162 Law }:As ted Jaw states that ifwe apply logic 1 signal to one of the twWo inputs of This lavw states an AND gate and signal 4 he output will be A. Since input ND gate and si tothe other input, will ante ther Tosie Dae Jogic 1, only two input combinations are possi) Acan be ci P which have been considered below: eo Bie ; From Postulate 2 1 (a) WhenA=0; 4:1=0°1=0 (same as A) Ast ; From Postulate 4 To When A=1; AL=1-1=1 (ameas A) 1 : Fig 6.2 (a) and (b) You will notice that in both the cases output is the same as A. een if ly a logic 0 signal to one of the two The second law states that if we apply a logic 0 sig inputs, when the other inputis 4, the output will be logic 0. The following two input combinations are possible. A=0 From Postulate 1 0 WhenA = 0; 4:0=0-0=0 0 (a) From Postulate 3 Azl : WhenA= 1; A‘0=1:0=0 0 (b) Fig. 6.3 (a) and (b) This proves that if one of the two inputs of an AND gate is 0, the output Will always be logic 0, irespective of the logic state of the input. We can derive the following conclusions from these two laws. @) A-1*A forall values of 4 (Amay be 0 or 1) @ A-0=0 forall valuesofA (Amay be 0 or 1) 1's worth noting that the laws of Intersection are also applicable to AND , Bates having more than two inputs. For instance: AB l= A-B ABO =0 64.2 Laws of Union These laws may be stated algebraically as follows: @ scanned with OKEN Scanneroolean Algebra 163 A 1 Atl 1 1 (a) A 2 AtOmA >) > (b) Fig. 6.4 (2) and (b) pZ: Atle law 3 en ; From Postulate 6 ' >> When A0; A+l=04+1"1 (a) A=1 From Postulate 8 i 1 WhenAw1; A+l=14+1=] (b) Fig. 6.5 (a) and (b) Law 4:A+0=A =0: From Postulate 5 0 At0=A When A®0; A+0=0+0=0 (same as A) (a) Azl From Postulate 7 A+0=A WhenA=1; A+0=1+0=1 0: (same as A) (b) Fig. 6.6 (a) and (b) Consider the application of these laws to OR gates with more than two inputs and draw your own conclusions. Compare your findings with the truth table of an OR gate with more than two inputs. 643 Laws of Tautology These laws may be stated as follows: D (a) 0 (b) Fig. 6.7 (a) and (b) @ scanned with OKEN ScannerDigital Technojog, 164 1 OR gates. In short these | laws apply to both AND and ani that ithesame, signal is applied toall the inputs ofa logic gate, the output sip bbe the same as the input. Law 5: Asana Az0 From Postulate 1 is When A=0; 4:A=0'0=0 (same as A) (a) Asl = From Postulate 4 Ja When A=1; AsAz1 121 (same as A) (b) Fig. 6.8 (a) and (b) Law6:A+A=A From Postulate 5 moma WhenA=0; A+4=0+00 (ame as A) ey From Postulate 8 “Ty oa WhenA=1; A+A=1+1=1 (ame as A) ibs Fig- 6.9 (a) and (b) 64.4 Law of Complements ‘According to this law if we apply a logic signal and its complement to an AND gate, the output will be logic 0. Stated algebraically it means that: » at 1 ° >> ° Fig. 6.10 For an OR gate this law is stated as follows: If we apply a logic signal and its complement to an OR gate, the output will be logic 1. Stated algebraically it means that: Fig. 6.11 ah @ scanned with OKEN Scannert golean Algebra 165 45 Law of Double Negation ‘The law states that the complement of the complement of Ais A. In equation form . [wo A 4-4 | Consider the following table: A a a ° 1 ° 2 1 ° 1 Inthe first case A = 0 ‘When Ais complemented, A = Postulate 9 one When A is complemented, A = Inthe second case A = 1 Postulate 10 When Ais complemented, A = =0, Postulate 16 When Ais complemented, A = 1 = 0 = 1, Postulate 9 It therefore follows that A = A as shown in Table 6.9. 64.6 Laws of Commutation In equation form, the Commutation laws can be stated as follows: 1. A+B B-A 2A+B=B+a Law 10 Law 11 These laws are the same as for conventional algebra. 64.7 Laws of Association These laws are the same as for conventional algebra. ‘They are stated below in equation form. () (A+B) C= A(B-C) Law 12 4 AB ‘ce dee ° = ay (Aye el c De “c4 Fig. 6.13 Fig. 6.16 ES | @ scanned with OKEN Scanner166 (2) (A+ B)+C= At+(Bt C) A (A+B) 8. A AalB4¢) (AB) 40 B- oe NS) ee Fig. 6.15 Fig. 6.16 648 Laws of Distribution We will consider two typical examples of the laws of distribution, 1. AtB+ A-C= A(B+ C) 2. (A + BA + C) = A+(BC) laws In case 1 you will find that groups AB and AG, which are connected by like operators, thats, contain the same variable that isa’. In case 2 you i again notice that groups (A + B) and (A + C), which are connected by lie Operaiors, that is ‘+’, contain the same variable that is ‘A’. The law el distribution states that in such cases, where a group of terms connected by the same operator have a common variable, the variable may be remover! rom the terms and associated with them by appropriate sign of operation Ifyou have a close look at the two cases cited above, you will notice that both of them satisfy the laws of distribution. Law 14: AB + AC = A(B + C) Look at the diagrams given in Figs 6.17 and 6.18, which represent the wo sides of the equation for Law 14. You can prove their equality by drawing truth tables for these two circuits which will prove Law 14 a A 5 * [pxowe 8 —) > -rsene 8. ©. Bec law 14 a Ke Fig. Fig. 6.18 ‘Two equations in their dual form which closely resemble the equation for Law 14 given above are stated below. @) AB+ AB= aA Q@ (A+ BlA+B-a @ scanned with OKEN Scannerpoet? Algebra spite these CqUAtIONS appear Very gj wrtying logic factions instance Yeu snd them very se ~ “At Bs Oyagh +e) owing function: qnis loge fanction, mentioned later in x, 611, has b cppiving Laws 14 and 5. By applying the second equation in eed bY aia in no time write down its simplified form given below FratvB i gwiS:(A* BY(A+ C)= A+ (BC) Logic circuits which represent the two si i eines, sides of the following equation of 167 vpsimp il (4 + BA + C) = 44 (Bc) ‘ AaB [Haine ¢ mT Fig. 6.19 Fig. 620 Truth tables for these two circuits will show that they are performing ‘dentical functions which will prove Law 15. This law can also be proved as follows: (4 + BA + C)= AA + AB+ AC+ BC = A(L + B+ C) + BC = A+ BC = A+ BC Some useful equations following from this law are given below: () A: B+ C+ AvB sD = AB(C + D) Q) A-B+ BC+BD = BiA+ C+D) B) AB+ =(4+c)(a+ B 4) (A+ B(A+ ©) = AC + AB (6) AvBe A:C+ BC = ABH AC © (A+ B+ CMB+ C)# (At Bt C) You can verify the correctness of these equations by comparing the truth tables of the two sides of each equation, 64.9 Laws of Absorption ‘There are five versions of this law as follows: aw) 1 A(A+ Be A tan MG @ scanned with OKEN Scanner168 Ry 2 A+ AB oA ise 3 At AB el 4, ABA B® AtB lw 5. A+ B 8 AtB We will take up one of these laws ata time for consideration, Law 16:A(A + By A ‘The equation is represented by the logic diagram given in Fig. 6.24 the truth table for this circuit is in Table 6.2 which shows that A (4+ [tse . AtB 1 and “= =A 8 Fig. 6.21 Table 6.2 a Q avs AA+B oO ° 5 asta A i 1 eo 49 7 i 1 1 1 1 ‘This law can also be proved as follows A(A + B)=AtA+ AB =AtAB = A(1 + B) =A Law17:A+ A*B=A ‘This function can be implemented by the logic circuit given in Fig. 6.22. fe AB ° Fig. 6.22 @ scanned with OKEN Scannerpoole” Algebra 169 ble for this circu the truth tal MS citcuit is given in abe 4 BWven in Table 6.3. It shows that Table 6.3 = Bol ae A¢acsk | ¢ 6, 040-0 e : ® 0+0"0 } . 0 14004 : a 1 Teacy this law can also be proved as follows: A+A Be Als B eal since + B)= 1 = =A Law 18:A(A + B) = AvB This function can be implemented by the logic diagram shown in Fig. 6.23. A Be Fig. 6.23 The truth table for this circuit is given in Table 6.4. It shows that A(A+ B= AB Table 6.4 A B A A+B A+B) | ae ° 0 1 1 0 ° ° 1 1 1 ° o 1 o ° 0 ° 0 1 1 ° 1 1 1 This can also be proved as follows: A(A + B= At At AB = A:B since AA law19:A:B+ B= A+B ‘ie ‘The function is represented by the logic diagram shown in Fig, 6.24. @ scanned with OKEN Scanner170 > Bias 8 Fig. 6.24 The truth table AB+ Bw A+ B Digital 7 ech, ro for this circuit is given in Table 6.5, I shows " thay ‘Table 6.5 4 B B | 4B AB+B AeB 0 0 1 0 z 1 ° 1 o | 0 ° ° 1 | o |e 0 1 1 1 1 Ofer 1 1 This can also be proved as follows: Multiply Bby (4 + 1). Since (4+). 1and B+ 1 = B the expression will not change. Thus AB+ Be A-B+ BAt1) = AB+ BAtB = A(B+B)+B A+B Law 20:A:B+ B= A+B ‘The function can be implemented by the logic diagram shown in Fig, 6.2. Fig. 6.25 “AB +8 The truth table for this circuit is given in Table 6.6, It shows that AB+ Be atB @ scanned with OKEN Scannerjose Va Table 6.6 This can also be proved as follows. AvB+ Be AvB+ BA + 1), since (A+ 1)™1 the value of the fe expression remains unchanged tAB+ ABs = A(B + B+ B =AL+B ~A+B 64.10 De Morgan’s Theorem There are two versions as follows ) A+ B=A4-B A BL law 21 Q AB =A+B Law 22 law 21:A+ B= AB The two sides of the equation are represented by logic diagrams given in Figs 6.26 and 6.27. ASB [ ws Fig. 6.26 Fig. 6.27 The equality of these logic dingrams is best proved by the truth table given below (Table 6.7). Table 6.7 Inputs Intermediate values Oupputs aa A+B a a A+B ab ° ° 0 1 1 1 1 ° 1 1 1 ° 0 o 1 ) 1 ° 1 ° o 1 1 1 0 0 0 ° Le @ scanned with OKEN ScannerDigital Tec, 172 Olog,, Gr Be AB Table 6.7 shows that A + B Law 22; B= A+B The two sides of the ¢* Figs 6.28 and 6.29. quation are represented by the logic diagrams in DD Fig. 6.28 ‘The following truth table, Table 6.8, establishes the equality of the two expressions. Fig. 6.29 Table 6.8 Inputs Intermediate values Outputs A B AB 4 B WB A+B ° o 0 1 1 1 1 o 1 ° 1 o 1 1 1]o ° ose 1 1 tea 1 o | o ° ° Table 6.8 shows that A" B = A+ B. 6.5 APPLICATION OF DE MORGAN'S THEOREM De Morgan's theorem will be found very useful in simplifying logic functions. By applying this theorem the following simplifications can be achieved. (@) An AND expression can be changed into an OR expression which makes further simplification easy. For example A- B can be changed woA+B (2) A sum-of-products expression can be changed to a product-of-sums form. Forexample A+ B+ B- C canbe changedto(A + B)(B + + If we follow the transformation from : A+ BwA-B step by step, the process of transformation will appear simple. Step Change ORintoAND : A+B becomes AB 2 Complement each tem : A-B becomes A+B @ scanned with OKEN Scanner- potean Algebra 173, 3 Complement the entire expression i Ap = p' ' AB becomes AB of" AR Now, following the same Steps, let us transform 4:B ino A¥B sup! Change AND intoOR : 4-B becomes AaB 2 Complementeach term : 3 Complement the éntire expression +B becomes A+ Bor A+B ae Pak ‘A+B becomes A+B general rule for changing the form of an expressi it : , foll sap aren Goes in rn, lng De (1) Change all OR (+) expression to AND (3 i isan athe cule aa be © expression or the other way (2) Complement individual terms that were ORed or ANDed. (3) Complement the entire expression. Example 6.1 Prove that A-B = A + Busing the rule mentioned above. Step Change AND to OR : A» B becomes A+B 2 Complementeachterm : A+B becomes A+B 3. Complement the entire expression : A+B becomes A+B equals A+B Example 6.2 Prove that =AtB Step1 Change AND to OR : A+B becomes A+B 2. Complement each term : A+B becomes A+B 3 Complement the entire expression :A+B becomes A+B 4+B equis A+B De Morgan's theorem can also be used to simplify expressions having ‘more than two terms by using the same procedure. Example 6.3 Simplify (4+ )(B:C)(C: D) se The best way to simplify this expression is 10 first expand each group, using De Morgan's theorem, and then to expand each term using the same Procedure, as follows: (4B (B-c)(C-D) given expression @ scanned with OKEN ScannerDigital Tecy, nol ‘gy 174 apt ot (oD) each group expanded by De Morgan oe : theore, g+a+G ded by Dy m oe +(C+D each term expan De Morn. (A+ B+ (B+ ¢c) one AaBe B+ c+ c+? tr A+ B+ C+D mA Example 6.4. Simplify GB c) + (A'BC) ee ee === G+B+c) +(a+Bt o _ each group expandeg (4+ B+ C++ B+ ©) cin At Be Ce At Be’ expanded by Law 13 At dt Be B+ Cr expanded by Law 11 el¢i+] tee «1 ‘There isa simpler method to Demorganize expressions. Itis simply stateg as follows in a few words: “BREAK THE LINE ; CHANGE THE SIGN” We will apply this method in those cases which we have already considered, to see how it works. Example 6,5 Demorganize A-B Step Break theline A*B_ 2 Change the sign A+B Example 6,6 Demorganize A-B Step Break theline A 2 Change the sign A+B Example 6.7 Simplify (A+B) (B+ C)(C:D) Step1 Break the line” (A» B) (B+ C)(C-D) 2 Change the sign (4+ B) + (B+C) + (CD) each group expanded 3 Breaktheline (4B) + (B-C) + (C+D) each term separated 4 Change thesign A+B +B+C+C+D 4+B+C+D simplified by Law 6 Example 6,8 (4+ B+ C) + (A: BC) Slep\ Break theline (4-B-@ ) + B.S) 2 Changethesign 4+ B+ Ce As Ba S @ scanned with OKEN Scannerpoolean Algebra 175 A+ Bs CsRs pet avaas Law9 + BeBe ese Valois law 1 law: Table 69 Summary of Boolean Algebra Laws Classification tte 1 Laws of Intersection AL eA 7 406 2. Laws of Union 4 i ‘ : ote 3 AsOnA A+Awd 6 4. Laws of Complements AAnO 7 AtAel 8 5 Law of Double Negation aig 9 6 Lasts of Commutation AvBaBeA 10 ASBaBsA u 7 Laws of Association (A+ B)C# A(B* C) a2 (A+ B+ C= A+(B+ C) Bi 8 Laws of Distribution A’B+A-C# A(B+C) Mw (A+ A+ C)+ A+ (BC) 8 9) Laws of Absorption AAs eA 6 AtABeA v7 A(A+ B)= 4B 8 ABs B-AsB 19 AB+B+A+B 20 10 De Morgan's Theorem Web 4B a As Be A+B 22 6.6. SIMPLIFICATION OF BOOLEAN ALGEBRAIC EXPRESSIONS Simplification of Bool-an. Algebraic expressions leads ultimately to reduction of Booleanexpressions. Since each! logic operator represents a logichardware, reduction of a Boolean expression means reduction in cost. A Boolean expression can be recuiced by using Boolean algebraic laws which we have juist considered. A stage may be reached when no further reduction is possible and that will represent the simplest form of logic circuitry which satisfies the Boolean expression. Let us consider the function Fe AB+ (B+ ©) ‘The logic diagram for this expression is given in Fig. 6.30 @ scanned with OKEN ScannerDigital Teed noo, te ) ‘ > -F eADH (BHC) : Swe Pig. 6.90 Lerus now simplify the & ae ete Bt Yee ie «Bite aw =B+C Lay} this function is given in Fig. 6.31, = losic di which will represent ‘The logic diagram hat has been achieved by using You will notice the great simplification t Boolean laws. ane a F=B+C Cc Fig.6.31 ‘To verify this you may draw up the truth tables for the two logic circuits. ‘The truth tables for both the circuits are given in Table 6.10. ‘Table 6.10 a4]a|clas] ste |asesec Oe | oral 0. ° ° oY ig) AAG A dg) 1 1 of} 1 ]o}o 1 1 Or feed a TE |p: 1 1 1]o}otlo ° ‘ rePoon[sasdee 1 : PPA ay 8 le : 4 a Saea 1 1 You will notice from the above table that B+ CHA BeBe 4 @ scanned with OKEN Scannergxample 6.9 Simplify the following function: Fr CB+ cas Bac) Example 6.10 Simplify (CB + cc)(4 + B+ ¢) Law 14 = (CB + C)(4+ B+ c) Law 5 = CB+ (4+ Be c) Law 14 = C(A+ B+) Law 3 = CA + CB4+ CC Law 14 = C(4+ B41). Law 14 =c Law 3, the following function: PeaBeC+ AB C+ ABC ei ABC Law 11 « eS Law 14 = law 8 = Lawl Example 6.11 Simplify the following function: F=(4+B+C)(a+B+c) = AA + AB + AC+ BA+ BB+ BC+ CA+ CB+ CC lawld = A+ AB + AC+ BA+ Bit BC+ CA+CB+ CC law5 =A(1+ B+ C+ B4C)+ B+ C+ C) 40 Law 14 = A14 Be =A+B Example 6.12 Simplify the following function: F=A-B(A+ B) -G@+Bla+B _ = A-A+AB+AB Law 22 +BB lawl4 =0+A4:B+A-B+0 Law7 =A:B+ AB Example 6.13. Simplify the following function: Law 22 Law9 Law 22 BB Law 14 law7 @ scanned with OKEN ScannerDigitar t, ech 178 lop, 2 AOB following function: pon (As Bs (BA) — =< » (A: B) + (Bea) Example 6.14 simplify the AB + BA law 29 -AOB laws Example 6.15 simplify the following function: pete ba car be Vat Bt A+ Bs A+B, was cas oat B+) : = c+ B+) = cla+B) 6.7 LOGIC CIRCUITS snaking functions a combination of AND, OR and Not d. The logic circuits so formed are known as eoabt national logic circuits. There are many (ypes of combinational logic circuits ‘wnich perform specific functions such as encoders, decoders, multiples = ttc, which we will study later on. While these combinational logic circuits ploy a variety of circuit configurations we will, forthe present, restrict oe discussion to two configurations, Which occur frequently in combinational logic circuits. These circuits are referred to as (@) Sun-of-products (SOP) and (b) Product-of-sums (POS) circuits Sum-of-products circuits Fig. 6.32 shows a circuit in which the output of two AND gates constitutes the input of an OR gate. The final output is thus (AB + CD). For various decision logic gates is employe Fig. 6.32 Ye : SE oreon nT that AB and CD are the two product terms and the caer ates asum term (AB + CC), whichis inthe frm of sm, to AND gat ie distinguishing feature of this circuit is that, inputs are coupled gales and the output is obtained from an OR gate. @ scanned with OKEN Scannerpooled Algebra 179 We have considered a produg a single Variable product term “term with two Variable sould also be noted that a sum. ; , but there may be Fa logical s, but there may be ofp Product of s¢ rodtiets eo uet OF several variables. I vo product terms such a5 (ap ery eyes CSPHESION may have more than ‘The sum-of-products circuit given om servo, which means that he Smt eB S325 inthe gates. There May, however, be SOP cane ohio levels: h emy producl-of'sums circuit The otherbasic decision-makin cjcut which, in its simplest form form ofa wwo-level output through two iploy more than two IBCircuitis referredto asa of: Shown eae aa produco-ums AtB JFF=(aeay(c+0) Fig. 6.33 c+ In this type of circuit inputs feed OR gates and the output is derived from an AND gate. The expression for the output of this circuit is Fe (A+ B(C+D) ¢ the SOP circuit this is also a two-level circuit, in which both the sum terms have two variables. However, a sum term may have a single variable or a sum of several variables. The POS circuit of Fig. 6.33 generates a product of two sum terms, but there may be POS expressions having several sum terms. 6.8 TRANSLATING ALGEBRA TO LOGIC All logic diagrams are so drawn that the input is on the left hand side and the output is on the right hand side. To draw a logic diagram which corresponds toa given Boolean expression, we should begin at the output and develop the logic circuit as we work backwards from the output to the input. Suppose We have to develop logic circuit which corresponds tothe following Boolean expression: Fe AaB+ BC i 1m-of-products form, which points te ‘The expression corresponds to a sum-of-pr . an OR gate at the output. The OR gate has two inputs A+ Band B+ C These inputs point to an AND function which provide inputs A» Band B- C The following logic circuit will therefore correspond to the given Boolean expression: @ scanned with OKEN Scanner180 Digitat Techno —) —F-A8s8¢ Dy (Ss! Fig. 6.34 Let us now consider the following Boolean expression: Fe A:B+ BC and draw a corresponding logic circuit. The expression is a NOTed function which points to an inverter at the output, the input of which is A- B+ B.¢ This is a sum-of-products function, which points to an OR gate before the Inverter. There are three input signals. The inputs to the OR gate are in a Product form, which points to AND functions. The input Bis realized by using an Inverter, The logic circuit corresponding to the given Boolean expression is given in Fig. 6.35. A sep Fig. 6.35 AB+BC oe ‘We will now consider another expression involving more than two level changes as well as involving a combination of both product-of-sums and sum-of-product forms. The following expression is an example: Fe(A+C)(4+B+(B+cja-c This expression points to an OR gate at the output. It also suggests that the OR gate is fed by AND gates, which are preceded by OR gates and an AND gate. The entire circuit is given in Fig. 6.36 (a). The Boolean expression was translated into a logic circuit without first simplifying it, and you will notice that in many cases considerable simplicity and saving in cost czn be achieved by reducing an expression to its simplest form before translating it into a logic circuit, as you will see in this particular case. The Boolean expression which we have just considered can be reduced to the following form: Fu Bla+C)+ae a @ scanned with OKEN Scannerppoiean Algebra 181 bh Ast ¢. k A+B 8. 3 Bsc F(A4CyR4B) (B40). ¢ b Fig. 6.36 (a) This leads to a much simpler logic circuit i it Fig ' requires only four gates. gic circuit as shown in Fig. 6.36 (b) which a ast ¢. BiA+E) 8 a ~) maureen A KE ake Fig. 6.36 (b) 69 TRANSLATING LOGIC CIRCUIT TO ALGEBRA In developing a Boolean expression for a given logic circuit, we start at the input and develop an expression for the output of each logic gate advancing from leftto right, until the output has been reached. We will consider the logic diagram given in Fig. 6.37 (a) and, after translating its function into a Boolean expression, we will attempt to simplify the Boolean expression and rx cate a logic circuit which will perform the same function. Steps Inputs A and B fed AND gate 1, so its output is A B Inputs Band Cfeed OR gate 2, so its output is B + © Inputs A and Cfeed AND gate 3, s0its output is A C Outputs of gates 1 and 2 feed OR gate 4, so ts output is A:B+ (B+ C) @ scanned with OKEN Scanner“e i. Pisitadtecty, ‘s —— as AB Lbs HB 40) a y > yite : B-_\ Fig. 6.37 (a) 5. Outputs of gates 2 and 3 feed AND gate 5, so its output is A-C(B+C) 6. Outputs of gates 4 and 5 feed OR gate 6s so the final output ig A-B+ (B+ C)+4:CB+ Cc) This Boolean expression is capable of simplification as indi Fe A-B+ (B+ C)+4:CB+c) = A-B+(B+ C)(1+ 4c), =A B+Bec eAtBee This expression can be implemented by a 3-input OR gate as shown in Fig. 6.37 (b). icated below, Omt> Fig. 6.37 (b) 6.10 TRUTH TABLE FROM LOGIC CIRCUIT For analyzing the performance of a logic circuit, it is useful to develop a truth table from which the output can be evaluated forall possible combinations of input values, We will analyze the performance of the logic circuit given in Fig. 6.38. @) As a first step develop an output equation for the Linscheires following the guidelines given in Sec6.9. The output equation fort logic circuit of Fig. 6.38 is @ scanned with OKEN Scannerr we ae 183 be Fea+BC BC Be ¢ Fig. 6.38, Prat Be combinations is 8. @) Next draw up a truth table as indicated in Table 6.11 Table 6.11 i Ouputs BeBe Ge Re e Be A+ © ° 0 ° 1 Oered 0 0 1 0 1 O+let 0 1 0 o 1 Orlet o 4 afr oo o+o-0 1 0.0 fo a leted 1 o8eAsn [0% 4 leaded 1 1 of o 4 deded 1 11 | tera go 1eoed You will notice from the truth table that the output is 0 only for one of the 8combinations of the input variables. 6.11 LOGIC CIRCUIT FROM TRUTH TABLE Staring from a truth table, it is possible to design logic circuits in the sum-of-products and product-of-sums forms. This will enable a choice to be made out of the simpler of the two logic circuits. : When we design a logic circuit, we know the number of inputs for which the circuitis to be designed and, according to the design criteria, we also know the output states for the various input combinations. Let us conside: the following truth table for a 2-input logic circuit as given in Table 6.12. 7 @ scanned with OKEN Scanneron Digital Tech 4 Mo 184 Oh, Table 6.12 mp ‘ouput Product sum ae Terms Terms | A B x ‘ oe 1 ab Of fa 1 AB ees ° a+e 1 i 1 AB ‘This table also gives the product terms for which output is 1 and the sum, terms for which the output is 0. Sum-of products expression For the sum-of- products expression, we only consider the product terms for the rows for which the output is 1. Output is 1 for rows 1,2 and 4. The sitput of row 1 willbe 1 only when both the inputs A and Bare complemented The output of row 2 will be 1 when A is complemented and B is not complemented. Likewise, for sow 4 neither input is to be complemented, The product terms for the three output states will be AB, A- Band A-B. Ty logical sum of these three product terms will give the required SOP expression, which will be as follows: Fe A+B This leads to logic circuit Fig. 6.39 Product-of-sums expression For the product-of-sums expression, we need to consider the rows for Which the output is 0. The output is 0 only for row 3 and what we requi the sum term for this row. The sum term for this row should, therefore, be A + B, that is input A should be complemented and input B should remain as itis. If we had two sum terms, we would have taken the logical product of these two sum terms to give the required expression. However, since there 15 only one sum tem, the expression will be given by Feats This expr sion is the same as for the sum-of-products expression. @ scanned with OKEN ScannerAlgebra sientee Alge? 185 we now take up a circuit having three i ye oth table given in Table 6.13 and deri ol ihe sequired logic circuit inputs, for which we will consider) tive SOP and POS expressions for Table 6.13 Inputs ouput | Product sum (op aeta| ee Tems Terms oe 1 Be ool 1 Ric ge ee 1 Abe oa eek ° ABs Into a8 1 AB Age 240 idsturh 1 ABC 1 rsan iso ° FsBec te cael ° A+Bee The sum-of- products expression will be as follows: Fe A-BeC+ AB C+ A:BC+ AB C+ ABC B+ 0) + a-B+ 0) +A-B-C “B+ AB+ ABC The logic circuit required to implement this function will be as shown in | ‘ig. 6.40. >I c Fig. 6.40 ‘The product-of-sums expression will be the product of the three sum terms as follows: = io 5 palate G+ B+ G+ B+ 2 (44 B+ Ot BD 2 Birds Bas +4 ¢ =B+ ae ‘This expression happens to be! solution. he same as for the sum-of-products @ scanned with OKEN Scanner186 Digital Tecbrotogy 6.12 COMRINATIONAL CIRCUITS USING NAND/NOR GATES Jered AND, OR gates and Inverters for implementing combinational logic circuits. However, NAND and NOR gates ate more versatile, as they can be used to perform AND, OR and INVERT functions fr this section we will look into this aspect and later investigate how AND/OWINVERT logic circuits can be converted to NAND/NOR logic, We have so far cons 612.1 NAND Logie NAND used as verter ANAND gate can be used as an Inverter by tying all inputs together. The summary of finetions in Table 6.14 shows how a 2-input NAND gate can be used as an Inverter. When a NAND of NOR gate is used in a logic diagram, the symbol used in the diagram should represent the logic function being performed and not the NAND or NOR configuration. This is in accordance with the standards for logic symbols. Therefore, if a NAND or NOR gate is used as an Inverter, the logic diagram should show the Inverter symbol. Similarly when a NAND gate is used as a negated-OR, the symbol for negated-OR should be tsed. Also when a NOR gate is used as a negated-AND, the symbol for negated-AND should be used. You may refer to Tables 6.14 and 6.15 for these symbols. NAND used as AND Ifthe output of a NAND gate is inverted by connecting an Inverter at the output, the combination will function as an AND gate. \NAND used as negated-OR De Morgan's theorem, Law 22, states as follows: WB-A+B The left side of the equation represents the NAND function and the right side of the equation represents a negated-OR function. In other words NAND = negated-OR In symbolic form t > al g 3 + 1 o> > a (a)* (b) Fig. GAL When a NAND gate is requited to represent the negated-OR function, the symbol used is the OR symbol with bubbles at the inputs, which represent Inverters, although actually there are no Inverters. This is only a device to indicate that the NAND gate is used to. represent a negated-OR function as shown in Fig. 6.41 (b). @ scanned with OKEN Scannerigor Alger? 67 poor 1s ,ypused as OR " the above discussion it will be obvious that a NAND gate will promt Fav py the OR function, if Inverters are added ahead of the inputs of a NAND fo 4 jello following diagrams (Fig, 6.42 and Fig, 6.43) will clarify the point ene nye Morgan's theorem —4 8 {>> Fig. 6.42 since in this application the NAND gate is used to perform the negated-OR function, it is desirable to use a negated-OR symbol as shown in Fig. 6.43- pt Fig. 6.43 Table 6.14 [a Fencton Sl [ek Function Configuration INVERTER AND NEGATED-OR @ scanned with OKEN ScannerDigital Tecbnotey, 188 612.2 NOR Logic The NOR gate is as ve functions, le asthe NAND gate and it can perform all ogi NOR used as Inverter beats Vea XOR gate can also function as an Inverter, if ¢ the NAND gate, the NOR gate ca vn the ane ceie togeth le 6.15 shows a 2-input NOR gate used as 4 Inverter. NOR used as OR Ifan Inverter is connected to the output of a NOR gate, it Hs erfonm the function of an OR gate. This combination is also shown in Table 6.15, NOR used as negated-AND De Morgan’s theorem, Law 21, states as follows: A+Bea-B The lefi side of the equation represents j¢ NOR function side represents the negated-AND function. In other words NOR = negated-AND and the night In symbolic form fa) Fig. 6.44 When a NOR gate is required! to sepresent the negated AND function, the nbol used is the AND symbol with bubs although actually there are no Inverters The only a device to indicate that the NOR gate is used to represents egated-AND function, NOR used as AND Nou will realize from the above discussion that the AND function, i Inverters are added ahead Of the i The following diagrams (Fig, 6.45 and 6.46) illustrate by is performed. ‘OR gate will perform Inputs of a NOR gate }ow the AND function A a Fig. 6.45 @ scanned with OKEN Scannerpose ee 189 sincein thisapplication, the NOR gate is used to perform the negated-AND lion, it is desirable to use the negated-AND symbol as shown in Fig. 6.46. fu Fig. 6.46 Table 6.15 Tuetion Configuration Function Symbol INVERTER sere feb & cS - or BD fo Bi AB ad As \EGATED-AND lAND » 8 6.13 CONVERTING AND/OR TO NAND/NOR LOGIC So far we have considered AND/OR combinational logic circuits, although NAND/NOR gates are far more versatile. We ‘will now consider procedures for implementing Boolean expressions by using NAND/NOR gates. : NAND Logic ‘We will consider the following expression: Z= (A+ B(A+ Cc) and consider the necessary steps for implementing it with NAND gates. () For implementing the expression with NAND gates it should be changed to a sum-of-products form as indicated below: @ scanned with OKEN ScannerPisitar Tectngy Z= (A+ B(A+c) + AA + AB+ AC+ BC = AB + BC+ AC = AB + BC(A + 4) + Fic = AB + ABC + ABC + Ac ‘ = AB(L + C) + Ac(C + 1 = AB+ AC 2) The next step is to draw a corres : configuration, as given in Fig. 6.47. at 8 sale) _) >= BHR ro c— ce Fig. 6.47 ponding 2-teye, a /03 (3) The equivalent NAND gate logic circuit is obtained by chang gates in Fig, 647 to NAND gates as shown in Fig, 6457 "88 all AS Fig. 6.48 By using De Morgan's theorem it can be proved that A‘B+ ACH A-B+A-C AB+ACHABtAC “GBA B+hC =~ GEC) ‘This proves thatthe logic circuit of Fig 648 s equivalentto the logiccicuit of Fig. 6.47. @ scanned with OKEN Scannerran Algebra so 191 vor ei consider th fe will consider the same expressi wees) for implementing Tank oR eae and discuss the various (1) Forimplementing with NOR gates the expressi aes " -ssion hi inthe ofa product-of-sums. Since the expression under ae Z=(A+ B(a+c) is already in the S-O-P form, no transformation is required. ste @ The next step is to draw i configuration s given in ig. 649. ae as i ; ° Tf rattssuate . ASC ‘ Fig-649 (3) The equivalent NOR gate logic circu in Fig, 6.49 to) ealized by changing all gates ‘OR gates, as shown in Fig. 6.50. X (R48) 8. A zo] ¢ Fig. 6.50 ‘The transformation from AND/OR to NAND/NOR logic can also be accomplished by the following procedure: (2) Reduce the expression using the laws of Boolean Algebra. (2) implement the reduced expression using AND/OR gates. @) Decide whether NAND or NOR logic is to be used. G) IFNAND logic is used, replace each AND, OR symbol by the NAND equivalent of the logic symbol as given in Table 6.14 (5) If NOR logic is used, replace each AND, OR symbol by the NOR equivalent of the logic symbol as given in Table 6.15 @ scanned with OKEN Scanner192 teal Techy eg (6) Ifany symbol becomes superfluous, it should be climinateg, Using NAND gates the same expression Z= 4-3 + Fc hy, implemented as shown in Fig. 651. This circuit is equivalent to the cae Fig 64, asthe Inverters have become sperfous andthe bubbieg go ta is equivalent oa NAND gate. Bate ABIES Fig. 6.51 Following this procedure the expression Z= (A+ Hl(A+ C) has been implemented using NOR gates for a product-of-sums shown in Fig. 6.52. This circuit is equivalent to the citcuit sho ay the Inverters have become superfluous and the bubble equuvalent to a NOR gate. Expression, a5 wn in Fig. 6 59 d AND gate jg x TM hs Me 8 —] Homa - Rt Ase a ¢ Fig. 6.52 Problems 61 Simplify the following Boolean expressions ) Feacdd 6) Fed BAS ABA Q FABRA © FAA BIG TBA @ Fea: ) Fe AB-4-B 4 4-8 @ FAB BC ABO Simplify the following Boolean expressions Fee Blase 62 @ scanned with OKEN Scannerspan Alger” wate 193 2) = (A+ Be @ FAS BCA B+) () Fe (4+ Blas cc) simplify the follow os seer te ving poe expressions: (@ Fe aa + (AB + BD (@) Fa (AB + BAB + B | (4) F= A(AB + B) 64. Simplify the following Boolean expressions (Q) Fe Abt 4B +B (2) F= AB + AC+ ABC @) F ABC + ABC + ABC G) F = ABCD + ABCD + ABC + BD 65. Simplify the following Boolean expressions: | () Fe A+ BUA 4 C) 4 CC + AB Q) Fe ABA +C)+ ABB + ©) Q) F = AB(B + C) + BC + A) | (4) F + (AB + €)(AB + ©) 646 Simplify the following Boolean expressions: Q) FeaB Fe Re @) Fe AB G) Fe AB C+ BC ‘| | 67. Simplify the following Boolean expressions: es eee nee eae a) Fe (A+ Bid + C)B+ C) © Fe (a-B C+ AB) (c-B) 68 Without simplifying convert the following expressions 10 AND/ORVINVERT logic: () FeAB+aC+D Q) Fe aBC+ ABC+ ABC Q) Fe FBC D+ ABCD + ABE () Fe AB(C + D) + BCA + D) 69 Without simplifying convert the following expressions to AND/ORVINVERT logic: @ scanned with OKEN Scanner194 6.10 611 613 614 615 Digitat Techno Q) Fa(4+ BC+ D) @ Fa (4B + Cylac+ B @ Fe a(a+ C+ ©) @ Fe ADB+ D) Translate the following logic ctcuitstoalgebra and simpli (A) Logic circuit given in Fig. 6.7 (2) Logic circuit given in Fig. 6.9 (3) Logic circuit given in Fig. 6.10 ify the, Xpression Draw logic circuit diagram from the following truth table: Inputs Ouput 4 a é F ° ° ° t o ° 1 ° ° 1 ° ° ° 1 1 ° 1 ° ° 1 1 0 1 ° 1 i ° ° 1 1 1 ° Implement the folloming function with NAND/NOR logic Fe(at Be +D Implement the folowing function with NAND/NOR logic Fe ADB + Dd) Simply the following f ogi Simpy Tecate fenton ac a a logic cuit npemen te Felld+ B+ che ac Prove that (4+ B+ CBs Calas Ds c) @ scanned with OKEN Scanner