Điều khiển thiết bị qua PC

LI M U
Vi vic pht trin ca k thut vi x l hin nay th vic p dng vo thc tin
i sng l mt nhu cu cn thit ca con ngi. Vi xu hng hin i ha nh hin
nay th vic iu khin thit b bi mt h thng s gip vic iu khin thit b n
gin v d s dng cho ngi dng.
Nm bt c tnh hnh nhm sinh vin chng em la chn ti iu Khin
Thit B Qua PC nhm nghin cu cung cp cho ngi dng mt h thng iu
khin n gin m hiu qu, l h thng iu khin nhiu thit b ti ch qua vic
kt ni vi cng COM my tnh, chng ta c th iu khin c cc thit b dn dng
nh n dy tc, n hunh quang, v cc thit b c c iu khin bng chc
nng ON/OFF.
Thng qua vic nghin cu vi iu khin AT89S8252, cc cng giao tip my
tnh v cc linh kin in t, ti s mang li mt h thng n nh, chnh xc v an
ton vi ngi s dng.
Vi s hng dn ca c Nguyn Lan Anh gip chng em hon thnh tt
ti ny.
Trong qu trnh tm hiu khng th khng c nhng iu thiu st, mong qu
Thy C v ngi c gp , chnh sa ti ca chng em c hon thin tt
hn.
Nhm Sinh Vin
Trang 1
iu khin thit b qua PC
Mc lc
MC LC
LI M U .........................................................................................................................1
MC LC ................................................................................................................................2
CHNG 1: DN NHP ....................................................................................................6
1.1
L DO CHN TI ............................................................................................6
1.3
I TNG NGHIN CU V PHM VI NGHIN CU ..........................6
1.3.1
i tng nghin cu. .......................................................................................6
1.3.2
Phm vi nghin cu............................................................................................6
CHNG 2: TM HIU VI IU KHIN AT89S8252 ..............................................7

2.1
M T ........................................................................................................................7
2.2
CU TRC VDK AT89S8252, CHC NNG TNG CHN ........................7
2.3
T CHC B NH .............................................................................................. 11
2.3.1
RAM mc ch chung..................................................................................... 12
2.3.2
RAM nh v. ................................................................................................... 12
2.3.3
Cc bng thanh ghi (Register Banks). .......................................................... 12
2.3.4
Cc thanh ghi chc nng c bit (Special Function Register). ................ 13
2.3.4.1 T trng thi chng trnh (PSW: Program Status Word): .................... 14
2.3.4.2 Thanh ghi B:................................................................................................. 16
2.3.4.3 Con tr Stack SP (Stack Pointer): ............................................................. 16
2.3.4.4 Hai con tr d liu DPTR (Data Pointer) ................................................. 16
2.3.4.5 Cc thanh ghi Port (Port Register): ........................................................... 16
2.3.4.6 Cc thanh ghi Timer (Timer Register):..................................................... 16
2.3.4.7 Cc thanh ghi Port ni tip (Serial Port Register): .................................. 17
2.3.4.8 Cc thanh ghi ngt (Interrupt Register): ................................................... 17
2.3.4.9 Thanh ghi iu khin ngun PCON (Power Control Register): ............ 18
2.3.4.10 Thanh ghi iu khin b nh v kim sot gi (WMCON) ............... 19
2.3.4.11 Thanh ghi giao tip ni tip bn ngoi SPI (Serial Peripheral
Interface) .................................................................................................................... 20
2.4
TM TT TP LNH CA AT89S8252 ......................................................... 21
2.4.1
Cc ch nh v ( addressing mode ) ....................................................... 21
2.4.1.1 S nh v thanh ghi ( Register Addressing) ............................................ 21

2.4.1.2 S nh a ch trc tip ( Direct Addressing ) ........................................ 22
2.4.1.3 S nh v a ch gin tip ( Indirect Addressing) ................................. 22
Trang 2
Mc lc
2.4.1.4 S nh v a ch tc thi (Immediate Addressing) ............................... 23

2.4.1.5 S nh v a ch tng i ....................................................................... 23
2.4.1.6 S nh a ch tuyt i ( Absolute Addressing) ................................... 24
2.4.1.7 S nh v a ch di ( Long Addressing ) .............................................. 24
2.4.1.8 S nh a ch ph lc (Index Addressing )............................................ 24
2.4.2
Cc kiu lnh (instruction types) ................................................................... 25
2.4.2.1 Cc lnh s hc (Arithmetic Instrustion): ................................................ 25

2.4.2.2 Cc hot ng logic (Logic Operation): ................................................... 26
2.4.2.3 Cc lnh r nhnh ........................................................................................ 27
2.4.2.4 Cc lnh dch chuyn d liu. .................................................................... 29
2.4.2.5 Cc lnh lun l (Boolean Instruction) ..................................................... 30
2.5
HOT NG CA PORT NI TIP AT89S8252. ........................................ 31
2.5.1
Gii thiu .......................................................................................................... 31
2.5.2
Thanh ghi iu khin port ni tip SCON (Serial Port Control Register) 32
2.5.3
Cc mode hot ng (Mode Of Operation) ................................................. 33
2.5.4
S khi ng, truy xut cc thanh ghi port ni tip.................................... 34
2.5.4.1 S cho php b thu (Recive Enable) ......................................................... 34

2.5.4.2 Bit data th 9 ( the 9 th data bit) .................................................................. 34
2.5.4.3 S thm vo bit kim tra chn l Parity .................................................... 34
2.5.4.4 C ngt .......................................................................................................... 35
2.5.5
2.5.6
2.6
S truyn ca b x l a knh ................................................................. 35

Tc baud ca port ni tip ........................................................................ 36
HOT NG TIMER CA AT89S8252 .......................................................... 39
2.6.1
Gii thiu .......................................................................................................... 39
2.6.2
Timer 0 v Timer 1 ......................................................................................... 39
2.6.2.1 Thanh ghi iu khin Timer TCON (Timer Control Register).............. 41

2.6.2.2 Cc Mode v c trn (Timer Modes And Overflow).............................. 41
2.6.2.2.1 Mode Timer 13 bit (MODE 0) ............................................................. 41
2.6.2.2.2 Mode Timer 16 bit (MODE 1) ............................................................. 42
2.6.2.2.3 Mode t ng np 8 bit (MODE 2) ..................................................... 42
2.6.2.2.4 Mode Timer tch ra (MODE 3)............................................................ 43
2.6.2.3 Cc ngun xung clock (Clock Sources).................................................... 43
2.6.2.3.1 S bm gi bn trong (Interval Timing) ............................................. 43
2.6.2.3.2 S m cc s kin (Event Counting) ................................................. 44
Trang 3
Mc lc
2.6.2.4 S bt u, kt thc v s iu khin cc Timer (Starting, Stoping And

Controlling The Timer) ............................................................................................. 44
2.6.2.5 S khi ng v truy sut cc thanh ghi Timer. ...................................... 44
2.6.2.6 S c thanh ghi timer trn tuyn. ............................................................ 45
2.6.3
Timer 2.............................................................................................................. 45
2.6.3.1 Thanh ghi T2CON (Timer/Counter 2 Control Register) ........................ 46

2.6.3.2 Thanh ghi T2MOD Timer 2 Mode Control Register........................... 47
2.6.3.3 Ch Capture ............................................................................................ 47
2.6.3.4 Ch Auto-Reload.................................................................................... 48
2.6.3.5 Ch Baud Rate Generator...................................................................... 49
CHNG 3: TM HIU CC CNG GIAO TIP................................................... 51
3.1
GIAO TIP CNG SONG SONG (CNG MY IN) ..................................... 51
3.1.1
Tn gi .............................................................................................................. 51
3.1.2
Mc in p cng ............................................................................................ 51
3.1.3
Khong cch ghp ni .................................................................................... 51
3.1.4
Tc truyn d liu ...................................................................................... 51
3.1.5
Cu trc cng song song................................................................................. 51
3.1.6
Cc thanh ghi cng song song. ................................................................... 53
3.2
GIAO TIP CNG NI TIP (RS232) ............................................................. 53
3.2.1
Cu trc cng ni tip. .................................................................................... 53
3.2.2
Truyn thng ni tip gia 2 nt. .................................................................. 56
3.3
TM HIU V USB ............................................................................................... 57
3.3.1
Khi nim ......................................................................................................... 57
3.3.2
Kt ni qua USB.............................................................................................. 58
3.3.3
M rng cng USB ......................................................................................... 58
3.3.4
Cc t tnh ca USB ...................................................................................... 59
3.3.5
USB 2.0 ............................................................................................................ 60
3.3.6
USB 3.0 ............................................................................................................ 60
CHNG 4: CHUN TRUYN THNG NI TIP RS232.................................. 62

4.1
T VN . ....................................................................................................... 62
4.2
U IM CA GIAO DIN NI TIP RS232. ............................................. 62
4.3
NHNG C IM CN LU TRONG CHUN RS232. ..................... 62
4.4
CC MC IN P NG TRUYN......................................................... 62
4.5
CNG RS232 TRN PC....................................................................................... 63
4.6
QU TRNH D LIU. ....................................................................................... 64

Trang 4
Mc lc
4.6.1
Tc Baud. .................................................................................................... 65
4.6.2
Bit chn l hay Parity bit. .............................................................................. 65
4.7
S KT NI ................................................................................................... 66
CHNG 5. THIT K MCH PHN CNG IU KHIN ............................. 67

5.1
KHI NGUN NUI VI IU KHIN, MCH. ........................................... 67
5.2
KHI CHUYN I TN HIU RS232 THNH TTL DNG MAX232... 68
5.2.1
Gii thiu v MAX232 ................................................................................... 68
5.2.2
S kt ni. ................................................................................................... 68
5.3
MCH IU KHIN NG NGT TI AC. ................................................ 69
CHNG 6: THIT K CODE V GIAO DIN IU KHIN.......................... 71

6.1
THIT K CODE IU KHIN VI X L .................................................... 71
6.1.1
tng thit k ............................................................................................... 71
6.1.2
Lu gii thut ............................................................................................. 72
6.1.3
Code iu khin ............................................................................................... 72
6.2
THIT K GIAO DIN IU KHIN .............................................................. 75
6.3
MCH NGUYN L ........................................................................................... 83
6.4
MCH M PHNG.............................................................................................. 84
CHNG 7: HNG PHT TRIN CA TI................................................. 85

TI LIU THAM KHO ................................................................................................. 86
PH LC 1........................................................................................................................... 87
PH LC 2........................................................................................................................... 88
Trang 5
1.1
Chng 1: Dn Nhp
CHNG 1: DN NHP
L DO CHN TI
Vi s pht trin khng ngng ca cc ngnh khoa hc k thut nhn p ng

ngy cng a dng v phong ph cho i sng con ngi, vic nghin cu v pht
trin cc sn phm iu khin t ng thay th sc lao ng ca con ngi l mt
nhim v rt cn thit.
Vic gim st v iu khin cc thit b t xa qua h thng gm cc phn t ni
vi nhau bng dy dn thng qua chun RS232 em li mt li ch ht sc to ln
cho nhu cu pht trin ca x hi, tit kim c rt nhiu thi gian, sc lc v mang
li hiu qu kinh t ln.
Nm bt c tnh hnh quan trng, vi quyt nh la chon ti iu khin
thit b qua PC nhm gp phn mang li s tin nghi, tin ch cho cuc sng ngy
nay.
1.2
MC CH NGHIN CU TI
ti s dng iu khin cc thit b dn dng trong gia nh nh n, qut,..

thng qua ngn ng lp trnh ph bin hin nay. T vic tm hiu v cc thit b giao
tip cho n vic thit k mch nhm gip ngi c d dng tip nhn v mun cung
cp h thng iu khin cho ngi s dng.
1.3 I TNG NGHIN CU V PHM VI NGHIN CU

1.3.1 i tng nghin cu.
Tm hiu v cc cng giao tip: cng ni tip, cng song song, cng USB,
chun kt ni RS232, kho st vi iu khin AT89S8252.
1.3.2 Phm vi nghin cu.

Thc hin vic kt ni thit b iu khin vi PC thng qua RS232, iu khin
cc thit b dn dng.
Trang 6
Chng 2: Tm hiu VDK AT89S8252
CHNG 2: TM HIU VI IU KHIN AT89S8252

2.1 M T
AT89S8252 l mt vi iu khin do ATMEL sn xut, ch to theo cng ngh
CMOS vi 8KB Flash (Flash programmable and erasable read only memory) v 2KB
EEPROM. Thit b ny c ch to bng cch s dng k thut b nh khng bc
hi mt cao ca ATMEL v tng thch vi chun cng nghip MSC-52 T M v lp
tp lnh v cc chn ra. AT89S8252 l mt vi iu khin mnh c cng sut ln c
tnh linh ng cao v ph hp v gi c i vi cc ng dng vi iu khin.
Cc c im ca AT89S8252 c tm tt nh sau:
Tng thch hon ton vi h MSC-52T M ca Intel.

8 KB b nh c th lp trnh li nhanh, c kh nng ti 1000 chu k ghi
Tn s hot ng t 0Hz n 24 MHz.

3 mc kha b nh lp trnh.
3 b Timer/Counter 16 bit.
256 Byte RAM ni.
4 Port xut nhp I/O 8 bt.
Giao tip ni tip.
2KB EEPROM bn trong dng lu tr chng trnh.
bn EEPROM: 100.000 ln ghi/xa.
Ch h ngun v ch li tiu tn cng sut thp.
9 ngun ngt.
iu khin truyn d liu trc tip qua cc chn MISO, MOSI, SCK.
2.2
CU TRC VDK AT89S8252, CHC NNG TNG CHN
xa.
Chc nng hot ng ca tng chn (PIN) c tm tt nh sau:
Trang 7
Hnh 2.1: S chn AT89S8252

T chn 18 Port 1 (P1.0, P1.1, , P1.7) dng lm Port xut nhp I/O giao
tip bn ngoi vi in tr ko ln bn trong. Cc b m xut ca Port 1 c th
cp/ht dng cho 4 ng vo TTL loi LS. Cc chn Port 1 c cc bit 1 c ghi
c ko ln mc cao bi cc in tr ko ln bn trong v trong trng thi ny chng
c dng lm cc ng nhp. Khi l Port nhp cc chn ca Port 1 ang c ko
xung mc thp do bn ngoi s cp dng do cc in tr bn trong ko ln. Cc chn
P1.0 v P1.1 ca Port 1 cng c dng cho cc chc nng T2 v T2EX. Cc chn
P1.5, P1.6, P1.7 l cc chn c dng cho cc chc nng MOSI, MISO, SCK iu
khin truyn v xut d liu cho vi iu khin. Cng dng chuyn i c lin h vi
cc t tnh ca AT89S8252 nh sau:
Bng 2.1: Chc nng chuyn i Port 1
Chc nng chuyn i
Bit
Tn
P1.0
T2
P1.1
T2EX
P1.4
P1.5
MOSI
Chn xut d liu Master, nhp d liu Slave
P1.6
MISO
Chn nhp d liu Master, xut d liu Slave
P1.7
SCK
Ng ra xung clock ca Master, ng vo xung clock Slave
Ng vo ca b nh thi/m 2
Np li/thu nhn ca b nh thi 2
Ng vo la chn cng Slave
Trang 8
Chn 9 (RST) l chn RESET cho AT89S8252. Bnh thng cc chn ny

mc thp. Khi ta a tn hiu ln mc cao (ti thiu 2 chu k my), th nhng thanh
ghi ni ca AT89S8252 c LOAD nhng gi tr thch hp khi ng li h
thng.
T chn 1017 l Port 3 (P3.1, P3.1, P3.7) dng vo hai mc ch: dng lm
Port xut nhp I/O hoc mi chn li gi mt chc nng c bit c tm tt s b
nh sau:
Bng 2.2: Cc chc nng chuyn i Port 3
Chc nng chuyn i
Bit
Tn
P3.0
RXD
D liu nhn cho port ni tip
P3.1
TXD
D liu pht cho port ni tip
P3.2
Ngt 0 bn ngoi
P3.3
Ngt 1 bn ngoi
P3.4
T0
Ng vo ca timer/counter 0
P3.5
T1
Ng vo ca timer/counter 1
P3.6
Xung ghi b nh d liu ngoi
P3.7
Xung c b nh d liu ngoi
Cc chn 18, 19 (XTAL2 v XTAL1) c ni vi b dao ng thch anh 12

MHz to dao ng trn Chp. Hai t 30 pF c thm vo n nh dao ng.
Hnh 2.2 Dao ng trn chip vi thch anh

Chn 20 (Vss) ni t (Vss = 0).
T chn 2128 l Port 2 ( P2.0, P2.1, , P2.7) dng vo hai mc nh: dng
lm Port xut nhp I/O hoc dng lm byte cao ca bus a ch th n khng cn tc
Trang 9
dng I/O na. Bi v ta mun EPROM v RAM ngoi nn phi s dng Port 2 lm
byte cao ca bus a ch.
Chn 29 () l tn hiu iu khin xut ra ca AT89S8252, n cho php
chn b nh ngoi v c ni chung vi chn ca OE (Out Enable) ca EPROM
ngoi cho php c cc byte ca chng trnh. Cc xung tn hiu h thp
trong sut thi gian thi hnh lnh. Nhng m nh phn ca chng trnh c c t
EPROM i qua bus d liu v c cht vo thanh ghi lnh IR ca AT89S8252 bi
m lnh. Khi thi hnh chng trnh trong ROM ni s mc th ng (mc
cao). Khi AT89S8252 ang thc thi lnh t b nh chng trnh ngoi, c
tch cc hai ln cho mi chu k my, ngoi tr thi gian mi ln truy xut b nh
d liu ngoi, hai ln tch cc ca c b qua.
Chn 30 (ALE/ : Adress Latch Enable) l tn hiu iu khin xut ra ca
AT89S8252, n cho php phn knh bus a ch v bus d liu ca Port 0. Cc xung
tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th dng lm
ngun xung nhp cho cc phn khc ca h thng. Nu nhp xung trn AT89S8252
l 12 MHz th ALE c tn s l 2MHz. Tuy nhin cn ch l mt xung ALE s b
mt khi truy xut b nh bn ngoi. C th hy b chc nng set ca bit 0 ca thanh
ghi SFR v tr 8EH. Khi bit ny c set, ALE ch tch cc khi c lnh MOVX
hoc MOVC, nu khng c lnh ny ALE mc cao. Vic set bit 0 ca thanh ghi
v tr 8EH khng lm nh hng n vi iu khin khi truy cp b nh ngoi.
Chn 31 (EA: Eternal Acess) c a xung thp cho php chn b nh m
ngoi i vi 8031.
i vi AT89S8252 th:
EA = 5V: Chn ROM ni.

EA=0V: Chn ROM ngoi.
EA=12V: Lp trnh EPROM ni.
Cc chn t 3239 l Port 0 (P0.0, P0.1, , P0.7) dng cho c hai mc ch:
va lm byte thp cho bus a ch, va lm bus d liu, nu Port 0 khng cn chc
nng xut nhp I/O na.
Chn 40 (Vcc) c ni ln ngun 5V.
Trang 10
2.3
T CHC B NH
Bn b nh data trn Chip nh sau:

7F
RAM a dng
30
2F
7F
7E
7D 7C
7B 7A 79
78
2E
77
76
75
73
71
70
2D
6F
6E
6D 6C
6B 6A 69
68
2C
67
66
65
63
61
60
2B
5F
5E
5D 5C
5B 5A 59
58
2A
57
56
55
53
51
50
29
4F
4E
4D 4C
4B 4A 49
48
28
47
46
45
43
41
40
27
3F
3E
3D 3C
3B 3A 39
38
26
37
36
35
33
31
30
25
2F
2E
2D 2C
2B 2A 29
28
24
27
26
25
23
21
20
23
1F
1E
1D 1C
1B 1A 19
18
22
17
16
15
13
11
10
21
0F
0E
0D 0C
0B 0A 09
08
20
07
06
05
03
00
1F
18
17
10
0F
08
74
64
54
44
34
24
14
04
72
62
52
42
32
22
12
02
01
Bank 3
Bank 2
Bank 1
07
Bank thanh ghi 0
00
(mc nh cho R0-R7)
Hnh 2.3: Cu trc b nh trn AT89S8252
Trang 11
2.3.1 RAM mc ch chung

Trong bn nh trn, 80 byte t a ch 30H7FH l RAM mc ch chung.
K c 32 byte phn di t 00H1FH cng c th s dng ging nh 80 byte trn,
tuy nhin 32 byte cn c mc ch khc s cp sau.
Bt k v tr no trong RAM mc ch chung cng c th c truy xut ty
ging nh vic s dng cc mode nh a ch trc tip hay gin tip. V d c
ni dung RAM ni c c ch 5FH vo thanh ghi tch ly th ta dng lnh
MOV A, 5FH.
Lnh ny chuyn 1 byte d liu dng cch nh a ch trc tip xc nh
a ch ngun (ngha l 5FH). ch nhn d liu c xc nh ngm trong m lnh
l thanh ghi tch ly A.
RAM ni cng c truy xut bi vic dng a ch gin tip qua R0 v R1.
Hai lnh sau y s tng ng lnh trn:
MOV R0, #5FH
MOV A, @R0
Lnh th nht dng s nh v tc thi a gi tr 5FH vo thanh ghi R0,
lnh th 2 dng s nh v gin tip a d liu c tr n bi R0 vo thanh
ghi tch ly A.
2.3.2 RAM nh v.
AT89S8252 cha 210 v tr c th nh v bit, trong c 128 bit nm cc a
ch t 20H2FH v phn cn li l cc thanh ghi chc nng c bit.
tng truy xut tng bit ring l bng phn mm l mt c tnh tin li
ca hu ht cc vi iu khin. Cc bit c th t, xo, AND, OR, vi mt lnh
n. Trong khi a s cc vi x l i hi mt chui lnh c-sa-ghi t
hiu qu tng t. Hn na cc port I/O cng c a ch ha theo bit a ch lm
n gin ha phn mm xut nhp tng bit.
C 128 bit a dng c a ch ha cc byte 20H n 2FH (8bit/byte x
16 bytes = 128 bits). Cc a ch ny c truy cp nh cc byte hoc nh cc bit ty
theo lnh s dng. V d, t bit 67H ln gi tr 1, c th dng lnh sau:
SETB 67H
Ch rng, a ch bit 67H l bit c trng s ln nht (MSB) a ch
byte 2CH. Lnh trn s khng tc ng n cc bit khc a ch ny.
2.3.3 Cc bng thanh ghi (Register Banks).
32 v tr nh cui cng ca b nh t a ch byte 00H1FH cha cc dy thanh
ghi. Tp hp cc lnh ca AT89S8252 cung cp 8 thanh ghi t R0R7 a ch
00H07H nu my tnh mc nhin chn thc thi. Nhng lnh tng ng dng s
nh v trc tip. Nhng gi tr d liu dc dng thng xuyn chc chn s s dng
mt trong cc thanh ghi ny.
Trang 12
Lnh sau s c a ch 05H vo thanh ghi tch ly:

MOV
A, R5
y l lnh 1 byte dng cch nh a ch thanh ghi. D nhin, cng tc v

c th thc hin bng lnh hai byte dng a ch trc tip nm trong byte th hai:
MOV
A, 05H
Cc lnh dng thanh ghi R0 n R7 th s ngn hn v nhanh hn cc

lnh tng ng nhng dng cch nh a ch trc tip. Cc gi tr d liu
c dng thng xuyn nn dng mt trong cc thanh ghi ny.
Bng thanh ghi tch cc c th chuyn i bng cch thay i cc bit chn
bng thanh ghi trong t trng thi chng trnh (PSW). Gi s rng thanh ghi
3 c tch cc, lnh sau s ghi ni dung ca thanh ghi tch ly vo a ch 18H:
MOV
R0, A
tng dng cc bng thanh ghi cho php chuyn ng cnh chng trnh
nhanh v hiu qu m tng phn ring r ca phn mm s c mt b thanh
ghi ring c lp vi cc phn khc.
2.3.4 Cc thanh ghi chc nng c bit (Special Function Register).
Trang 13
Hnh 2.4: Bn cc thanh ghi c bit

Cc thanh ghi trong AT89S8252 c t cu hnh nh mt phn ca RAM
trn chip. V vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi m chng
trnh v thanh ghi lnh v cc thanh ghi ny him khi b x l trc tip, nn khng c
li g khi t chng trong RAM trn chip). l l do m AT89S8252 khng c
nhiu thanh ghi. C 33 thanh ghi chc nng c bit SFR nh ca RAM ni t a
ch cc thanh ghi chc nng c bit c nh r, cn phn cn li khng nh r.
Mc d thanh ghi A c th truy xut trc tip nhng hu ht cc thanh ghi chc
nng c bit c truy sut bng cch s dng s nh v a ch trc tip. Ch rng
vi thanh ghi SFR c c bit nh v v c byte nh v. Ngi thit k s cn thn khi
truy xut bit m khng truy xut byte.
2.3.4.1 T trng thi chng trnh (PSW: Program Status Word):
T trng thi chng trnh a ch D0H c tm tt nh sau:
Bng 2.3: Tm tt thanh ghi PSW
BIT
SYMBOL
ADDRESS
DESRIPTION
PSW.7
CY
D7H
Carry Flag
PSW.6
AC
D6H
Auxiliary Carry Flag
Trang 14
PSW.5
F0
D5H
Flag 0
PSW.4
RS1
D4H
Register Bank Select 1
PSW.3
RS0
D3H
Register Bank Select 0

00: Bank 0; Address 00H07H
01: Bank 1; Address 08H0FH
10: Bank 2; Address 10H17H
11: Bank 3; Address 18H1FH
PSW.2
OV
D2H
Overlow Flag
PSW.1
D1H
Reserved
PSW.0
D0H
Even Parity Flag
Chc nng tng bit trng thi chng trnh.
C Carry CY (Carry Flag):
C Carry c set ln 1 nu c s trn bit 7 trong php cng hoc c s

mn vo bit 7 trong php tr.
C Carry cng l 1 thanh ghi tch ly lun l, n c dng nh mt thanh
ghi 1 bit thc thi trn cc bit bi nhng lnh lun l. V d lnh: ANL C,25H s AND
bit 25H vi c Carry v cp kt qu vo c Carry.
C Carry ph AC (Auxiliary Carry Flag):
Khi cng nhng gi tr BCD (Binary Code Decimal), c nh ph AC c set

nu c s trn t bit 3 sang bit 4 hoc 4 bit thp nm trong phm vi 0AH0FH.
C 0 (Flag 0):
C 0 (F0) l c c mc ch tng hp cho php ngi ng dng dng n.

d). Nhng bit chn dy thanh ghi RS1 v RS0:
RS1 v RS0 quyt nh chn dy thanh ghi tch cc. Chng c xa sau khi
reset h thng v c thay i bi phn mm khi cn thit.
C trn OV (Over Flag):
C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc. Bit
OV c b qua i vi s cng tr khng du. Khi cng tr c du, kt qu ln hn
+127 hay nh hn -128 s set bit OV.
Bit Parity (P):
Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh

ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A
cha 10101101B th bit P set ln mt tng s bit 1 trong A v P tp thnh s chn.
Trang 15
Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni

tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.
2.3.4.2
Thanh ghi B:
Thanh ghi B c ch F0H c dng i i vi thanh ghi A cho cc hot ng

nhn chia.
Thanh ghi B c th c dng nh mt thanh ghi m trung gian a mc ch.
N l nhng bit nh v thng qua nhng a ch F0HF7H.
2.3.4.3 Con tr Stack SP (Stack Pointer):
Stack Pointer l mt thanh ghi 8 bit a ch 81H. N cha a ch ca d liu
ang hin hnh trn nh Stack. Cc hot ng ca Stack bao gm vic y d liu vo
Stack (PUSH) v ly d liu ra khi Stack (POP).
Vic PUSH vo Stack s tng SP ln 1 trc khi d liu vo.
Vic POP t Stack ra s ly d liu ra trc ri gim SP i 1.
2.3.4.4 Hai con tr d liu DPTR (Data Pointer)
Data Pointer c truy xut b nh m ngoi hoc b nh d liu ngoi, n
l hai thanh ghi 16 bit m byte thp l DP0L a ch 82H cn byte cao l DP0H a
ch 83H, 84H (DP1L l byte thp) v 85H (DP1H l byte cao). a ni dung 55H
vo RAM ngoi c c ch 1000H ta dng 3 lnh sau:
MOV A,#55H
MOV DPTR,#1000H
MOVX @ DPTR,A
Lnh th nht dng s nh v trc tip a hng s 55H vo A. Lnh th hai
cng tng t lnh th nht a hng s d liu 1000H vo trong DPTR. Lnh cui
cng dng s nh v gin tip chuyn dch gi tr 55H trong A vo vng nh RAM
ngoi nm trong DPTR.
2.3.4.5 Cc thanh ghi Port (Port Register):
Cc Port 0, Port 1, Port 2, Port 3 c cc a ch tng ng 80H, 90H, A0H,
B0H. Cc Port 0, Port 1, Port 2, Port 3 khng cn tc dng xut nhp na nu b nh
ngoi c dng hoc mt vi c tnh c bit ca AT89S8252 c dng (nh
Interrupt, Port ni tip,...). Do vy ch cn c Port 1 c tc dng xut nhp I/O.
Tt c cc Port u c bit a ch, do n c kh nng giao tip vi bn ngoi
mnh m.
2.3.4.6 Cc thanh ghi Timer (Timer Register):
AT89S8252 cha 3 b nh thi / m 16 bit c dng cho vic nh thi
hoc m s kin. Timer 0 a ch 8AH (TL0 l byte thp) v 8CH (TH0 l byte
cao). Timer 1 a ch 8BH (TL1 l byte thp) v 8DH (TH1 l byte cao). Timer 2
a ch CCH (TL2 l byte thp) v CDH (TH2 l byte cao).
Trang 16
Hot ng ca Timer 0 v Timer 1 ca AT89S8252 th ging nh hot ng

ca Timer 0 v Timer 1 ca AT89C51. Hot ng ca Timer 0 v Timer 1 c
t bi thanh ghi Timer Mode (TMOD) a ch 89H v thanh ghi iu khin Timer
(TCON) a ch 88H. Hot ng ca Timer 2 c t bi cc thanh ghi
T2MOD a ch C9H v thanh ghi iu khin T2CON a ch C8H. Cc Timer
c bn chi tit phn sau.
2.3.4.7 Cc thanh ghi Port ni tip (Serial Port Register):
AT89S8252 cha mt Port ni tip trn Chip cho vic truyn thng tin vi
nhng thit b ni tip nh l nhng thit b u cui, modem, hoc giao tip IC
khc vi nhng b bim i A/D, nhng thanh ghi di chuyn, RAM,... Thanh ghi m
d liu ni tip SBUF c ch 99H gi c d liu pht ln d liu thu. Vic ghi ln
SBUF LOAD d liu cho vic truyn v c SBUF truy xut d liu cho vic
nhn nhng mode hot ng khc nhau c lp trnh thng qua thanh ghi diu khin
Port ni tip SCON.
2.3.4.8 Cc thanh ghi ngt (Interrupt Register):
AT89S8252 c hai cu trc ngt u tin, 6 b ngun ngt. Nhng Interrupt b
mt tc dng sau khi h thng reset (b cm) v sau c cho php ghi ln thanh
ghi cho php ngt IE (Interrupt Enbale Register) a ch A8H. Mc u tin c t
vo thanh ghi u tin ngt IP (Interrupt Priority Level) ti a ch B8H. C hai thanh
ghi trn u c bit a ch.
V tr cc bit nh sau:
EA
ET2
ES
ET1
EX1
ET0
EX0
Bit = 1 cho php.

Bit = 0, khng cho php.
Chc nng ca tng bit nhu sau:
Bng 2.4: Tm tt thanh ghi IE (Interrupt Register)
Bit
V tr
M t
EA
IE.7
Khng cho php tt c cc ngt. Nu EA=0, khng

cho php ngt, nu EA=1 mi ngun ngt s c
kch hot hay tt bi vic thit lp hay xa cc bit cho
php ca n.
IE.6
Reserved
ET2
IE.5
Bit cho php Timer 2 ngt
ES
IE.4
Bit cho php ngt SPI v UART
ET1
IE.3
Bit cho php Timer 1 ngt.
Trang 17
EX1
IE.2
Bit cho php ngt ngoi 1
ET0
IE.1
Bit cho php Timer 0 ngt.
EX0
IE.0
Bit cho php ngt ngoi 0
2.3.4.9 Thanh ghi iu khin ngun PCON (Power Control Register):

Thanh ghi PCON khng c bit nh v. N a ch 87H bao gm cc bit tng
hp. Cc bit PCON c tm tt nh sau:
Bng 2.5: Tm tt thanh ghi PCON
Bit
K hiu
M t bit
SMOD
Bit tng gp i tc baud; khi c t ln 1 th tc

baud c tng gp i trong ch cng ni tip 1, 2 hoc
3.
Khng c nh ngha.
Khng c nh ngha.
POF
C ngt ngun (Power Off Flag). POF = 1 khi ngun tng.

POF c th set v reset bng phn mm iu khin, khng b
nh hng bi reset.
GF1
C a dng (General Purpose Flag), bit 1.
GF0
C a dng, bit 0.
PD
Ch tt ngun (Power Down); c t ln 1 kch

hot ch tt ngun, ch thot khi b xo v 0.
IDL
Ch ngh; c t ln 1 kch hot ch ngh, ch

thot khi c ngt hoc reset h thng.
Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC

MSC-51 nhng ch c thi hnh trong s bin dch ca CMOS.
Ch ngh Idel: Lnh t bit IDL ln 1 s l lnh cui cng c thc thi
trc khi vo ch ngh. Trong ch ngh, tn hiu xung nhp bn trong khng
cung cp cho CPU m ch cung cp cho cc chc nng ngt, nh th v cng ni
tip. Trng thi CPU v tt c ni dung cc thanh ghi c gi nguyn. Cc chn
cc cng cng gi nguyn mc logic ca chng. Tn hiu ALE v c gi mc
cao. Ch ngh b kt thc bi bt c ngt no c cho php hoc bi reset h
thng. C hai iu kin ny xo bit IDL v 0.
Ch tt ngun Power Down: Lnh t bit PD ln 1 s l lnh cui cng
c thc thi trc khi vo ch tt ngun.Trong ch tt ngun:
Trang 18
Dao ng trn chip b dng.

Tt c cc chc nng b dng.
Tt c cc ni dung ca RAM trn chip c gi nguyn.
Cc chn cng cng gi nguyn cc mc logic ca chng.
Tn hiu ALE v c gi mc thp.
Cch duy nht thot khi ch ny l reset h thng.

Trong ch tt ngun, Vcc c th thp c 2V. Ch l ch c th h Vcc
sau khi vo ch tt ngun v phc hi Vcc v 5V t nht 10 chu k dao ng
trc khi chn RST xung thp ln na (khi ri khi ch tt ngun).
2.3.4.10
Thanh ghi iu khin b nh v kim sot gi (WMCON)
Thanh ghi WMCON (Watchdog And Memory Control Register) a ch 96H

cha cc bit iu khin cho Watchdog Timer c trnh by bng sau. Cc bit
EEMEN v EEMWE c s dng la chn 2 KB trn chip EEPROM v c th
ghi byte. Bit DPS c s dng la chn 1 trong 2 thanh ghi con tr d liu.
Bng 2.6: Thanh ghi iu khin b nh v Watchdog
Bit
K hiu
Chc nng
PS2
PS1
PS0
Khi tt c 3 bit ny c t v 0, nh thi Watchdog c

chu k l 16s, khi tt c 3 bit ny t ln 1, nh thi
Watchdog c chu k 2048s
EEMWE
Bit ghi b nh d liu EEPROM (EEPROM Data Memory

Enable). Bit ny c t ln 1 trc khi byte u tin ghi
ln chip EEPROM bng lnh MOVX. Nn dng phn mm
s dng t bit ny v 0 sau khi EEPROM ghi xong.
EEMEN
Bit Truy Nhp Eeprom Bn Trong (Internal Eeprom Asscess

Enable).Khi EEMEN = 1, lnh MOVX vi con tr d liu
DPTR truy cp EEPROM thay v l truy cp b nh d liu
bn ngoi. Khi EEMEN = 0, lnh MOVX vi DPTR truy cp
d liu bn ngoi.
DSP
Bit chn thanh ghi con tr d liu (Data Pointer Register

Select). Khi DPS = 0 chn bng u tin ca thanh ghi con
tr d liu DP0. Khi DSP = 1 chn bng th hai PD1.
WDTRST
RDY/
Bit reset nh thi watchdog v c bo Ready/ ca

EEPROM (Watchdog Timer Reset and EEPROM
Ready/ Flag). Mi ln bit ny c t ln 1 bng phn
mm th s c mt xung pht ra reset nh th watchdog.
Khi , bit WDTRST s t ng reset v 0 trong chu k lnh
Trang 19
k tip. Bit WDTRST l bit ch dng ghi. Bit ny cng l

c bo sn sng/bn RDY/ dng trong b nh ch c
trong sut qu trnh ghi EEPROM. RDY/ = 1, EEPROM
sn sng c lp trnh. Trong khi hot ng lp trnh
ang c thc hin, bit RDY/ s bng 0 v t ng
reset v 1 khi lp trnh kt thc.
0
WDTEN
2.3.4.11
Interface)
Bit cho php nh thi watchdog (Watchdog Timer Enable

Bit). WDTEN = 1 cho php nh thi watchdog, WDTEN = 0
khng cho php nh thi watchdog
Thanh ghi giao tip ni tip bn ngoi SPI (Serial Peripheral
Bit trng thi v iu khin cho SPI c cha trong thanh ghi SPCR a
ch D5H trnh by bng 2.6 v SPSR a ch AAH trnh by bng 2.7. Cc bit d
liu SPI cha trong thanh ghi SPDR a ch 86H. Thanh ghi d liu SPI s ghi d
liu trong sut qu trnh truyn d liu ni tip t vo bit WCOL (Write Collition)
trong thanh ghi SPSR. Thanh ghi SPDR l b m i ghi v gi tr trong SPDR
khng b thay i khi reset.
Bng 2.7: Thanh ghi iu khin SPI
Bit
K hiu
Chc nng
SPIE
Bit cho php ngt SPI (SPI Interrupt Enable). Bit ny cng vi bit
ES trong thanh ghi IE bng 1 cho php ngt SPI. SPIE bng 0
khng cho php ngt SPI.
SPE
Bit cho php SPI (SPI Enable). SPI = 1 cho php knh SPI v kt
ni , MOSI, MISO v SCK n cc chn P1.4, P1.5, P1.6 v
P1.7. SPI = 0 khng cho php knh SPI.
DORD
DORD = 1 chn truyn d liu th nht LSB. DORD = 0 chn

truyn d liu th nht MSB.
MSTR
MSTR = 1 chn kiu Master SPI. MSTR = 0 chn kiu Slave SPI.
CPOL
Khi CPOL = 1, SCK mc cao khi ch ngh. Khi CPOL =

0, SCK mc thp khi khng c truyn thng tin.
CPHA
Bit CPOL v bit CPHA iu khin xung clock v d liu lien

quan gia Master v Slave.
SPR0
SPR1
Hai bit ny iu khin tc SCK ca thit b kt ni Master.

Mi quan h gia SCK v tn s FOSC l:
SPR1
SPR0
SCK = FOSC
Trang 20
16
64
128
Bng 2.8: Thanh ghi trng thi SPI

Bit
K hiu
Chc nng
SPIF
C ngt SPI (SPI Interrupt Flag). Khi s truyn d liu ni tip

hon tt, bit SPIF c t v mt xung ngt pht ra nu SPIE = 1
v ES = 1.
WCOL
Bit WCOL c t nu thanh ghi d liu SPI c ghi trong khi

d liu c truyn. Trong khi truyn d liu, kt qu c ca
thanh ghi SPDR c th khng ng v qu trnh ghi khng b nh
hng.
2.4
TM TT TP LNH CA AT89S8252
Cc chng trnh c cu to t nhiu lnh , chng c xy dng logic,s

ni tip ca cc lnh c ngh ra mt cch hiu qu v nhanh,kt qu ca chng
trnh th kh quan.
Tp lnh h MSC-51 c s kim tra ca cc mode nh v v cc lnh ca
chng c cc Opcode 8 bit.iu ny cung cp kh nng 2 8=256 lnh c thi hnh v
mt lnh khng c nh ngha. Vi lnh c 1 hoc 2 byte bi d liu hoc a ch
thm vo Opcode. Trong ton b cc lnh c 139 lnh 1 byte,92 lnh 2 byte v 24 lnh
3 byte.
2.4.1 Cc ch nh v ( addressing mode )
Cc mode nh v l mt b phn thng nht ca tp lnh mi my tnh. Chng
cho php nh r ngun hoc ni gi ti ca d liu cc ng khc nhau ty thuc
vo trng thi ca lp trnh. AT89S8252 c 8 mode nh v c dng nh sau:
Thanh ghi.
Trc tip.
Gin tip.
Tc thi.
Tng i.
Tuyt i.
Di.
nh v.
2.4.1.1 S nh v thanh ghi ( Register Addressing)
Vi cch nh a ch ny ngi ta s dng cc thanh ghi cha d liu.
Ngi ta t ton hng (d liu) trong thanh ghi v x l n bng cch tham chiu
Trang 21
thanh ghi (bng tn) trong lnh. Khi s dng cc thanh ghi thng dng c hiu
ngm theo ng cnh ca lnh th thanh ghi khng cn cc bit m ha, tuy nhin
vi cc thanh ghi khc (R0 R7) th cn thm cc bit m ha trong lnh.
C 4 dy thanh ghi 32 byte u tin ca RAM d liu trn Chip a ch
00H1FH, nhng ti mt thi im ch c mt dy hot ng cc bit PSW3, PSW4
ca t trng thi chng trnh s quyt nh dy no hot ng. Cc lnh nh v
thanh ghi c ghi mt m bng cch dng bit trng s thp nht ca Opcode lnh
ch mt thanh ghi trong vng a ch theo logic ny. Nh vy 1 m chc nng v a
ch hot ng c th c kt qu to thnh mt lnh ngn 1 byte nh sau:
n
Opcode
2.4.1.2 S nh a ch trc tip ( Direct Addressing )

S nh a ch trc tip c th truy xut bt k gi tr no trn Chip hoc thanh
ghi phn cng trn Chip. Mt byte a ch trc tip c a vo Opccode nh r
v tr c dng nh sau:
Opcode
Direct Addressing
Ty thuc cc bit bc cao ca a ch trc tip m 1 trong 2 vng nh c

chn. Khi bit 7 = 0, th a ch trc tip trong khong 0127 (00H7FH) v 128 v tr
nh thp ca RAM trn Chip c chn. Tuy nhin, tt c cc I/O v cc SFR, cc
thanh ghi trng thi, iu khin c a ch trong khong 80H FFH. Khi MSB ca a
ch trc tip l 1 th truy cp n cc SFR. Th d cng P0 v P1 c a ch trc tip
tng ng l 80H v 90H. Khng nht thit nh cc a ch ny v trnh hp ng
cho php v hiu cc vit tt gi nh cho chng (v d P0 ch Port 0, TMOD ch
thanh ghi ch timer, ).
2.4.1.3 S nh v a ch gin tip ( Indirect Addressing)
S nh v a ch gin tip c tng trng bi k hiu @ c t trc R0,
R1 hay DPTR. R0 v R1 c th hot ng nh mt thanh ghi con tr m ni dung ca
n cho bit mt a ch trong RAM ni ni m d liu c ghi hoc c c. Bit
c trng s nh nht ca Opcode lnh s xc nh R0 hay R1 c dng con tr
Pointer.
Trang 22
Opcode
V d a ni dung 60 H vo RAM ni ti a ch 50 H ta lm nh sau:

MOV R1, #50H
MOV @R1, 60H
2.4.1.4 S nh v a ch tc thi (Immediate Addressing)
Khi ton hng ngun l hng s ch khng phi l bin th c th a hng
s vo lnh nh byte d liu tc thi. S nh a ch tc thi c tng trng bi
k hiu # c ng trc 1 hng s,1 bin k hiu hoc 1 biu thc s hc c s
dng bi cc hng , cc k hiu, cc hot ng do ngi iu khin. Trnh bin dch
tnh ton gi tr hay thay th d liu tc thi. Byte lnh thm vo cha tr s d liu
tc thi nh sau:
Opcode
Immediate Data
V d:
MOV A, #12 <= a trc tip s thp phn 12 vo A
MOV A, #10 <= a trc tip s Hex 10H (16D) vo A
MOV A, #000100110B <= a trc tip s nh phn ny vo A
2.4.1.5 S nh v a ch tng i
S nh a ch tng i ch s dng vi nhng lnh nhy no . Mt a ch
tng i ( hoc Offset ) l 1 gi tr 8 bit m n c cng vo b m chng trnh
PC to thnh a ch 1 lnh tip theo c thc thi. Phm vi ca s nhy nm trong
khong -128 127. Offset tng i c gn vo lnh nh 1 byte thm vo nh sau:
Opcode
Relative Offset
Trang 23
S nh v tng i em li thun li cho vic cung cp m v tr c lp,

nhng bt li l ch nhy ngn trong phm vi -128 127 byte.
2.4.1.6 S nh a ch tuyt i ( Absolute Addressing)
S nh a ch tuyt i c dng vi cc lnh ACALL v AJMP. Cc lnh 2
byte cho php phn chia trong trang 2K ang lu hnh ca b nh m ca vic cung
cp 11 bit thp nht xc nh a ch trong trang 2K (A0A10 gm A10A8 trong
Opcode v A7A0 trong byte ) v 5 bit cao chn trang 2K (5 bit cao ang lu hnh
trong b m chng trnh l 5 bit Opcode).
Opcode
Addr 10 Addr 8
Addr 7 Addr 0
S nh v tuyt i em li thun li cho cc lnh ngn ( 2 byte ), nhng bt
li trong vic gii hn phm vi ni gi n v cung cp m c v tr c lp.
2.4.1.7 S nh v a ch di ( Long Addressing )
S nh v di c dng vi lnh LCALL v LJMP. Cc lnh 3 byte ny bao
gm 1 a ch ni gi ti 16 bit y l 2 byte v 3 byte ca lnh.
Opcode
Addr 15 Addr 8
Addr 7 Addr 0
u im ca s nh di l vng nh m 64K c th c dng ht, nhc

im l cc lnh di 3 byte v v tr l thuc. S ph thuc vo v tr s bt li bi
chng trnh khng th thc thi ti a ch khc.
2.4.1.8 S nh a ch ph lc (Index Addressing )
S nh a ch ph lc dng 1 thanh ghi c bn ( cng nh b m chng
trnh hoc b m d liu ) v Offset ( thanh ghi A) trong s hnh thnh 1 a ch lien
quan bi lnh JMP hoc MOVC.
Base Register
PC (or DPTR)
Offset
Effective Address
ACC
Trang 24
Index Addressing
2.4.2 Cc kiu lnh (instruction types)
AT89S8252 chia ra 5 nhm lnh chnh:
Cc lnh s hc.
Lnh logic.
Dch chuyn d liu.
L lun.
R nhnh chng trnh.
Tng kiu lnh c m t nh sau:

2.4.2.1 Cc lnh s hc (Arithmetic Instrustion):
ADD A, <src, byte>

ADD
A, Rn
: (A) (A) + (Rn)
ADD
A, direct
: (A) (A) + (direct)
ADD
A, @ Ri
: (A) (A) + ((Ri))
ADD
A, # data
: (A) (A) + # data
ADDC
A, Rn
: (A) (A) + (C) + (Rn)
ADDC
A, direct
: (A) (A) + (C) + (direct)
ADDC
A, @ Ri
: (A) (A) + (C) + ((Ri))
ADDC
A, # data
: (A) (A) + (C) + # data
SUBB A, <src, byte>
SUBB A, Rn
: (A) (A) (C) (Rn)
SUBB A, direct
: (A) (A) (C) (direct)
SUBB A, @ Ri
: (A) (A) (C) ((Ri))
SUBB A, # data
: (A) (A) (C) # data
INC <byte>
INC
: (A) (A) + 1
INC
direct
: (direct) (direct) + 1
INC
Ri
: ((Ri)) ((Ri)) + 1
INC
Rn
: (Rn) (Rn) + 1
INC
DPTR
: (DPTR) (DPTR) + 1
DEC <byte>
DEC
: (A) (A) 1
DEC
direct
: (direct) (direct) 1
DEC
@ Ri
: ((Ri)) ((Ri)) 1
Trang 25
DEC
Rn
: (Rn) (Rn) 1
MULL
AB
: (A) LOW [(A) x (B)], c nh hng c OV

: (B) HIGH [(A) x (B)], c Carry c xa.
DIV
AB
: (A) Integer Result of [(A)/(B)], c OV

: (B) Remainder of [(A)/(B)], c Carry xa.
DA
A
: iu chnh thanh ghi A thnh s BCD ng trong
php cng BCD (thng DA A di km vi ADD, ADDC)
Nu [(A3 A0) > 9] v [(AC) = 1] <= (A3A0) (A3A0) + 6
Nu [(A7 A4) > 9] v [(C) = 1] <= (A7A4) (A7A4) + 6
2.4.2.2 Cc hot ng logic (Logic Operation):
Tt c cc lnh logic s dng thanh ghi A nh l mt trong nhng ton hng
thc thi mt chu k my, ngoi A mt hai chu k my. Nhng hot ng logic c th
c thc hin trn bt k byte no trong v tr nh d liu ni m khng qua thanh
ghi A.
Cc hot ng logic c tm tt nh sau:
ANL <dest byte > <src byte>
ANL
A, Rn
: (A) (A) AND (Rn).
ANL
A, direct
: (A) (A) AND (direct).
ANL
A, @ Ri
: (A) (A) AND ((Ri)).
ANL
A, # data
: (A) (A) AND (# data).
ANL
direct, A
: (direct) (direct) AND (A).
ANL
direct, # data : (direct) (direct) AND # data.
ORL <dest byte> <src byte>
ORL
A, Rn
: (A) (A) OR (Rn).
ORL
A, direct
: (A) (A) OR (direct).
ORL
A, @ Ri
: (A) (A) OR ((Ri)).
ORL
A, # data
: (A) (A) OR # data.
ORL
direct, A
: (direct) (direct) OR (A).
ORL
direct, # data : (direct) (direct) OR # data.
XRL <dest byte> <src byte>
XRL
A, Rn
: (A) (A) ) (Rn).
XRL
A, direct
: (A) (A) ) (direct).
XRL
A, @ Ri
: (A) (A) ) ((Ri)).
XRL
A, # data
: (A) (A) ) # data.
XRL
direct, A
: (direct) (direct) ) (A).

Trang 26

XRL
direct, # data : (direct) (direct) ) # data.

Y = a ) b = ab + ab
CLR
: (C) 0.
CLR
Bit
: (Bit) 0.
RL
: quay vng thanh ghi A qua tri 1 bit

(An + 1) (An), n = 06
(A0) (A7)
RLC
: quay vng thanh ghi A qua tri 1 bit c c Carry

(An + 1) (An), n = 06
(C) (A7)
(A0) (C)
RR
: quay vng thanh ghi A qua phi 1 bit

(An + 1) (An), n = 06
(A0) (A7)
RRC
: quay vng thanh ghi A qua phi 1 bit c c Carry

(An + 1) (An), n = 06
(C) (A7)
(A0) (C)
SWAP
: i ch 4 bit thp v 4 bit cao ca A cho nhau

(A3A0)(A7A4)
2.4.2.3 Cc lnh r nhnh

C nhiu lnh diu khin r nhnh ln chng trnh bao gm vic gi hoc
tr li t chng trnh con hoc chia nhnh c iu kin hay khng c diu kin.
Tt c cc lnh r nhnh u khng nh hng n c. Ta c th nh nhn cn
nhy ti m khng cn ch r a ch, trnh bin dch s t a ch ni cn nhy ti vo
ng khu lnh a ra.
Sau y l s tm tt tng loi hot ng nhy.
JC
rel
: nhy n rel nu c Carry C = 1.
JNC
rel
: nhy n rel nu c Carry C = 0.
JB
bit, rel : nhy n rel nu (bit) = 1.
JNB
bit, rel : nhy n rel nu (bit) = 0.
JBC
bit, rel : nhy n rel nu bit = 1 v xa bit.
ACALL
addr11
: lnh gi tuyt i trong page 2K.

(PC) (PC) + 2
(SP) (SP) + 1
Trang 27

((SP)) (PC7PC0)
(SP) (SP) + 1
((SP)) (PC15PC8)
(PC10PC0) page address
LCALL
addr16
: lnh gi di chng trnh con trong 64K

(PC) (PC) + 3
(SP) (SP) + 1
((SP)) (PC7PC0)
(SP) (SP) + 1
((SP)) (PC15PC8)
(PC) Addr15Addr0
: kt thc chng trnh con tr v chng trnh
RET
chnh.
(PC15PC8) (SP)
(SP) (SP) 1
(PC7PC0) ((SP))
(SP) (SP) 1
RETI
: kt thc th tc phc v ngt quay v chng trnh
chnh hot ng tng t nh RET.
AJMP
Addr11
: nhy tuyt i khng iu kin trong 2K

(PC) (PC) + 2
(PC10PC0) page Address
LJMP
Addr16
: nhy di khng iu kin trong 64K

Hot ng tng t nh LCALL.
SJMP
rel
: nhy ngn khng iu kin trong (-128127) byte

(PC) (PC) +2
(PC) (PC) + byte 2
JMP @ A + DPTR : nhy khng iu kin n a ch (A) + (DPTR)

(PC) (A) + (DPTR)
JZ
rel
: nhy n A = 0. Thc hnh lnh k nu A 0.

(PC) (PC) + 2
(A)= 0 <= (PC) (PC) + byte 2
JNZ
rel
: nhy n A 0. Thc hnh lnh k nu A = 0.

(PC) (PC) + 2
(A)< > 0 <= (PC) (PC) + byte 2
Trang 28

CJNE

: so snh v nhy n A direct
A, direct, rel
(PC) (PC) + 3
(A)< > (direct) <= (PC) (PC) + Relative Address
(A)< (direct) <= C = 1
(A)> (direct) <= C = 0
(A)= (direct). Thc hnh lnh k tip.
CJNE
A, # data, rel : tng t lnh CJNE A, direct, rel.
CJNE
Rn, # data, rel
: tng t lnh CJNE A, direct, rel.
CJNE
@ Ri, # data, rel
: tng t lnh CJNE A, direct, rel.
DJNE
Rn, rel
: gim Rn v nhy nu Rn 0.
(PC) (PC) + 2
(Rn) (Rn) 1
(Rn) < > 0 <= (PC) (PC) + byte 2
DJNZ direct, rel
: tng t lnh DJNE Rn, rel.
2.4.2.4 Cc lnh dch chuyn d liu.

Cc lnh dch chuyn d liu trong nhng vng nh ni thc thi 1 hoc 2 chu
k my. Mu lnh MOV <destination>, <source> cho php di chuyn d liu bt k 2
vng nh no ca RAM ni hoc cc vng nh ca cc thanh ghi c bit m khng
thng qua thanh ghi A.
Vng Stack ca AT89S8252 ch cha 128 byte RAM ni, nu con tr Stack SP
c tng qu ch 7FH th cc byte c PUSH vo s mt i v cc byte POP ra th
khng bit r.
Cc lnh dch chuyn b nh ni v b nh ngoi dng s nh v gin tip. a
ch gin tip c th dng a ch 1 byte (@ RI) hoc a ch 2 byte (@ DPTR). Tt c
cc lnh dch chuyn hot ng trn ton b nh ngoi thc thi trong 2 chu k my v
dng thnh ghi A l ton hng DESTINATION.
Vic c v ghi RAM ngoi (RD v RW) ch tch cc trong sut qu trnh thc
thi ca lnh MOVX, cn bnh thng RD v RW khng tch cc (mc 1).
Tt c cc lnh dch chuyn u khng nh hng n c. Hot ng ca tng
lnh c tm tt nh sau:
MOV
A, Rn
: (A) (Rn)
MOV
A, direct
: (A) (direct)
MOV
A, @ Ri
: (A) ((Ri))
MOV
A, # data
: (A) # data
MOV
Rn, A
: (Rn) (A)
MOV
Rn, direct
: (Rn) (direct)
Trang 29
MOV
Rn, # data
: (Rn) # data
MOV
direct, A
: (direct) (A)
MOV
direct, Rn
: (direct) (Rn)
MOV
direct, direct
: (direct) (direct)
MOV
direct, @ Ri
: (direct) ((Ri))
MOV
direct, # data : (direct) # data
MOV
@ Ri, A
: ((Ri)) (A)
MOV
@ Ri, direct
: ((Ri)) (direct)
MOV
@ Ri, # data
: ((Ri)) # data
MOV
DPTR, # data 16
: (DPTR) # data 16
MOV
A, @ A + DPTR
: (A) (A) + (DPTR)
MOV
@ A + PC
: (PC) (PC) + 1
(A) (A) + (PC)
MOVX
A, @ Ri
: (A) ((Ri))
MOVX
A, @ DPTR
: (A) ((DPTR))
MOVX
@ Ri, A
: ((Ri)) (A)
MOVX
@ DPTR, A
: (DPTR) (A)
PUSH
direct
: ct d liu vo Stack
(SP) (SP) + 1
(SP) (direct)
POP
direct
: ly t Stack ra direct
(direct) ((SP))
(SP) (SP) 1
XCH
A, Rn
: i ch ni dung ca A vi Rn
(A) (Rn)
XCH
A, direct
: (A) (direct)
XCH
A, @ Ri
: (A) ((Ri))
XCHD
A, @ Ri
: i ch 4 bit thp ca (A) vi ((Ri))

(A3A0) ((Ri3Ri0))
2.4.2.5 Cc lnh lun l (Boolean Instruction)

AT89S8252 cha mt b x l lun l y cho cc hot ng bit n. y l
mt im mch ca h vi iu khin MSC-51 m cc h x l khc khng c.
RAM ni cha 128 bit n v v cc vng nh cc thanh ghi chc nng c bit
cp ln n 128 bit n v khc. Tt c cc ng Port l bt nh v, mi ng c th
c x l nh Port n v ring bit. Cch truy xut cc bit ny khng ch cc lnh r
Trang 30
nhnh khng, m l mt danh mc y cc lnh MOVE, SET, CLEAR,

COMPLEMENT, OR, AND.
Ton b s truy xut ca bit dng s nh v trc tip vi nhng a ch t
00H7FH trong 128 vng nh thp v 80HFFH cc vng thanh ghi chc nng c
bit.
Bit Carry C trong thanh ghi ca t trng thi chng trnh v c dng
nh mt s tch ly n ca b x l lun l. Bit Carry cng l bit nh v v c a
ch trc tip v n nm trong . Hai lnh CLR C v CLR CY u c tc dng l
xa bit c Carry nhng lnh ny mt 1 byte cn lnh sau mt 2 byte.
Hot ng ca cc lnh lun l c tm tt nh sau:
CLR
: xa c Carry xung 0. C nh hng c Carry.
CLR
BIT
: xa bit xung 0. Khng c nh hng c Carry.
SET
: set c Carry ln 1. C nh hng c Carry.
SET
BIT
: set bit ln 1. Khng nh hng c Carry.
CPL
: o bt c Carry. C nh hng c Carry.
CPL
BIT
: o bit. Khng nh hng c Carry
ANL
C, BIT
: (C) (C) AND (BIT). C nh hng c Carry.
ANL
C, /BIT
: (C) (C) AND NOT (BIT). Khng nh hng c
ORL
C, BIT
: (C) (C) OR (BIT). Tc ng c Carry.
ORL
C, /BIT
: (C) (C) OR NOT (BIT). Tc ng c Carry.
MOV
C, BIT
: (C) (BIT). C Carry b tc ng.
MOV
BIT, C
: (BIT) (C). Khng nh hng c Carry.
Carry.
2.5
HOT NG CA PORT NI TIP AT89S8252.
2.5.1 Gii thiu

Hot ng port ni tip ca AT89S8252 cng ging nh hot ng ni tip ca
h 8051, v th ta s xt Port ni tip AT89S8252 nh h 8051.
Port ni tip ca AT89S8252 c th hot ng trong cc mode ring bit trn
phm vi cho php ca tn s. Chc nng ch yu ca Port ni tip l thc hin s
chuyn i song song thnh ni tip cho d liu ra v s chuyn i ni tip thnh
song song cho d liu vo.
Phn cng truy xut ti Port ni tip qua cc chn TXD (P3.1) v RXD (P3.0).
Port ni tip tham d hot ng y ( s pht v thu cng lc), v thu vo b
m m n cho php 1 k t nhn vo v c ct b m trong khi k t th 2
c nhn vo. Nu CPU c k t th nht trc khi k t th 2 c nhn vo hon
ton th d liu khng b mt.
Trang 31
Hai thanh ghi chc nng c bit cung cp cho phn mm truy xut n Port
ni tip l SBUF v SCON. S m Port ni tip ( SBUF) a ch 99H l 2 s m
tht s : Ghi ln SBUF LOAD d liu pht v c SBUF truy xut d liu nhn.
y l 2 thanh ghi ring bit v r rt, m thanh ghi pht ch ghi cn thanh ghi thu ch
c. S khi ca Port ni tip nh sau:
Hnh 2.5: S khi Port ni tip

Thanh ghi iu khin Port ni tip SCON (98H) l thanh ghi c nh v bit
bao gm cc trng thi v cc bit iu khin. Cc bit iu khin set mode ca Port ni
tip, cn cc bit trng thi cho bit s kt thc vic thu pht 1 k t. Cc bit trng thi
c th c kim tra trong phn mm hoc c th lp trnh sinh ra s ngt.
Tn s hot ng ca Port ni tip hoc tc BAUD c th c ly t dao
ng trn Chip AT89S8252 hoc thay i. Nu 1 tc Baud thay i c dng, th
Timer cung cp 1 tc Baud ghi gi v phi c lp trnh 1 ccah1 ph hp.
2.5.2 Thanh ghi iu khin port ni tip SCON (Serial Port Control
Register)
Mode hot ng ca Port ni tip AT89S8252 c set bi vic ghi ln thanh
ghi mode ca Port ni tip SCON a ch 99H. Bng tm tt thanh ghi iu khin
Port ni tip SCON nh sau:
Trang 32
Bng 2.9: Tm tt thanh ghi SCON

M t hot ng
Bit
K kiu
a ch
SCON.7
SM0
9FH
Bit 0 ca mode Port ni tip
SCON.6
SM1
9EH
Bit 1 ca mode Port ni tip
SCON.5
SM2
9DH
Bit 2 ca mode Port ni tip. Cho php s

truyn ca b x l a knh mode 2, 3.
RI s khng tch cc nu bit th 9 thu
vo l 0.
SCON.4
REN
9CH
REN = 1 s cho thu k t
SCON.3
TB8
9BH
Pht bit 8. Bit 9 pht trong mode 2 v 3,

n c st hoc xa bi phn mm.
SCON.2
RB8
9AH
Thu bit 8, bit 9 thu.
SCON.1
TI
99H
C ngt pht. c set khi kt thc s

truyn k t v c xa bi phn mm.
SCON.0
RI
98H
C ngt thu. c set khi kt thc s thu

v c xa bi phn mm
SCON Register Sumary

2.5.3 Cc mode hot ng (Mode Of Operation)
Bng 2.10: Bng MODE hot ng ca Port ni tip.
SM0
SM1
Mode
M t
Thanh ghi dch
2
3
Tc Baud
C nh
FOSC/12).
(tn
dao
ng
URAT 8 bit
Thay i (c t bi Timer).
URAT 9 bit
C nh (tn s dao ng FOSC/64

hoc FOSC/32.
URAT 9 bit
Thay i (c t bi Timer).
SCON Register Sumary
Trang 33
Trc khi dng Port ni tip, SCON phi c gn ng mode. V d khi

gn Port ni tip MODE 1 (SM0/SM1 = 0/1), cho php thu ( REN = 1), v set c ngt
ca vic pht sn sng hot ng (TI =1 ), ta dng lnh sau:
MOV SCON, # 01010010H.
Port ni tip ca AT89S8252 c 4 mode hot ng ty thuc theo 4 trng thi
ca SM0/SM1.
Ba trong 4 mode cho php truyn s ng b vi mi k t thu hoc pht s
c b tr bi bit Start hoc bit Stop.
2.5.4 S khi ng, truy xut cc thanh ghi port ni tip
2.5.4.1 S cho php b thu (Recive Enable)
Bit cho php thu REN trong thanh ghi SCON phi c set bi phn mm
cho php s thu cc k t. iu ny thng c lm u chng trnh khi cc Port
ni tip v cc Timer c khi ng.
Ta c th khi ng bng lnh :
SETB REN hoc MOV CON, #XXX1XXXXB
2.5.4.2 Bit data th 9 ( the 9 th data bit)
Bit data th 9 c pht trong mode 2 v mode 3 phi c LOAD vo TB8
bi phn mm, cn bit data th 9 c thu th t trong RB8.
Phn mm c th ( hoc khng ) i hi 1 bit data th 9 tham gia vo nhng chi
tit k thut ca thit b ni tip vi iu kin m s truyn data c thnh lp.
2.5.4.3 S thm vo bit kim tra chn l Parity
Cch tng qut dng chung bit data th 9 l cng bit Parity vo 1 k t.
Bit P (Parity) trong t trng thi chng trnh PSW s c set hoc xa vi
mi chu k my thnh lp bit Parity chn vi 8 bit trong thanh ghi tch ly A.
V d nu s truyn yu cu 8 bit data cng thm 1 bit Parity chn, th cc lnh
sau y c th c dng pht 8 bit vo thanh ghi A vi Parity chn c cng vo
bit th 9.
MOV C, P
MOV TB8, C
MOV SBUF, A
Nu Parity l c yu cu th cc lnh trn c sa li l:
MOV C, P
CPL C
MOV TB8, C
MOV SBUF, A
Vic dng bit Parity khng b gii hn trong mode 2 hoc mode 3.8 bit data
c pht trong mode 1 c th bao gm 7 bit data, v 1 bit Parity. pht 1 m ASCII
7 bit vi 1 bit Parity chn vo 8 bit, cc lnh sau y c dng :
CLR ACC, 7
: xa bit MSB trong A m bo Parity chn
MOV C, P
: a Parity chn vo C
Trang 34
MOV ACC.7, C
:a Parity chn vo bit SB ca A
MOV SBUF, A
:gi bit data cng bit Parity chn
2.5.4.4 C ngt
C ngt thu RI v pht TI trong thanh ghi SCON vn hnh 1 rle quan trng
trong s truyn ni tip AT89S8252. C 2 bit u c set bi phn cng nhng phi
xa bi phn mm.
in hnh l RI c set cui s thu k t v cho bit : thanh ghi m thu
y. iu kin ny c th kim tra trong phn mm hoc c th c lp trnh sinh
ra s ngt. Nu phn mm mun nhp 1 k t t 1 thit b c kt ni n Port ni
tip, th n phi ch n khi RI c set, sau khi xa RI v c k t t SBUF. iu
ny c lp trnh nh sau :
WAIT :
JNB RI, WAIT
: kim tra RI c set cha
CLR RI
:xa c ngt thu RI
MOV A, SBUF
: CPU c k t
TI c set cui s pht k t v cho bit thanh ghi m ca s pht
rng. Nu phn mm mun gi 1 k t n 1 thit b c kt ni n Port ni
tip, trc tin n phi kim tra xem Port ni tip sn sng cha. Nu k t trc
c gi i, th n phi ch cho n khi s pht i hon thnh. Cc lnh sau y
dng pht 1 k t trong thanh ghi A ra :
WAIT :
JNB RI, WAIT
: kim tra TI c set cha
CLR RI
:xa c ngt thu TI
MOV A, SBUF
: CPU c k t
2.5.5 S truyn ca b x l a knh
Mode 2 v mode 3 c 1 s cung cp c bit cho vic truyn a knh x l.
cc mode ny, 9 bit data c thu v bit th 9 i vo RB8. Port c th lp trnh nh
iu m bit Stop thu c, s ngt ca Port ch c tch cc nu RB8 = 1. c im
ny cho php bi vic set bit MS2 trong thanh ghi SCON. ng dng ny l 1 s ci
t mng c dng bi nhiu AT89S8252 s sp t my ch v my con nh sau
Trang 35
Hnh 2.6: S b x l a knh AT89S8252

Khi b x l ch mun pht 1 khi d liu n b x l con ring l, trc tin
n gi ra 1 byte a ch nhn din b x l con mong mun. Byte a ch c phn
bit vi byte d liu bi bit th 9 : bit th 9 bng 1 trong bit a ch v bng 0 trong
byte d liu. Tuy nhin byte a ch s ngt ton b cc b x l con, do c th
khm ph byte thu kim tra nu n ang nh a ch. B x l con c nh
a ch s xa bit SM2 ca n v chun b thu cc byte d liu theo sau . Nhng b
x l con khng c nh a ch vn c gi cc bit SM2 ca n v set tr v cc
bn ca chng ng thi l i cc byte d liu thu thp. Chng s c ngt li khi
byte a ch k tip c pht bi b x l c.
Bit SM2 khng c tc dng trong mode 0 v trong mode 1 n c th c dng
kim tra s thch hp ca bit Stop. Trong s thu mode 1, nu SM2 = 0 th s ngt
thu s khng tch cc tr khi bit Stop thch hp c thu.
2.5.6 Tc baud ca port ni tip
Tc Baud ca port ni tip c nh mode 0 v mode 2. Trong mode 0 n
lun lun l tn s dao ng trn Chip chia cho 12. Thng thng thch anh 12 MHz
l dao ng trn Chip AT89S8252 nn tc Baud ca mode 0 l 1 MHz.
On Chip Oscillator
+12
Baud Rate Clock
MODE 0
Bng s mc nhin sau khi reset h thng, tc Baud mode 2 l tn s dao
ng chia cho 64, tc Baud cng b nh hng bi bit SMOD ca thanh ghi PCON.
Vic set bit SMOD s tng gp i tc Baud trong cc mode 1, 2 v 3. Trong
mode 2, tc Baud c th c gp i t gi tr mc nh 1/64 tn s/Chip ( ng
SMOD = 0 ) ln n 1/32 tn s dao ng trn Chip ( ng vi SMOD = 1 ).
Trang 36
+64
SMOD = 0
On Chip Oscillator
Baud Rate Clock
+32
SMOD = 1
MODE 1
Bi thanh ghi PCON khng c bit nh v, nn set bit SMOD m khng thay
i cc bit khc ca thanh ghi PCON th i hi phi c 1 hot ng c b sung
ghi.
Cc lnh sau y set bit SMOD :
MOV A, PCON :nhp vo A gi tr hin hnh ca PCON
SETB ACC, 7
:set bit 7 ca ACC ( bit SMOD )
MOV PCON, A
: ghi gi tr tr v PCON m SMOD c set
Cc tc Baud trong mode 1 v mode 3 ca AT89S8252 c xc nh bi
tc trn ca Timer 1. Bi v Timer hot ng tn s cao lin tc nn trn xa hn
na c chia cho 32 ( chia cho 16 nu SMOD = 1 ) trc khi cung cp xung clock
tc Baud n Port ni tip. Tc Baud mode 1 v 3 ca AT89S8252 c xc
nh bi tc trn ca Timer 1 hoc Timer 2, hoc c 2.
+32
SMOD = 0
On Chip Oscillator
Baud Rate Clock
+16
SMOD = 1
MODE 2
Mun sinh ra tc Baud, ta khi gn TMOD mode t ng np 8 bit ( mode
2 ca Timer ) v t gi tr Reload ng vo byte cao ca thanh ghi Timer 1 (TH1)
sinh ra tc trn chnh xc cho tc Baud. C nhng tc Baud rt chm ta dng
mode 16 bit l mode 1 ca Timer, nhng ta phi khi gan sau mi s trn cho
TL1/TH1 trong th tc phc v ngt ISR.
Hot ng khc c m gi bi vic dng Timer 1 ngoi l T1 (P3.5). Cng
thc chung xc nh tc Baud trong mode 1 v mode 3 l:
BAUD RATE = TIMER 1 OVERFLOW RATE32
Trang 37
V d 1 hot ng 1200 Baud i hi 1 tc trn l 1200/32 = 38,4KHz. Nu

thch anh 12 MHz li dao ng trn Chip, th Timer 1 c m gi tc ca tn
s 1 MHz. Bi v Timer phi trn tc tn s 38,4 KHz v Timer m gi tc
ca tn s 1 MHz, nn 1 s trn c yu cu vi 1000:38,4 = 26,04 clock (lm trn
26). Bi v cc Timer m ln v trn trn s chuyn i t FFH 00H ca b m, nn
26 s m thp di 0 l gi tr Reload cn np cho TH1 ( gi tr ng l -26 ). Ta
dng lnh MOV TH1, #26.
V d sau khi ng Port ni tip hot ng ging nh UART 8 bit tc
Baud 2400, dng Timer 1 cung cp s m gi tc Baud :
MOV
SCON, #01010010B
: port ni tip mode 1.
MOV
TMOD, #20
: timer 1 mode 2.
MOV
TH1, # -13
:np vo b m tc 2400 Baud.
SETB
TR1
: Start Timer 1.
Trong SCON c SM0/SM1 vo mode UART 8 bit, REN = 1 cho php Port
ni tip thu cc k t v TI = 1 cho php pht k t u tin bi vic cho bit thanh
ghi m rng. TMOD c M1/M0 = 1/0 t Timer 1 vo mode t ng np 8 bit.
Vic set bit TR1 m my chy Timer. Tc Baud 2400 s cho ta tc trn
Timer 1 l 2400/32 = 76,8 KHz ng thi Timer 1 c m gi tc ca tn s
1000KHz ( ng vi thch anh 12MHz ) s cho s xung Clock sau mi s trn l
1000:76,8 = 13,02 (ly trn 13 ). Vy -13 l gi tr cn np vo TH1 c tc Baud
l 2400 Baud.
Sau y l bng tm tt tc Baud ph bin ng vi 2 loi thch anh 12 MHz
v 11,059 MHz :
Bng 2.11: Tm tt tc Baud ph bin
SMOD
TH1
Reload
Value
Actua
Baud Rate
Error
12 MHz
-7 (F9H
8923
7%
2400
12 MHz
-13 (F9H)
2404
0.16%
1200
12 MHz
-23 (F9H)
1202
0%
19200
11.059 MHz
-3 (F9H)
19200
0%
9600
11.059 MHz
-3 (F9H)
9600
0%
2400
11.059 MHz
-12 (F9H)
2400
0%
1200
11.059 MHz
-24 (F9H)
1200
0%
Baud Rate
Crytal
Frequency
9600
Baud Rate Sumary
Trang 38
2.6
HOT NG TIMER CA AT89S8252
2.6.1 Gii thiu

B nh thi ca Timer l mt chui cc Flip Flop c chia lm 2, n nhn tn
hiu vo l mt ngun xung clock, xung clock c a vo Flip Flop th nht l
xung clock ca Flip Flop th hai m n cng chia tn s clock ny cho 2 v c tip
tc.
V mi tng k tip chia cho 2 nn Timer tng phi chia tn s clock ng vo
cho 2 . Ng ra ca tng cui cng l clock ca Flip Flop trn Timer hoc c m n
kim tra bi phn mm hoc sinh ra ngt. Gi tr nh phn trong cc Flip Flop ca b
Timer c th c ngh nh m xung clock hoc cc s kin quan trng bi v Timer
c khi ng. V d Timer 16 bit c th m t FFFFH sang 0000H.
n
Cc Timer c ng dng thc t cho cc hot ng nh hng. AT89S8252

c 3 b Timer 16 bit, mi Timer c 4 mode hot ng. Cc Timer dng m gi,
m cc s kin cn thit v s sinh ra tc ca tc Baud bi s gn lin Port ni
tip.
Trc ht ta st Timer 0 v Timer 1 ca AT89S8252.
2.6.2 Timer 0 v Timer 1
Timer 0 v Timer 1 ca AT89S8252 ging nh h 8051.
Mi s nh thi l mt Timer 16 bit, do tng cui cng l tng th 16 s
chia tng s clock vo cho 2 16 = 65536.
Trong cc ng dng nh thi, 1 Timer lp trnh trn mt khong thi gian
u n v c set c trn Timer. C c dng ng b chng trnh thc
hin mt hot ng nh vic a ti mt tng ng vo hoc gi d liu n ng ra.
Cc ng dng khc c s dng vic ghi gi u u ca Timer o thi gian tri qua
gia hai trang thi (v d nh o rng xung). Vic m mt d kin c dng
xc nh s ln xut hin ca s kin , tc thi gian tri qua gia cc s kin.
Cc Timer 0 v Timer 1 ca AT89S8252 c truy sut bi vic dng 6 thanh
ghi chc nng c bit nh sau:
Bng 2.12: Cc thanh ghi truy sut Timer 0 v Timer 1
Timer SFR
Purpose
Address
Bit - Addressable
TCON
Control
88H
YES
TMOD
Mode
89H
NO
TL0
Timer 0 low byte
8AH
NO
TL1
Timer 1 low byet
8BH
NO
TH0
Timer 0 high byte
8CH
NO
Trang 39
Timer 1 high byte
TH1
8DH
NO
Thanh ghi Mode Timer TMOD (Timer Mode Register)

Thanh ghi mode gm 2 nhm 4 bit l: 4 bbit thp t mode hot ng cho
Timer 0 v 4 bit cao t mode hot ng cho Timer 1 8 bit ca thanh ghi TMOD c
tm tt nh sau:
Bng 2.13: Tm tt hot ng thanh ghi TMOD
Bit
Name
Timer
Description
GATE
Khi GATE = 1, Timer ch lm vic khi

INTI = 1
Bit cho m s kin hay ghi gi
C/T
C/T = 1: m s kin
C/T = 0: ghi gi u n
M1
Bit chn mode cua Timer 1
M0
GATE
Bit cng ca Timer 0
C/T
Bit chn Counter/Timer ca Timer 0
M1
M0
Hai bit M0 v M1 ca TMOD chn mode cho Timer 0 hoc Timer 1.

Bng 2.14: Hot ng 2 bt M0 v M1
M1
M0
MODE
Description
Mode Timer 13 bit (mode 8048)
Mode Timer 16 bit
Mode t ng np 8 bit
Mode Timer tch ra:
Timer 0: TL0 l 8 bit c diu khin bi

cc bit ca Timer 0. TH0 tng t nhng
c iu khin bi cc mode Timer 1.
Timer 1: c ngc li
Trang 40
TMOD khng c bit nh v, n thng c LOAD mt ln phn mm u

chng trnh khi ng mode Timer. Sau s nh gi c th dng li, c khi
ng li nh th bi s truy sut cc thanh ghi chc nng c bit ca Timer khc.
2.6.2.1 Thanh ghi iu khin Timer TCON (Timer Control Register)
Thanh ghi iu khin bao gm cc bt trang thi v cc bit iu khin bi Timer
0 v Timer 1. Thanh ghi TCON c bt nh v. Hot ng ca tng bit c tm tt
nh sau:
Bng 2.15: Tm tt hot ng thanh ghi TCON
Bit
TCON.7
Symbol
TF1
Bit
Address
Description
8FH
C trn Timer 1 c set bi phn cng

s trn, c xa bi phn mm hoc
bi phn cng khi cc vecto x l n th
tc ngt ISR.
TCON.6
TR1
8EH
Bit iu khin chy Timer 1 c set

hoc xa bi phn mm chy hoc
ngng chy Timer.
TCON.5
TF0
8DH
C trn Timer 0 ( hot ng tng t

TF1).
TCON.4
TR0
8CH
Bit iu khin chy Timer 0 (ging TR1).
8BH
C kiu 1 ngt ngoi. Khi cnh xung

xut hin trn INT1 th IE1 c xa bi
phn mm hoc phn cng khi CPU nh
hng n th tc phc v ngt ngoi.
TCON.3
IE1
TCON.2
IT1
8AH
C kiu 1 ngt ngoi c set hoc xa

bng phn mm bi cnh kch hot bi s
ngt ngoi.
TCON.1
IE0
89H
C cnh ngt 0 ngoi.
TCON.0
IT0
88H
C kiu ngt 0 ngoi.
2.6.2.2 Cc Mode v c trn (Timer Modes And Overflow).

AT89S8252 c Timer l Timer 0 v Timer 1. Ta dng k hiu TLx v THx
ch 2 thanh ghi byte thp v byte cao ca Timer 0 hoc Timer 1.
2.6.2.2.1
Mode Timer 13 bit (MODE 0)
Trang 41

Timer Clock
TLx (5 bit)
THx (8 bit)
TFx
Overflow
MODE 0
Mode 0 l mode Timer 13 bit, trong byte cao ca Timer (THx) c t thp
v 5 bit trng s thp ca byte thp Timer (TLx) t cao hp thnh Timer 13 bit. 3
bit cao ca TLx khng dng.
2.6.2.2.2
Timer Clock
Mode Timer 16 bit (MODE 1)
TLx (8 bit)
THx (8 bit)
TFx
OverFlow
MODE 1
Mode 1 l mode Timer 16 bit, tng t nh mode 0 ngoi tr Timer ny hot
ng nh mt Timer y 16 bit, xung clock c dng vi s kt hp cc thanh ghi
cao v thp (TLx, THx). Khi xung clock c nhn vo, b m Timer tng ln
0000H, 0001H, 0002H,... v mt s trn s xut hin khi c s chuyn trn b m
Timer t FFFFH sang 0000H v s set c trn Timer, sau Timer m tip.
C trn l bit TFx trong thanh ghi TCON m n s c c hoc ghi bi phn
mm.
Bit c trng s ln nht (MSB) ca gi tr trong thanh ghi Timer l 7 bit ca
THx v bit c trng s thp nht (LSB) l bit 0 ca TLx. Bit LSB i trng thi tn
s clock vo c chia 2 16 = 65536.
Cc thanh ghi Timer TLx v THx c th c c hoc ghi ti bt k thi im
no bi phn mm.
2.6.2.2.3
Mode t ng np 8 bit (MODE 2)
Timer Clock
TLx (8 bit)
TFx
Overflow
Reload
THx (8 bit)
MODE 2
Mode 2 l mode t ng np 8 bit, byte thp TLx ca Timer hot ng nh mt
Timer 8 bit trong khi byte cao THx ca Timer gi gi tr Reload. Khi b m trn t
Trang 42
FFH sang 00H, khng ch c trn c st m gi tr trong THx cng c np vo

TLx. B m ny c tip tc t gi tr ny ln n s chuyn trng thi t FFH sang
00H k tip v c th tip tc. Mode ny th ph hp bi v cc s trn xut hin c
th m mi lc ngh thanh ghi TMOD v THx c khi ng.
2.6.2.2.4
Mode Timer tch ra (MODE 3)
Timer Clock
TLx (8 bit)
THx (8 bit)
Overflow
Timer Clock
TLx (8 bit)
TF0
Overflow
Timer Clock
TLx (8 bit)
TF1
Overflow
MODE 3
Mode 3 l mode tch ra v l s khc bit cho mi Timer.
Timer 0 mode 3 c chia lm 2 Timer 8 bit. TL0 v TH0 hot ng nh
nhng Timer ring l vi su75 trn s set cc bit TL0 v TF1 tng ng.
Timer 1 b dng li mode 3, nhng c th c khi ng bi vic ngt n
vo 1 trong cc mode khc. Ch c nhc im l c trn TF1 ca Timer 1 khng nh
hng bi cc s trn ca Timer 1 bi v TF1 c ni vi TH0.
Mode 3 tt yu cung cp 1 Timer ngoi 8 bit l Timer th ba ca AT89S8252.
Khi vo Timer 0 mode 3, Timer c th hot ng hoc tt bi s ngt n ra ngoi v
vo trong mode ca chnh n hoc c th c dng bi Port ni tip nh l mt my
pht tc Baud, hoc c th dng trong hng no m khng s dng Interrupt.
2.6.2.3 Cc ngun xung clock (Clock Sources)
C 2 ngun xung clock c th m gi v s nh gi bn trong v s m s
kin bn ngoi. Bit C/T trong TMOD cho php chn mt trong hai khi Timer c
hot ng.
2.6.2.3.1
S bm gi bn trong (Interval Timing)
Nu bit C/T = 0 th hot ng ca Timer lin tc v c chn vo b Timer

c ghi gi t dao ng trn Chip. Mt b chia 12 c thm vo gim tn s
clock n 1 gi tr ph hp hu ht cc ng dng. Cc thanh ghi TLx v THx tng tc
1/12 ln tn s dao ng trn Chip. Nu dng thch anh 12 MHz th s a n tc
clock 1 MHz.
Trang 43
Cc s trn Timer sinh ra sau mt con s c nh ca nhng xung clock n ph

thuc vo gi tr khi to c LOAD vo cc thanh ghi Thx v TLx.
2.6.2.3.2
S m cc s kin (Event Counting)
Nu bit C/T = 1 th b Timer c ghi gi t b ngun bn ngoi trong nhiu

ng dng, b ngun bn ngoi ny cung cp 1 s nh gi vi 1 xung trn s xy ra
ca s kin. S nh gi l s m s kin. Con s s kin c xc nh trong phn
mm bi vic c cc thanh ghi Timer. TLx/THx, bi v gi tr 16 bit trong cc thanh
ghi ny tng ln cho mi s kin.
Ngun xung clock bn ngoi a chn P3.4 l ng nhp ca xung clock bi
Timer 0 (T0) v P3.5 l ng nhp ca xung clock bi Timer 1 (T1).
Trong cc ng dng m cc thanh ghi Timer c tng trong p ng ca s
chuyn trang thi t 1 sang 0 ng nhp Tx. Ng nhp bn ngoi c th trong sut
S5P2 ca mi chu k my. Do khi ng nhp a ti mc cao trong mt chu k v
mc thp trong mt chu k k tip th b m tng ln mt. Gi tr mi xut hin trong
cc thanh ghi Timer trong sut S5P1 ca chu k theo sau mt s kn chuyn i c
khm ly. Bi v n chim 2 chu k my (2s) nhn ra s chuyn i t 1 sang 0,
nn tn s bn ngoi ln nht l 500 KHz nu dao ng thch anh 12 MHz.
2.6.2.4 S bt u, kt thc v s iu khin cc Timer (Starting, Stoping
And Controlling The Timer)
Bit TRx trong thanh ghi c bit nh v TCON c khin bi phn mm bt
u hoc kt thc cc Timer. bt u cc Timer ta set bit TRx v kt thc Timer
ta clear TRx. V d Timer 0 c bt u bi lnh SETB TR0 v c kt thc bi
lnh CLR TR0 (bit GATE = 0). Bit TRx b xa sau s seset h thng, do cc Timer
b cm bng s mc nh.
Thm phng php na iu khin cc Timer l dng bit GATE trong thanh
ghi TMOD v ng nhp bn ngoi INTx. u ny c dng o cc rng xung.
Gi s xung a vo chn INT0 ta khi ng Timer 0 cho mode 1 l mode Timer 16
bit vi TL0/TH0 = 0000H, GATE = 1, TR0 = 1. Nh vy khi INT0 = 1 th Timer
c m cng v ghi gi vi tc ca tn s 1 MHz. Khi INT0 xung thp th
Timer ng cng v khong thi gian ca xung tnh bng s l s m c trong
thanh ghi TL0/TH0.
2.6.2.5 S khi ng v truy sut cc thanh ghi Timer.
Cc Timer c khi ng mt ln u chng trnh t mode hot ng
cho chng. Sau trong thn chng trnh cc Timer c bt u, c xa, cc
thanh ghi Timer c c v cp nht... theo yu cu ca tng ng dng c th.
Mode Timer TMOD l thanhg ghi u tin c khi gn, bi v t mode hot
ng cho cc Timer. V d khi ng cho Timer 1 hot ng mode 1 (mode Timer
16 bit) v c ghi gi bng dao ng trn Chip ta dng lnh: MOV TMOD, #
00001000B. Trong lnh ny, M1 = 0, M0 = 0 vo mode 1 v C/T = 0, GATE = 0
Trang 44
cho php ghi gi bn trong ng thi xa cc bit mode ca Timer 0, sau lnh trn
Timer vn cha m gi, n ch bt u m gi khi set bit iu khin chy TR1 ca
n.
Nu ta khng khi gn gi tr u cho cc thanh ghi TLx/THx th Timer s bt
u m t 0000H ln v khi trn t FFFFH sang 0000H li m t 0000H ln.
Nu ta khi gn gi tr u cho TLx/THx, th Timer s bt u m t gi tr
gn ln nhng khi trn t FFFFH sang 0000H li m t 0000H ln.
Ch c trn TFx t ng s c st ln bi phn cng sau mi su75 trn v
s c xa bi phn mm. Chnh v vy ta c th lp trnh ch sau mi ln trn ta s
xa c TFx v quay vng lp khi gn cho TLx/THx Timer lun lun bt u m
t gi tr khi gn ln theo ta mong mun.
c bit nhng s khi gn nh hn 256 s, ta s gi mode Timer t ng np
8 bit ca mode 2. Sau khi khi gn gi tr u vo THx, khi set bit TRx th Timer s
bt u m gi tr khi gn v khi trn t FFH sang 00H trong TLx, c TRx t ng
c set ng thi gi tr m ta khi gn cho THx c n\p t ng vo TLx v
Timer li m t gi tr khi gn ny ln. Ni cch khc, sau mi trn ta khng cn
khi gn li cho cc thanh ghi Timer m chng vn m c li t gi tr ban u.
2.6.2.6 S c thanh ghi timer trn tuyn.
Trong mt s ng dng cn thit c gi tr trong cc thanh ghi Timer trn
tuyn, c mt vn tim nng n gin bo v li phn mm. Bi v 2 thanh ghi
Timer phi c c, nn li giai on c th xut hin nu byte trn v byte cao
gia 2 hot ng c. Mt gii php khc phc l c byte cao trc, sau c
byte thp, v c li byte cao. Nu byte cao thay i th lp li cc hot ng c.
2.6.3 Timer 2
Timer 2 c 3 ch hot ng l capture, auto-reload v baud rate generator.
Timer 2 bao gm 8-bit, TH2 v TL2. Trong cc chc nng hn gi, thanh ghi TL2
c tng ln mi chu k my. K t khi mt chu k my bao gm 12 thi gian dao
ng, t l tnh l 1 / 12 ca tn s dao ng.
Trong cc chc nng truy cp, thanh ghi c tng ln p ng mt s
chuyn tip 1-to-0 u vo ca n tng ng bn ngoi, T2. Trong chc nng ny,
cc u vo bn ngoi l ly mu trong S5P2 mi chu k my. Khi cc mu cho thy
mt cao trong mt chu k v mt thp trong chu k tip theo, vic m c tng ln.
Gi tr m mi xut hin trong thanh ghi trong sut S3P1 ca chu k sau m trong
qu trnh chuyn i c pht hin.
K t khi hai chu k my (24 khong thi gian dao ng) c yu cu nhn ra mt
s chuyn i 1 - 0, t l s lng ti a l 1 / 24 ca tn s dao ng. m bo cho
mc ly mu t nht mt ln trc khi n thay i, mc cn c t chc cho t
nht mt chu k my y .
Trang 45
Bng 2.16: Hot ng Timer 2

RCLK+TCLK
CP/
TR2
16 bit auto-reload
16 bit capture
Baud Rate generator
Off
MODE
2.6.3.1 Thanh ghi T2CON (Timer/Counter 2 Control Register)

Thanh ghi T2CON c nh v a ch 0C8H, y l thanh ghi 8 bit, v tr
cc bit nh sau:
CP/
TF2
EXF2
RCLK
TCLK
EXEN2 TR2
C/
6
Ta xt chc nng tng bit nh sau:

Bng 2.17: Chc nng tng bt T2CON
Bit
M t
TF2
C trn ca Timer 2 c set ln 1 khi b m Timer 2 trn v

phi c xa bng phn mm. TF2 khng s c set ln 1 khi
mt trong hai RCLK = 1 hoc TCLK = 1.
EXF2
C ngt ngoi ca Timer 2 c set khi c mt capture hoc

reload c gy ra bi mt qu trnh chuyn i v T2EX v
EXEN2 = 1. Khi Timer 2 c cho php ngt, EXF2 = 1 s gy
ra CPU thng xuyn ngt Timer 2. EXF2 phi c xa bi
phn mm. EXF2 khng gy ra mt ngt trong ch ln / xung
truy cp (DCEN = 1).
RCLK
Nhn c xung clock cho php. Khi thit lp, nh hng ti

cng ni tip s dng s trn ca Timer 2 nhn tn hiu xung
t cng ni tip ch 1 v 3. RCLK = 0 gy ra cho Timer 1
trn s dng cho nhn xung clock.
TCLK
Truyn tn hiu xung clock. Khi thit lp, nh hng ti cng ni

tip s dng s trn ca Timer 2 truyn tn hiu xung t cng
ni tip ch 1 v 3. TCLK = 0 gy ra cho Timer 1 trn, s
dng cho nhn xung clock.
EXEN2
Cho php ngt ngoi Timer 2. Khi c thit lp, cho php
capture hoc reload xy ra nh l kt qu ca mt qu trnh
chuyn i trn T2EX nu Timer 2 l khng c s dng tao
clock cng ni tip. EXEN2 = 0, Timer 2 b qua cc s kin
Trang 46
ti T2EX.
TR2
Start / Stop kim sot Timer 2. TR2 = 1 bt u hn gi.
C/
Chn chc nng m hay hn gi ca Timer 2. C/T2 = 0 chn

chc nng hn gi. C/T2 = 1 chn m s kin (xung cnh xung
kch hot m).
CP/
Capture / Reload chn. CP/RL2 = 1 chn capture trn cc qu

trnh chuyn i ti T2EX nu EXEN2 = 1. CP/RL2 = 0 chn
reload t ng xy ra khi Timer 2 trn hoc qu trnh chuyn i
xy ra ti T2EX khi EXEN2 = 1. Khi RCLK hoc TCLK = 1, bit
ny c b qua v vic hn gi s t ng reload li khi Timer 2
trn.
2.6.3.2 Thanh ghi T2MOD Timer 2 Mode Control Register

Thanh ghi T2MOD c xc nh a ch C9H, gm 8 bit nh sau:
Bit
T2OE
DCEN
Chc nng ca tng bt:

Bit 1 T2OE: bt cho php Timer 2 xut ra.
Bit 0 DCEN: bt cho php Timer 2 m ln hay m xung.
2.6.3.3 Ch Capture
Trong ch capture, hai la chn c la chn bi bit EXEN2 trong
T2CON. Nu EXEN2 = 0, Timer 2 l mt b m thi gian 16-bit hoc truy cp m
khi trn b bit TF2 trong T2CON. Bit ny sau c th c s dng to ra mt
gin on. Nu EXEN2 = 1, Timer 2 thc hin cng hot ng, nhng l - 0 mt qu
trnh chuyn i ti T2EX u vo bn ngoi cng lm cho gi tr hin ti TH2 v TL2
capture vo RCAP2H v RCAP2L, tng ng. Ngoi ra, chuyn tip T2EX gy ra
bit EXF2 trong T2CON c thit lp. Cc bit EXF2, nh TF2, c th to ra mt
ngt..
Trang 47
Hnh 2.7: Timer 2 trong ch Capture

2.6.3.4 Ch Auto-Reload
Timer 2 c th c lp trnh m ln hoc xung khi cu hnh t ng 16 bit ca ch auto-reload. Tnh nng ny c gi bi DCEN (Down Counter Enable)
bit nm T2MOD SFR. Khi reset, cc bit DCEN c thit lp l 0 Timer 2 mc
nh m. Khi DCEN c thit lp, Timer 2 c th m ln hoc xung, ty thuc
vo gi tr ca T2EX.
Hinh 2.8 cho thy Timer 2 t ng m ln khi DCEN = 0. Trong ch ny,
hai ty chn c la chn bi bit EXEN2 trong T2CON. Nu EXEN2 = 0, Timer 2
m ln FFFFH v sau thit lp bit TF2 khi trn. Trn cng gy ra cc b m thi
gian ng k c np li vi gi tr 16-bit trong RCAP2H v RCAP2L. Cc gi tr
trong RCAP2H v RCAP2L c ci sn bng phn mm. Nu EXEN2 = 1, 16 bit
reload c th c kch hot bi s trn hoc bi mt s chuyn tip 1 - 0 u vo
bn ngoi T2EX. iu ny chuyn i cng thit lp cc bit EXF2. C hai TF2 v
EXF2 bit c th to ra mt ngt nu c kch hot.
Trang 48
Hnh 2.8: Timer 2 trong ch Auto Reload

Thit lp cc bit DCEN cho php Timer 2 m ln hoc xung, nh th hin
trong hnh 2.9. Ch , PIN T2EX iu khin theo hng m. Mt logic 1 ti T2EX
lm cho Timer 2 m. B m thi gian s trn ti FFFFH v thit lp cc bit TF2.
Trn cng lm cho gi tr 16-bit trong RCAP2H v RCAP2L c np li vo s ng
k hn gi, TH2 v TL2, tng ng.
Mt logic 0 T2EX lm cho Timer 2 m ngc. Hn gi underflows khi TH2
v TL2 bng gi tr c lu tr trong RCAP2H v RCAP2L. Underflows thit lp bit
TF2 v gi FFFFH c np li vo s ng k hn gi.
Bit EXF2 Toggles bt c khi no Timer 2 trn hoc underflows v c th c
s dng nh mt 17 bit phn gii. Trong ch ny hot ng, EXF2 khng nh
du mt ngt
Hnh 2.9: Timer 2 trong ch Auto-Reload

2.6.3.5 Ch Baud Rate Generator
Trang 49
Hnh 2.10: Timer 2 trong ch Baud Rates Generator

Timer 2 c chn l my pht in tc truyn bng cch thit lp TCLK
and/or RCLK trong T2CON. Lu rng tc baud cho truyn v nhn c th khc
nhau nu Timer 2 c s dng cho cc my thu hoc my pht v Timer 1 c s
dng cho cc chc nng khc. Thit lp RCLK and/or TCLK a Timer 2 vo my
pht in tc truyn ch , nh trong hnh 2.10.
T l ch my pht in baud l tng t nh ch t ng ti li, trong
mt R trong TH2 nguyn nhn Timer 2 ng k c np li vi gi tr 16-bit vo s
ng k RCAP2H v RCAP2L, c ci sn bi phn mm.
Mc truyn trong cc ch 1 v 3 c xc nh bng t l trn Timer 2
theo phng trnh sau y:
Timer c th c cu hnh cho mt trong hai b m thi gian hoc hot ng

truy cp. Trong hu ht cc ng dng, n c cu hnh cho cc hot ng hn gi
(CP/T2 = 0). Cc hot ng hn gi khc nhau hn gi 2 khi n c s dng nh
mt my pht in tc truyn. Thng thng, khi mt gi, n gia tng mi chu k
my (1 / 12 tn s dao ng). Nh mt my pht in tc truyn, tuy nhin , n
tng mi khi nh nc (1 / 2 tn s dao ng). Cng thc tc truyn a ra di
y
(
Vi (RCAP2H, RCAP2L) l ni dung ca RCAP2H v RCAP2L c thc

hin nh l mt 16 -bit kiu s.
Trang 50
Chng 3: Tm hiu cc cng giao tip
CHNG 3: TM HIU CC CNG GIAO TIP

3.1 GIAO TIP CNG SONG SONG (CNG MY IN)
3.1.1 Tn gi
Cng song song: D liu c truyn qua cng ny theo cch song song, c th
d liu c truyn 8 bit ng thi hay cn gi byte ni tip bit song song.
Cng my in: L do l hu ht cc my in u c ni vi my tnh qua cng
ny.
Cng Centronic: y l tn ca mt cng ty thit k ra cng ny. Centronic
l tn mt cng ty chuyn sn xut my in kiu ma trn ng hng u th gii. Chnh
cng ty ny ngh ra kiu thit k cng ghp ni my in vi my tnh.
3.1.2 Mc in p cng
u s dng mc in p tng thch TTL(Transiztor - Transiztor - Logic)
0V5V trong :
0V l mc logic LOW
2V5V l mc logic HIGH
V vy khi ghp ni vi cng ny ta ch ghp ni nhng thit b ngoi vi c mc
in p tng thch TTL. Nu thit b ngoi vi khng c mc in p tng thch TTL
th ta phi p dng bin php ghp mc hoc ghp cch ly qua b ghp ni quang.
3.1.3 Khong cch ghp ni
Khong cch cc i gia thit b ngoi vi v my tnh ghp qua cng song
song thng b hn ch. L do l hin tng cm ng gia cc ng dn v in
dung k sinh hnh thnh gia cc ng dn c th lm bin dng tn hiu. Khong
cch gii hn cc i l 8m. Thng thng ch 1,5 n 2m v l do an ton d liu. Nu
s dng khong cch ghp ni trn 3m th cc ng dy tn hiu v ng dy ni
t phi c son vi nhau thnh tng cp gim thiu nh hng ca nhiu. Bin
php khc s dng cp dt, trn mi ng d liu c t gia hai ng dy ni
t.
3.1.4 Tc truyn d liu
Tc truyn d liu qua cng song song ph thuc vo phn cng c s
dng. Trn l thuyt tc c th t n 1Mb/s nhng vi khong cch truyn hn
ch trong phm vi 1m. Vi nhiu mc ch s dng th khong cch ny hon ton
tha ng, tuy vy cng c nhng ng dng i hi phi truyn trn khong cch xa
hn. Trong trng hp ta phi ngh ngay n kh nng ghp ni khc (nh ghp
ni qua cng RS232).
3.1.5 Cu trc cng song song
Cng song song c hai loi: cm 36 chn v cm 25 chn. Ngy nay, loi
cm 36 chn khng cn c s dng, hu ht cc my tnh PC u trang b cm 25
chn nn ta ch cn quan tm n loi 25 chn.
Trang 51
Cng song song gm c 4 ng iu khin, 5 ng trng thi v 8 ng d

liu bao gm 5 ch hot ng:
Ch
Ch
Ch
Ch
Ch
tng thch (compatibility).

nibble.
byte.
EPP (Enhanced Parallel Port).
ECP (Extended Capabilities Port).
Ba ch u tin s dng port song song chun (SPP Standard Parallel Port)
trong khi ch 4, 5 cn thm phn cng cho php hot ng tc cao hn.
Bng 3.1 S chn ca my in
CHN
K HIU
NG
VO/RA
M T
STROBE
RA
2 n 9
D0 n D9
RA
10
ACK
VO
Bo nhn
11
BUSY
VO
Bo bn
12
PE
VO
Ht giy
13
SEL
Vo
La chn
14
AF
RA
T ng tip ng
15
ER
VO
16
INIT
RA
Thit lp thit b
17
SELIN
RA
La chn u vo
18 n 25
GND
VO
Cc bit d liu t D0 n D7
Li
Ni t
Cng song song c ba thanh ghi c th truyn d liu v iu khin my in. a

ch c s ca cc thanh ghi cho tt c cng LPT (line printer) t LPT1 n LPT4 c
lu tr trong vng d liu ca BIOS. Thanh ghi d liu c nh v offset 00h,
thanh ghi trng thi 01h, v thanh ghi iu khin 02h. Thng thng, a ch c s
Trang 52
ca LPT1 l 378h, LPT2 l 278h, do a ch ca thanh ghi trng thi l 379h hoc
279h v a ch thanh ghi iu khin l 37Ah hoc 27Ah. Tuy nhin trong mt s
trng hp, a ch ca cng song song c th khc do qu trnh khi ng ca BIOS.
BIOS s lu tr cc a ch ny nh sau:
Bng 3.2: a ch c s cc tthanh ghi cng song song
a ch
Chc nng
0000H0408H
a ch c s ca LPT1
0000H040AH
a ch c s ca LPT2
0000H040CH
a ch c s ca LPT3
3.1.6 Cc thanh ghi cng song song.

Thanh ghi d liu (hai chiu):
Tn hiu
D7
D6
D5
D4
D3
D2
D1
D0
Chn s
IPR
Thanh ghi trng thi my in (ch c):

Tn hiu my
BUSY
S chn cm
11
ACK
PAPER
SELECT ERROR
EMPTY
10
12
13
15
Thanh ghi iu khin my in:

Tn hiu
my in
DIR
IRQ
SELECTIN
INIT
AUTOFEED
STROBE
S chn
17
16
14
x: khng s dng
IRQ Enable: yu cu ngt cng; 1 = cho php; 0 = khng cho php
Ch rng chn BUSY c ni vi cng o trc khi a vo thanh ghi
trng thi, cc bit SELECTIN , AUTOFEED v STROBE c a qua cng o
trc khi a ra cc chn ca cng my in. Thng thng tc x l d liu ca cc
thit b ngoi vi nh my in chm hn PC nhiu nn cc ng ACK , BUSY v STR
c s dng cho k thut bt tay. Khi u, PC t d liu ln bus sau kch hot
ng STR xung mc thp thng tin cho my in bit rng d liu n nh trn
bus. Khi my in x l xong d liu, n s tr li tn hiu ACK xung mc thp ghi
nhn. PC i cho n khi ng BUSY t my in xung thp (my in khng bn) th
s a tip d liu ln bus.
3.2
GIAO TIP CNG NI TIP (RS232)
3.2.1 Cu trc cng ni tip.
Trang 53
Cng ni tip c s dng truyn d liu hai chiu gia my tnh v ngoi
vi, c cc u im sau:
Device).
Khong cch truyn xa hn truyn song song.

S dy kt ni t.
C th truyn khng dy dng hng ngoi.
C th ghp ni vi vi iu khin hay PLC (Programmable Logic
Cho php ni mng.
C th tho lp thit b trong lc my tnh ang lm vic.
C th cung cp ngun cho cc mch in n gin.
Cc thit b ghp ni chia thnh 2 loi: DTE (Data Terminal Equipment) v

DCE (Data Communication Equipment). DCE l cc thit b trung gian nh MODEM
cn DTE l cc thit b tip nhn hay truyn d liu nh my tnh, PLC, vi iu khin,
Vic trao i tn hiu thng thng qua 2 chn RxD (nhn) v TxD (truyn). Cc
tn hiu cn li c chc nng h tr thit lp v iu khin qu trnh truyn, c
gi l cc tn hiu bt tay (handshake). u im ca qu trnh truyn dng tn hiu bt
tay l c th kim sot ng truyn.
Tn hiu truyn theo chun RS-232 ca EIA (Electronics Industry
Associations). Chun RS-232 quy nh mc logic 1 ng vi in p t -3V n -25V
(mark), mc logic 0 ng vi in p t 3V n 25V (space) v c kh nng cung cp
dng t 10 mA n 20 mA. Ngoi ra, tt c cc ng ra u c c tnh chng chp
mch. Chun RS-232 cho php truyn tn hiu vi tc n 20.000 bps nhng nu
cp truyn ngn c th ln n 115.200 bps.
Cc phng thc ni gia DTE v DCE:
n cng (simplex connection): d liu ch c truyn theo 1 hng.
Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi thi
im ch c truyn theo 1 hng.
Song cng (full-duplex): s liu c truyn ng thi theo 2 hng.
nh dng ca khung truyn d liu theo chun RS-232 nh sau:
Start
D0 D1
D2
D3
D4
D5
D6
D7
P
STOP
Khi khng truyn d liu, ng truyn s trng thi mark (in p -10V).
Khi bt u truyn, DTE s a ra xung Start (space: 10V) v sau ln lt truyn t
D0 n D7 v Parity, cui cng l xung Stop (mark: -10V) khi phc trng thi
ng truyn.
Cc c tnh k thut ca chun RS-232 nh sau:
Trang 54
Chiu di cable cc di
15m
Tc d liu cc i
20 Kbps
in p ng ra cc i
25V
in p ng ra c ti
5V n 15V
3K n 7K
Tr khng ti
in p ng vo
15V
nhy ng vo
3V
3K n 7K
Tr khng ng vo
Cc tc truyn d liu thng dng trong cng ni tip l: 1200 bps, 4800
bps, 9600 bps v 19200 bps.
S chn cng ni tip

Cng COM c hai dng: u ni DB25 (25 chn) v u ni DB9 (9 chn) m
t nh bng 4.3.
Bng 3.3: ngha ca cc chn cng ni tip
D25
D9 Tn hiu
Hng truyn
M t
Protected ground: ni t bo v
TXD
DTE DCE
Transmitted data: d liu truyn
RXD
DCE DTE
Received data: d liu nhn
RTS
DTE DCE
Request to send: DTE yu cu truyn d liu
CTS
DCE DTE
Clear to send: DCE sn sng nhn d liu
Trang 55
DSR
DCE DTE
Data set ready: DCE sn sng lm vic
GND
Ground: ni t (0V)
DCD
DCE DTE
Data carier detect: DCE pht hin sng mang
20
DTR
DTE DCE
Data terminal ready: DTE sn sng lm vic
22
RI
DCE DTE
Ring indicator: bo chung
23
DSRD
DCE DTE
Data signal rate detector: d tc truyn
24
TSET
DTE DCE
Transmit Signal Element Timing: tn hiu

nh thi
15
TSET
DCE DTE
Transmitter Signal Element Timing: tn hiu

nh thi
17
RSET
DCE DTE
Receiver Signal Element Timing: tn hiu

nh thi
18
LL
21
RL
DCE DTE
Remote Loopback: To ra bi DCE khi tn

hiu nhn
14
STxD
DTE DCE
Secondary Transmitted Data
16
STxD
DCE DTE
Secondary Received Data
19
SRTS
DTE DCE
Secondary Request To Send
13
SCTS
DCE DTE
Secondary Clear To Send
12
SDSRD
DCE DTE
Secondary Received Line Signal Detector
25
TM
Dnh ring cho ch test
10
Dnh ring cho ch test
11
Khng dng
Local Loopback: kim tra cng
Test Mode
3.2.2 Truyn thng ni tip gia 2 nt.

Cc s khi kt ni dng cng ni tip:
TXD
TXD
TXD
TXD
RXD
RXD
RXD
RXD
GND
GND
GND
GND
DTE1
DTE2
DTE
DCE
Kt ni n gin trong truyn thng ni tip

Trang 56
Khi thc hin kt ni nh trn, qu trnh truyn phi bo m tc u pht

v thu ging nhau. Khi c d liu n DTE, d liu ny s c a vo b m v
to ngt.
Ngoi ra, khi thc hin kt ni gia hai DTE, ta cn dng s sau:
TXD
TXD
RXD
RXD
GND
GND
RTS
RTS
CTS
CTS
DSR
DSR
DCD
DCD
DTR
DTR
Kt ni trong truyn thng ni tip dng tn hiu bt tay

Khi DTE1 cn truyn d liu th cho DTR tch cc tc ng ln DSR ca DTE2
cho bit sn sng nhn d liu v cho bit nhn c sng mang ca MODEM (o).
Sau , DTE1 tch cc chn RTS tc ng n chn CTS ca DTE2 cho bit DTE1
c th nhn d liu. Khi thc hin kt ni gia DTE v DCE, do tc truyn khc
nhau nn phi thc hin iu khin lu lng. Qu trinh iu khin ny c th thc
hin bng phn mm hay phn cng. Qu trnh iu khin bng phn mm thc hin
bng hai k t Xon v Xoff.
K t Xon c DCE gi i khi rnh (c th nhn d liu). Nu DCE bn th s
gi k t Xoff. Qu trnh iu khin bng phn cng dng hai chn RTS v CTS. Nu
DTE mun truyn d liu th s gi RTS yu cu truyn, DCE nu c kh nng
nhn d liu (ang rnh) th gi li CTS.
3.3
TM HIU V USB
3.3.1 Khi nim

My in c ni vi my tnh qua cng song song trong khi hu ht cc my
tnh ch c trang b mt cng ny. S rt kh khn nu s dng thm Zip, lun i
hi tc kt ni cao vi my tnh v cn thit phi dng cng song song.
Modem c ni vi my tnh qua cng ni tip ging nh mt vi dng thit
b khc nh Digital Camera, Palm Pilots trong khi mi my tnh thng ch c hai
cng ni tip v chng rt chm.
Trang 57
Cc thit b i hi cc kt ni nhanh hn nh cc Card c bit c cm trc

tip vo khe cm (Slot) trn bo mch. Thc t s lng cc khe cm (Slo t) l c hn v
cn phi ci t cc phn mm cho thit b ny.
Mc ch ca USB l gii quyt cc vn ca ngi s dng khi cc cng kt
ni trn khng hiu qu. USB cung cp cho ngi s dng kh nng kt ni chun, d
dng vi 127 thit b trn cng mt my tnh. Mi thit b ngoi vi hin nay u c th
kt ni trn cng mt phin bn USB chng hn nh: my in, my qut nh, chut,
Joystick, Digital Camera, Webcam, Modem, loa, in thoi, Network Connection,
thit b lu tr thng tin ( Zip)...
3.3.2
Kt ni qua USB
Vic ni mt thit b vi my tnh qua USB ht sc n gin, ch vic cm cc

u ni ca thit b vi cc cng USB trn my tnh. Nu thit b c kt ni vi my
tnh ln u, h iu hnh s t ng d tm v yu cu np a Driver. Vi thit b
c ci t, my tnh t ng kch hot v kt ni vi thit b. Cc thit b kt ni qua
USB c th thit lp hay ngt kt ni bt k lc no. Nhiu loi thit b USB c ch
to lin vi cp ni vi hai kiu u ni A Connection v B Connection.
Chun USB s dng A Connection v B Connection trong hai trng hp
c th sau:
USB Type B
Chn 1 v 4 cp ngun 5 VDC.

Chn 2 v 3 l chn truyn d liu.
3.3.3 M rng cng USB
Thng thng cc my tnh hin nay ch c mt hoc hai khe cm USB (USB
Socket). Ngy nay vi a s cc thit b u s dng USB, my tnh rt d b thiu khe
cm. V d, trn my tnh c cc thit b nh: my in, my qut, Webcam,... s dng
USB trong khi my tnh ch c mt cng USB (USB Connector).
gii quyt vn ny, ch cn lp thm mt USB Hub. Chun USB h tr
ti 127 thit b v USB Hub l mt trong s ny. Cc Hub ny thng c bn cng
nhng cng c th c nhiu hn tu thuc tng loi. Ch cn cm USB Hub vo my
tnh sau cm cc thit b hoc Hub khc vo cc cng trn USB Hub.
Trang 58
Hub c hai loi: loi c cung cp ngun v khng cung cp ngun in cho
thit b cm vo Hub. Chun USB cho php cc thit b s dng ngun in t cng
USB. Cc thit b nh my in, my qut s dng ngun in ring cung cp t b
ngun (Power Supply) ca chng trong khi cc thit b s dng rt t in nng nh
chut, Digital Camera li dng in nng (khong 500mA - 5V) t Bus.
Nu my tnh kt ni vi nhiu thit b s dng ngun in ring (My in,
my qut...) th USB Hub khng cn thit phi l loi cung cp c ngun in.
Nu my tnh kt ni vi nhiu thit b khng c ngun in ring (Chut, Digital
Camera) th Hub nht thit phi c kh nng cung cp ngun cho cc thit b ny. Trn
Hub c mt b phn nh bin th cung cp dng in ti Bus v lm my tnh
khng b qu ti.
3.3.4 Cc t tnh ca USB
Cc c im ca USB bao gm:
My tnh hot ng nh mt Host.
C ti 127 thit b c th kt ni vo my tnh bao gm c ni trc tip

hay qua USB Hub.
Cc cp USB (USB Cable) ca tng thit b c th di ti 5m hay 30m
vi Hub.
Chun USB2.x cho php truyn d liu trn Bus ti tc 480 Mbps.
Mt cp USB c hai dy cung cp in v mt i dy xon truyn d
Trn dy cung cp in nng, in p c th ln ti 500mA - 5V.
liu.
Cc thit b s dng t in nng c cung cp in nng trc tip t
Bus. Cc Hub c th cung cp in nng cho cc thit b ni vi n t ngun in
ring ca chng.
Cc thit b USB c kh nng hon i nhanh, c th cm vo hay rt ra

khi Bus bt k lc no.
Cc thit b USB c th t ch ng (Sleep Mode) khi my tnh

chuyn sang ch Power-Saving.
Cc thit b ni vi cng USB dng cp USB truyn ti dng in hay

d liu. Khi my tnh hot ng, n truy vn ti tt c cc thit b ni vo Bus v gn
cho mi thit b mt a ch. Qu trnh ny c gi l lit k cc thit b. My tnh
cng s tm ra cch truyn d liu ca tng thit b:
Interrupt: Cc thit b nh bn phm gi lng d liu rt nh v ngt

on s c chn kiu Interrupt Mode.
Bulk: Cc thit b nh my in thng nhn nhng gi d liu ln, dng

kiu Bulk Transfer Mode. Tng on d liu (64 Byte) c gi ti my in v c
kim tra tnh chnh xc.
Trang 59
Isochronous: Cc thit b truyn d liu theo dng Stream nh loa s

dng Isochronous Mode. D liu tc thi c truyn gia thit b v my tnh v
khng c c ch sa li.
My tnh cng c th gi i cc lnh hay truy vn cc thng s vi cc gi

Control Packet. Khi mt thit b c my tnh lit k, my tnh s ginh ti 90% bng
thng (Bandwidth) phc v cc yu cu ca cc thit b kiu Interrupt v Isochronous.
Sau khi dng 90% ca 480 Mbps bng thng, my tnh s t chi cc truy nhp ca
bt k thit b kiu Interrupt hay Isochronous no khc. Cc Control Packet v thit b
kiu Bulk Transfer s s dng khong 10% bng thng cn li.
USB phn chia bng thng thnh cc Frame v my tnh s iu khin cc
Frame ny. Mi Frame cha 1.500 Byte v Frame mi c sinh ra sau mi mili giy.
Trong mt Frame, cc thit b kiu Isochronous v Interrupt phn chia thnh cc khe
nn chng m bo c bng thng cn thit trong khi cc thit b Bulk Transfer v
Control Packet s dng phn bng thng cn li.
3.3.5 USB 2.0
Chun USB2.0 xut hin vo thng T nm 2000 v c nng cp t USB1.1.
USB2.0 cung cp thm bng thng cho cc ng dng Multimedia v lu tr c tc
truyn d liu ln gp 40 ln so vi USB1.1. vic chuyn t chun USB1.1 sang
USB2.0 thun tin cho c ngi s dng v nh sn xut, USB2.0 c thit k hon
ton tng thch v lm vic c vi cp cng nh cng ni ca thit b USB nguyn
thu.
USB2.0 h tr ba ch truyn d liu: 1,5Mbps, 12Mbps v 480Mbps. Ngoi
ra USB2.0 h tr cc thit b bng thng thp nh bn phm v chut cng nh cc
thit b bng thng ln nh Webcam, my in, my qut nh v h thng lu tr.
3.3.6 USB 3.0
USB 3.0, cn c gi l SuperSpeed USB, l giai on tin ha k tip ca
Universal Serial Bus, inarguably tiu chun giao din ph bin v thnh cng nht
tng c to ra. Khi phn cng my tnh v cc thit b ngoi vi tip tc m rng
cng sut, tc , v tnh di ng, cc giao din kt ni vi h cng phi np tin tm
ng trong cc khu vc ny.
Xy dng s thnh cng ca USB 2.0, phin th ba ca Universal Serial Bus
nhm mc ch gii quyt ba tr ct ca thit k giao din:
Tc - So vi tc 12Mbps t i ca USB 1.1 v 450Mbps trung bnh

ca "High-Speed USB 2.0," SuperSpeed "giao din USB 3.0 c gng sng ln n tn
ca n vi mt l thuyt 5.0Gbps (5.120 Mbps) ca bng thng . Hin th nt cao
Blu-ray bn ngoi v a cng dung lng cao, USB 3.0 c thit k chim ot
v m rng th trng ang b chi phi bi FireWire.
Power - Vi mt danh sch ngy cng m rng cc ph kin v cc thit

b cm tay, xe but h tr phn cng t lu c y cc gii hn ca USB 2.0 c
Trang 60
th x l. u tin, cc c im k thut 3,0 cho php ln n 80% in nng tiu th

cao hn cho cc thit b chy SuperSpeed, v th hai, USB 3.0 bao gm mt phin
bn nng cao ca cc kt ni USB-B c gi l Powered-B, cho php USB ph kin
rt ra nng lng t cc thit b ngoi vi cng nh ch nh.
Kt ni Crossover - Trong c gng thit lp mt h sinh thi mnh m

hn ca cc thit b USB, cc tnh nng mi c thc hin trong c t USB 3.0 cho
php truyn thng cho gia phn cng. Tng t nh thng s k thut FireWire v
Ethernet, mi SuperSpeed USB bao gm mt phng php thit lp truyn thng ca
host-to-host (tc l t my tnh n my tnh) thng qua mt USB cho vi cp USB.
Ngoi ra, USB 3.0 c xy dng trn "USB On-The-Go" nguyn tc cho php cc
thit b cm tay (nh in thoi thng minh) hot ng nh thit b USB hoc mt
my ch USB, tng ng k tnh nng thit lp v kh nng s dng ca h vi cc
thit b USB.
Trang 61
Chng 4: Chun truyn thng ni tip RS232
CHNG 4: CHUN TRUYN THNG NI TIP RS232.

4.1 T VN .
Vn giao tip gia PC v vi iu khin rt quan trng trong cc ng dng
iu khin, o lng... Ghp ni qua cng ni tip RS232 l mt trong nhng k thut
c s dng rng ri ghp ni cc thit b ngoi vi vi my tnh.N l mt chun
giao tip ni tip dng nh dng khng ng b, kt ni nhiu nht l 2 thit b,
chiu di kt ni ln nht cho php m bo d liu l 12.5 n 25.4m, tc
20kbit/s i khi l tc 115kbit/s vi mt s thit b c bit. ngha ca chun
truyn thng ni tip ngha l trong mt thi im ch c mt bit c gi i dc theo
ng truyn.
C hai phin bn RS232 c lu hnh trong thi gian tng i di l
RS232B v RS232C. Nhng cho n nay th phin bn RS232B c th t c dng
cn RS232C hin vn c dng v tn ti thng c gi l tn ngn gn l chun
RS232.
Cc my tnh thng c 1 hoc 2 cng ni tip theo chun RS232C c gi l
cng COM. Chng c dng ghp ni cho chut, modem, thit b o lng...Trn
main my tnh c loi 9 chn hoc li 25 chn ty vo i my v main ca my tnh.
Vic thit k giao tip vi cng RS232 cng tng i d dng, c bit khi chn ch
hot ng l khng ng b v tc truyn d liu thp.
4.2
U IM CA GIAO DIN NI TIP RS232.
Kh nng chng nhiu ca cc cng ni tip cao.

Thit b ngoi vi c th tho lp ngay c khi my tnh ang c cp in.
Cc mch in n gin c th nhn c in p ngun nui qua cng ni
tip.
4.3
NHNG C IM CN LU TRONG CHUN RS232.
Trong chun RS232 c mc gii hn trn v di (logic 0 v 1) l +-12V. Hin

nay ang c c nh tr khng ti trong phm vi t 3000 m - 7000 m.
Mc logic 1 c in p nm trong khong -3V n -12V, mc logic 0 t +3V
n 12V.
Tc truyn nhn d liu cc i l 100kbps (ngy nay c th ln hn).
Cc li vo phi c in dung nh hn 2500pF.
Tr khng ti phi ln hn 3000 m nhng phi nh hn 7000 m.
di ca cp ni gia my tnh v thit b ngoi vi ghp ni qua cng ni tip
RS232 khng vt qua 15m nu chng ta khng s model.
Cc gi tr tc truyn d liu chun: 50, 75, 110, 750, 300, 600, 1200,
2400, 4800, 9600, 19200, 28800, 38400....56600, 115200 Bps.
4.4
CC MC IN P NG TRUYN.
Trang 62
RS 232 s dng phng thc truyn thng khng i xng, tc l s dng tn

hiu in p chnh lch gia mt dy dn v t. Do ngay t u tin ra i n
mang v li thi ca chun TTL, n vn s dng cc mc in p tng thch TTL
m t cc mc logic 0 v 1. Ngoi mc in p tiu chun cng c nh cc gi tr tr
khng ti c u vo bus ca b phn v cc tr khng ra ca b pht.
Mc in p ca tiu chun RS232C (chun thng dng by gi) c m t
nh sau:
Mc logic 0: +3V , +12V.
Mc logic 1: -12V, -3V.
Cc mc in p trong phm vi t -3V n 3V l trng thi chuyn tuyn.
Chnh v t - 3V ti 3V l phm vi khng c nh ngha, trong trng hp thay i
gi tr logic t thp ln cao hoc t cao xung thp, mt tn hiu phi vt qua qung
qu trong mt th gian ngn hp l. iu ny dn n vic phi hn ch v in
dung ca cc thit b tham gia v ca c ng truyn. Tc truyn dn ti a ph
thuc vo chiu di ca dy dn. a s cc h thng hin nay ch h tr vi tc 19,
2 kBd .
4.5
CNG RS232 TRN PC.
Hu ht cc my tnh c nhn hin nay u c trang b t nht l 1 cng Com

hay cng ni tip RS232. S lng cng Com c th ln ti 4 ty tng loi main my
tnh. Khi cc cng Com c nh du l Com 1, Com 2, Com 3...Trn c 2
loi u ni c s dng cho cng ni tip RS232 loi 9 chn (DB9) hoc 25 chn
(DB25). Tuy hai loi u ni ny c cng song song nhng hai loi u ni ny c
phn bit bi cng c (DB9) v cng ci (DB25).
Ta xt s chn cng Com 9 chn:
Trang 63
Hnh 4.1 K hiu chn v hnh dng ca cng COM DB9

Chc nng ca cc chn nh sau:
Chn 1: Data Carrier Detect (DCD): Pht tn hiu mang d liu.
Chn 2: Receive Data (RxD): Nhn d liu.
Chn 3: Transmit Data (TxD): Truyn d liu.
Chn 4: Data Termial Ready (DTR) : u cui d liu sn sng c

kch hot bi b phn khi mun truyn d liu.
Chn 5: Singal Ground ( SG) : Mass ca tn hiu.
Chn 6: Data Set Ready (DSR) : D liu sn sng, c kch hot bi

b truyn khi n sn sng nhn d liu.
Chn 7: Request to Send : yu cu gi, b truyn t ng ny ln mc

hot ng khi sn sng truyn d liu.
Chn 8: Clear To Send (CTS) : Xa gi , b nhn t ng ny ln

mc kch hot ng thng bo cho b truyn l n sn sng nhn tn hiu.
Chn 9: Ring Indicate (RI) : Bo chung cho bit l b nhn ang nhn
tn hiu rung chung.
Cn DB25 by gi hu ht cc main mi ra u khng c cng ny na. Nn
ti khng cp n y.
4.6
QU TRNH D LIU.
Truyn d liu qua cng ni tip RS232 c thc hin khng ng b. Do vy

nn ti mt thi im ch c mt bit c truyn (1 k t). B truyn gi mt bit bt
u (bit start) thng bo cho b nhn bit mt k t s c gi n trong ln truyn
bit tip the . Bit ny lun bt u bng mc 0. Tip theo l cc bit d liu (bits data)
c gi di dng m ASCII (c th l 5, 6, 7 hay 8 bit d liu). Sau l mt Parity
Trang 64
bit ( Kim tra bit chn, l hay khng) v cui cng l bit dng - bit stop c th l 1,
1.5 hay 2 bit dng.
4.6.1 Tc Baud.
y l mt tham s c trng ca RS232. Tham s ny chnh l c trng cho
qu trnh truyn d liu qua cng ni tip RS232 l tc truyn nhn d liu hay cn
gi l tc bit. Tc bit c nh ngha l s bit truyn c trong thi gian 1
giy hay s bit truyn c trong thi gian 1 giy. Tc bit ny phi c thit lp
bn pht v bn nhn u phi c tc nh nhau ( Tc gia vi iu khin v my
tnh phi chung nhau 1 tc truyn bit).
Ngoi tc bit cn mt tham s m t tc truyn l tc Baud. Tc
Baud lin quan n tc m phn t m ha d liu c s dng din t bit c
truyn cn tc bit th phn nh tc thc t m cc bit c truyn.V mt phn
t bo hiu s m ha mt bit nn khi hai tc bit v tc baud l phi ng
nht.
Mt s tc Baud thng dng: 50, 75, 110, 150, 300 , 600, 1200, 2400,
4800, 9600, 19200, 28800, 38400, 56000, 115200 Trong thit b h thng
dng tc l 19200.
Khi s dng chun ni tip RS232 th yu cu khi s dng chun l thi gian
chuyn mc logic khng vt qu 4% thi gian truyn 1 bit. Do vy, nu tc bit
cng cao th thi gian truyn 1 bit cng nh th thi gian chuyn mc logic cng phi
nh. iu ny lm gii hn tc Baud v khong cch truyn.
4.6.2 Bit chn l hay Parity bit.
y l bit kim tra li trn ng truyn. Thc cht ca qu trnh kim tra li
khi truyn d liu l b xung thm d liu c truyn tm ra hoc sa mt s li
trong qu trnh truyn . Do trong chun RS232 s dng mt k thut kim tra chn
l.
Mt bit chn l c b sung vo d liu c truyn cho thy s lng cc
bit "1" c gi trong mt khung truyn l chn hay l.
Trang 65
Mt Parity bit ch c th tm ra mt s l cc li ch hn nh 1, 3, , 5, 7, 9...

Nu nh mt bit chn c mc li th Parity bit s trng gi tr vi trng hp khng
mc li v th khng pht hin ra li. Do trong k thut m ha li ny khng c
s dng trong trng hp c kh nng mt vi bit b mc li.
4.7
S KT NI
C rt nhiu mch giao tip ca RS232 gia vi iu khin hay cc thit b khc.
Di y ta xt mch chun giao tip RS232 dng IC Max232
Max232 l IC chuyn dng cho giao tip gia RS232 v thit b ngoi vi.
Max232 l IC ca hng Maxim. y l IC chay n nh v c s dng ph bin
trong cc mch giao tip chun RS232. Gi thnh ca Max232 ph hp (12K hay
10K) v tch hp trong hai knh truyn cho chun RS232. Dng tn hiu c thit
k cho chun RS232 . Mi u truyn ra v cng nhn tn hiu u c bo v chng
li s phng tnh in ( hnh nh l 15KV). Ngoi ra Max232 cn c thit k vi
ngun +5V cung cp ngun cng sut nh.
Mch giao tip nh sau :
Hnh 4.2: S kt ni COM vi Max232
Trang 66
Chng 5: Thit k mch phn cng iu khin
CHNG 5. THIT K MCH PHN CNG IU KHIN

Mch phn cng iu khin gm cch khi sau y:
Khi ngun nui vi iu khin.

Khi chuyn i tn hiu RS232 thnh TTL dng MAX232.
Khi iu khin ng ngt dng MOC3020 v TRIAC.
5.1
KHI NGUN NUI VI IU KHIN, MCH.
Vi iu khin v cc con linh kin khc trong mch u hot ng vi ngun

nui 5V. Sau y ta xt mch to ngun 5V t ngun xoay chiu 220V v 50Hz nh
sau:
Hnh 5.1: Mch to ngun 5V t in p xoay chiu 220V

Mch ngun gm bin p cch ly T1, n c 2 cng dng:
Va to tnh cch ly gia mch in v ng ngun AC, gi an ton

cho ngi dng.
Va dng lm gim p AC, h mc ngun AC 220V xung 9V.

Dng cu nn dng 4 diode chuyn i dng AC ra dng dng in xung
mt pha.
T C1 dng t ha ln lm kho cha in, n c 3 cng dng:
Gim dn sng.
Nng cao mc p DC ln gn bng mc volt cc i.
Lm kho cha in n nh iu kin cp in cho ti.
Dng Led vi in tr hn dng 1K lm n ch th. c mc p DC 5V

c n nh tt, trong mch dng IC n p 3 chn 7805. Vi loi IC n p tch cc,
trnh mch in trong IC khng pht sinh hin tng dao ng t kch, ng ra
dng thm t ha C2 lm t lc, c th dng thm t lc nh C3 lc b cc tn hiu
nhiu tn cao nhim vo ng ngun. iu cn nh: IC 7805 phi cho gn trn l
nhm lm ngui.
Trang 67
5.2 KHI CHUYN I TN HIU RS232 THNH TTL DNG

MAX232.
5.2.1 Gii thiu v MAX232
Vi mch MAX 232 ca hng MAXIM l mt vi mch chuyn dng trong giao
din ni tip vi my tnh. Chng c nhim v chuyn i mc TTL li vo (T1in v
T2in ) thnh mc T1out , T2out pha truyn v chuyn i R1in , R2in thnh R1out , R2out
pha nhn vi mc in p l +5V n +10V hoc +10V n -10V. ng thi gi tr
in dung trn MAX232 l C1=C2=C3=C4=C5=10F.
Vi mch MAX232 c hai b m v hai b nhn. Chn 9 (R2 OUT) ca vi
mch MAX232 c ni vi ng dn iu khin li vo CTS, iu khin vic xut
ra d liu cng ni tip khi cn thit. Cn chn 10 (T2 IN) ca vi mch MAX232 ni
vi ng dn bt tay iu khin qu trnh nhn. ng dn bt tay c ni vi
cng ni tip qua cu ni, khi khng s dng, chng ta c th h mch. Cch truyn
d liu n gin nht l ch dng ba ng dn TxD, RxD v GND.
5.2.2 S kt ni.
Trang 68
Hnh 5.2: Mch chuyn i tn hiu TTL dng MAX232

5.3
MCH IU KHIN NG NGT TI AC.
Ta c mch iu khin nh sau:
Hnh 5.3: Mch ng ngt ti AC

Ta xt cc linh kin trong mch nh sau:
MOC 3021 l kinh kin tch hp c cu to gm 1 LED v 1 photo diot. Khi c
dng in nh chy qua 2 u ca LED trong OPTO lm cho LED pht sng, khi s
kch cho photo diot dn, cho dng in chy qua. MOC3021 c dng cch ly p
gia 2 khi vi x l v mch cng sut, ng thi trnh nhiu cho ng c. V i lc
ng c chy qu dng th dng tr v ln lm cht linh kin mch cng sut, nu
khng c cch ly quang OPTO th dng in ln s theo ng mch n tiu dit vi
iu khin v ton b linh kin khc.
Triac BTA41 l linh kin chu c dng cao ti 40A, do chu c cng
sut cao. Dng kch cho cc G ca BTA41 khong 50mA. Trong mch ny, BTA41
Trang 69
dn trong 2 trng hp: khi in p trn 2 cc MT2 v G ca triac ng du so vi cc

MT1.
Trang 70
Chng 6: Thit k code v giao din iu khin
CHNG 6: THIT K CODE V GIAO DIN IU KHIN

6.1 THIT K CODE IU KHIN VI X L
6.1.1
tng thit k
Khi cng COM truyn mt k t trong bng m ASCII, vi iu khin s

nhn k t , lu vo thanh ghi so snh. C mi ln nhn 1 chui d liu s so
snh, ng d liu no th s c mt phng thc iu khin mch ring. C th
nh sau:
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
t a m n 1.
t b tt n 1.
t c m n 2.
t d tt n 2.
t e m n 3.
t f tt n 3.
t g m n 4.
t h tt n 4.
t i m n 5.
t j tt n 5.
t k m n 6.
t l tt n 6
t m m n 7.
t n tt n 7.
t o m n 8.
t p tt n 8.
t q tt ht cc n.
Sau mi ln so snh n s xa d liu trong bin gn nhn d liu so snh

tip theo.
Trang 71
6.1.2 Lu gii thut
Hnh 6.1: Lu gii thut code iu khin

6.1.3 Code iu khin
Vit bng trnh hp ng, ta dc code iu khin nh sau:
org 00h
mov SCON, #50h
//truyn d liu 8 bit, 1 bit stop cho php thu
mov TMOD, #20h
//chn Timer 1, ch 2 (t ng np li)
mov TH1, #0FDh
//chn tc Baud 9600
setb TR1
//khi ng Timer 1
jmp main
org 0FFh
main:
jnb RI, $
//ch n khi nhn d liu cui cng
clr RI
//ch sn cho 1 byte k tip
mov A, SBUF
//gn d liu cho thanh ghi A
mo_den1:
cjne A, #'a', tat_den1
//so snh, nu A= a th m n 1
clr P1.0
nu sai th nhy xung lnh tip theo
jmp main
tat_den1:
cjne A, #'b', mo_den2
//so snh, nu A= b th tt n 1
Trang 72
setb P1.0
jmp main
mo_den2:
cjne A, #'c', tat_den2
//so snh, nu A= c th m n 2
clr P1.1
jmp main
tat_den2:
cjne A, #'d', mo_den3
//so snh, nu A= d th tt n 2
setb P1.1
jmp main
mo_den3:
cjne A, #'e', tat_den3
//so snh, nu A= e th m n 3
clr P1.2
jmp main
tat_den3:
cjne A, #'f', mo_den4
//so snh, nu A= f th tt n 3
setb P1.2
jmp main
mo_den4:
cjne A, #'g', tat_den4
//so snh, nu A= g th m n 4
clr P1.3
jmp main
tat_den4:
cjne A, #'h', mo_den5
//so snh, nu A= h th tt n 4
setb P1.3
jmp main
mo_den5:
cjne A, #'i', tat_den5 //so snh, nu A= i th m n 5
clr P1.4
jmp main
tat_den5:
cjne A, #'j', mo_den6
//so snh, nu A= j th tt n 5
setb P1.4
jmp main
mo_den6:
Trang 73
cjne A, #'k', tat_den6
//so snh, nu A= k th m n 6
clr P1.5
jmp main
tat_den6:
cjne A, #'l', mo_den7
//so snh, nu A= l th tt n 6
setb P1.5
jmp main
mo_den7:
cjne A, #'m', tat_den7
//so snh, nu A= m th m n 7
clr P1.6
jmp main
tat_den7:
cjne A, #'n', mo_den8
//so snh, nu A= n th tt n 7
setb P1.6
jmp main
mo_den8:
cjne A, #'o', tat_den8
//so snh, nu A= o th m n 8
clr P1.7
jmp main
tat_den8:
cjne A, #'p', reset_mach
//so snh, nu A= p th tt n 8
setb P1.7
jmp main
reset_mach:
cjne A, #'q', main
//so snh, nu A= q th tt ht n.
setb P1.0
setb P1.1
setb P1.2
setb P1.3
setb P1.4
setb P1.5
setb P1.6
setb P1.7
jmp main
end
Trang 74

6.2
THIT K GIAO DIN IU KHIN
Dng ngn ng lp trnh C# ca b Visual Studio 2008 to ra mt b form

iu khin vi giao din d nhn v d s dng cho ngi iu khin.
u tin m Visual Studio 2008, chn new project.
Sau chon Windows Forms Application v t tn cho chng. a n cho

chng ta mt giao din lp trnh Form.
Sau xy dng thnh biu form iu khin.

Trang 75
Bng cch dng nhng Lable, Button, Checkbox, Combobox, Piturebox trn
thanh Toolbox ko th vo ni thit k form.
Sau i tn thuc tnh, tn hin th nh trn form.

Trang 76
V cui cng ta vit code vo iu khin bng cch click double chut vo
tng thnh phn ca form.
V sao y l ton b code ca chng trnh nh sau:
using System;
using System.Collections.Generic;
using System.ComponentModel;
using System.Data;
using System.Drawing;
using System.Linq;
using System.Text;
using System.Windows.Forms;
using System.IO;
using System.IO.Ports;
using System.Xml;
namespace Giao_dien
{
public partial class Form1 : Form
{
SerialPort P = new SerialPort();
string InputData = string.Empty;
delegate void SetTextCallback(string text);
public Form1()
{
InitializeComponent();
string[] ports = SerialPort.GetPortNames();
Cbcom.Items.AddRange(ports);
P.ReadTimeout = 1000;
string [] BaudRate = { "1200", "2400", "4800", "9600", "19200",
"38400", "57600", "115200" };
Cbbaud.Items.AddRange (BaudRate);
string[] Databits = {"6", "7", "8" };
Cbdata.Items.AddRange(Databits);
string[] Parity = { "None", "Odd", "Even" };
Cbparity.Items.AddRange(Parity);
string[] Stopbit = { "1", "1.5", "2" };
Trang 77
Cbstop.Items.AddRange(Stopbit);
}
private void Cbcom_SelectedIndexChanged(object sender, EventArgs e)
{
if (P.IsOpen)
{ P.Close();
}
P.PortName = Cbcom.SelectedItem.ToString();
}
private void Cbbaud_SelectedIndexChanged(object sender, EventArgs e)
{
if (P.IsOpen)
{ P.Close();
}
P.BaudRate = Convert.ToInt32(Cbbaud.Text);
}
private void Cbdata_SelectedIndexChanged(object sender, EventArgs e)
{
if (P.IsOpen)
{
P.Close();
}
P.DataBits = Convert.ToInt32(Cbdata.Text);
}
private void Cbparity_SelectedIndexChanged(object sender, EventArgs e)
{
if (P.IsOpen)
{
P.Close();
}
switch (Cbparity.SelectedItem.ToString())
{
case "Old":
P.Parity = Parity.Odd;
break;
Trang 78
case "None":
P.Parity = Parity.None;
break;
case "Even":
P.Parity = Parity.Even;
break;
}
}
private void Cbstop_SelectedIndexChanged(object sender, EventArgs e)
{
if (P.IsOpen)
{
P.Close();
}
switch (Cbstop.SelectedItem.ToString())
{
case "1":
P.StopBits = StopBits.One;
break;
case "1.5":
P.StopBits = StopBits.OnePointFive;
break;
case "3":
P.StopBits = StopBits.Two;
break;
}
}
private void Form1_Load(object sender, EventArgs e)
{
Cbcom.SelectedIndex = 0;
Cbbaud.SelectedIndex = 3;
Cbdata.SelectedIndex = 2;
Cbparity.SelectedIndex = 0;
Cbstop.SelectedIndex = 0;
}
Trang 79
private void ketnoi_Click(object sender, EventArgs e)

{
try
{
P.Open();
ngatketnoi.Enabled = true;
ketnoi.Enabled = false;
}
catch (Exception ex)
{
MessageBox.Show("Don't
connect!",
MessageBoxButtons.OK, MessageBoxIcon.Error);
"Information",
}
}
private void ngatketnoi_Click(object sender, EventArgs e)
{
P.Close();
ketnoi.Enabled = true;
ngatketnoi.Enabled = false;
}
private void exit_Click(object sender, EventArgs e)
{
DialogResult kq = MessageBox.Show("Do you want to exit the
program?", "Warning", MessageBoxButtons.YesNo, MessageBoxIcon.Warning);
if (kq == DialogResult.Yes)
{
this.Close();
}
}
private void Ck_den1_CheckedChanged(object sender, EventArgs e)
{
if (Ck_den1.Checked) P.Write("a");
else P.Write("b");
}
Trang 80
{
if (Ck_den2.Checked) P.Write("c");
else P.Write("d");
}
{
if (Ck_den3.Checked) P.Write("e");
else P.Write("f");
}
{
if (Ck_den4.Checked) P.Write("g");
else P.Write("h");
}
{
if (Ck_den5.Checked) P.Write("i");
else P.Write("j");
}
{
if (Ck_den6.Checked) P.Write("k");
else P.Write("l");
}
{
if (Ck_den7.Checked) P.Write("m");
else P.Write("n");
}
{
if (Ck_den1.Checked) P.Write("o");
else P.Write("p");
}
private void reset_Click(object sender, EventArgs e)
Trang 81
{
P.Write("q");
if (Ck_den1.Checked) Ck_den1.Checked = false;
}
}
}
Trang 82

6.3
MCH NGUYN L
V1
VAC 220V 50 Hz
R31 470
R30 360
R29
330
Q8
BTA41 A1A2G
R32
39
U10
C22
0.05uF
J1
C21
0.01uF
R27
R28
470
Q7
BTA41 A1A2G
39
R25
R26 360
LOAD
MOC3021
4
1
2
330
U9
C20
0.05uF
J2
1
2
C19
0.01uF
MOC3021
4
1
2
LOAD
R21
R23
330
R22360
470
Q6
BTA41 A1A2G
R24
39
U8
C18
0.05uF
J3
C17
LOAD
0.01uF
MOC3021
4
1
2
R17
R19
330
R18360
470
Q5
BTA41 A1A2G
R20
39
U7
C16
0.05uF
J4
C15
0.01uF
MOC3021
4
1
2
LOAD
R13
470
Q4
BTA41 A1A2G
R14360
R15
R16
39
330
U6
C14
0.05uF
J5
C13
0.01uF
LOAD
MOC3021
4
1
2
R10 360
R9
R11
470
Q3
BTA41 A1A2G
R12
39
330
U5
C12
0.05uF
J6
1
2
C11
0.01uF
MOC3021
4
1
2
LOAD
R5
R7
470
U3
U1
C1
0.01uF
MOC3021
4
1
2
R1
LOAD
R3
470
39
R2 360
C4
0.05uF
J8
C5
0.01uF
2
MOC3021
4
1
2
1
2
3
4
5
6
7
8
U2
C2 30uF
19
18
LOAD
Y1
C3 30uF
12 MHz
31
9
40
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P1.0/T2
P1.1/T2-EX
P1.2
P1.3
P1.4/SS
P1.5/MOSI
P1.6/MISO
P1.7/SCK
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL1
XTAL2
ALE/PROG
PSEN
21
22
23
24
25
26
27
28
P1
10
11
12
13
14
15
16
17
U4
13
8
11
10
30
29
C9
10uF
EA/VPP
RST
VCC
C6
10uF
C8
10uF
20
Q1
BTA41 A1A2G
330
R4
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
AT89S8252
1
3
4
5
2
6
16
39
38
37
36
35
34
33
32
R1IN
R2IN
VCC
J7
T1IN
T2IN
C1+
C1C2+
C2V+
V-
R1OUT
R2OUT
T1OUT
T2OUT
12
9
14
7
1
6
2
7
3
8
4
9
5
CONNECTOR DB9
GND
C10
0.05uF
15
R33 360
GND
Q2
BTA41 A1A2G
330
R8
39
MAX232
C7
10uF
V2
VDC 5V
Trang 83

6.4
MCH M PHNG
Trang 84
Chng 7: Hng pht trin ca ti
CHNG 7: HNG PHT TRIN CA TI

ti nghin cu vic p dng k thut vi x l i vi cc thit b dn dng
cng sut thp v va, vic iu khin ch trong phm vi hp, v th chng ta cn ci
tin thm trong tng lai.
Hin ti vic iu khin ch c thc hin ti mt v tr vi iu kin my tnh
c cng COM, v th vic iu khin cha c linh hot. hon thin hn h thng,
chng ta c th nghin cu thm vic iu khin qua cc sng in t, sng AM, FM,
Bluetooth, wireless v ngay c Internet.
Tng bc nng cao cng sut ti tiu th, p dng thm nhng tin b ca k
thut vi x l vo mch gip hot ng tt hn, n nh hn. ng thi nghin cu
thm vic thit k giao din cho d iu khin.
Tng bc p dng k thut vi iu khin vo i sng, gip ngi c, ngi
s dng nm bt kp thi nhng tin b, gip sinh vin tng bc hon thin c
kin thc nn tng v nng cao kh nng nghin cu ca mnh.
Trang 85
Ti liu tham kho
TI LIU THAM KHO
Tng Vn n, H Vi iu Khin 8051, MK PUB
Ths Nguyn Hu Duy Khang, KS: Trn Hu Danh, Lp Trnh H

Thng, H Cn Th.
Phm Vn Cng, Lp Trnh H Thng V iu Khin Thit B, Hc

Vin Cng Ngh Bu Chnh Vin Thng.
L V H, Gio Trnh K Thut iu Khin, i Hc Quc Gia Thanh

Ph H Ch Minh.
Kenneth Ayala (Author),

Programming And Applications.
8051
Microcontroller:
Architecture,
Din n dientuvietnam.com, ...
Trang 86
Ph lc 1
PH LC 1
LIT K HNH
Hnh 2.1: S chn AT89S8252 .........................................................................................8

Hnh 2.2 Dao ng trn chip vi thch anh ..........................................................................9
Hnh 2.3: Cu trc b nh trn AT89S8252 ...................................................................... 11
Hnh 2.4: Bn cc thanh ghi c bit............................................................................. 14
Hnh 2.5: S khi Port ni tip ...................................................................................... 32
Hnh 2.6: S b x l a knh AT89S8252 ................................................................. 36
Hnh 2.7: Timer 2 trong ch Capture............................................................................. 48
Hnh 2.8: Timer 2 trong ch Auto Reload .................................................................... 49
Hnh 2.9: Timer 2 trong ch Auto-Reload .................................................................... 49
Hnh 2.10: Timer 2 trong ch Baud Rates Generator .................................................. 50
Hnh 4.1 K hiu chn v hnh dng ca cng COM DB9............................................... 64
Hnh 4.2: S kt ni COM vi Max232........................................................................ 66
Hnh 5.1: Mch to ngun 5V t in p xoay chiu 220V ............................................ 67
Hnh 5.2: Mch chuyn i tn hiu TTL dng MAX232 ............................................... 69
Hnh 5.3: Mch ng ngt ti AC ....................................................................................... 69
Hnh 6.1: Lu gii thut code iu khin ..................................................................... 72
Trang 87
Ph lc 2
PH LC 2
LIT K BNG
Bng 2.1: Chc nng chuyn i Port 1 ............................................................................8

Bng 2.2: Cc chc nng chuyn i Port 3......................................................................9
Bng 2.3: Tm tt thanh ghi PSW ...................................................................................... 14
Bng 2.4: Tm tt thanh ghi IE (Interrupt Register)......................................................... 17
Bng 2.5: Tm tt thanh ghi PCON .................................................................................... 18
Bng 2.6: Thanh ghi iu khin b nh v Watchdog ..................................................... 19
Bng 2.7: Thanh ghi iu khin SPI ................................................................................... 20
Bng 2.8: Thanh ghi trng thi SPI ..................................................................................... 21
Bng 2.9: Tm tt thanh ghi SCON .................................................................................... 33
Bng 2.10: Bng MODE hot ng ca Port ni tip. ..................................................... 33
Bng 2.11: Tm tt tc Baud ph bin ......................................................................... 38
Bng 2.12: Cc thanh ghi truy sut Timer 0 v Timer 1 .................................................. 39
Bng 2.13: Tm tt hot ng thanh ghi TMOD .............................................................. 40
Bng 2.14: Hot ng 2 bt M0 v M1 ............................................................................... 40
Bng 2.15: Tm tt hot ng thanh ghi TCON ............................................................... 41
Bng 2.16: Hot ng Timer 2 ............................................................................................ 46
Bng 2.17: Chc nng tng bt T2CON............................................................................. 46
Bng 3.1 S chn ca my in ......................................................................................... 52
Bng 3.2: a ch c s cc tthanh ghi cng song song ................................................... 53
Bng 3.3: ngha c a cc chn cng ni tip................................................................... 55
Trang 88

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LI M U

Nhm Sinh Vin

iu khin thit b qua PC

I TNG NGHIN CU V PHM VI NGHIN CU ..........................6

i tng nghin cu. .......................................................................................6

Phm vi nghin cu............................................................................................6

CHNG 2: TM HIU VI IU KHIN AT89S8252 ..............................................7

CU TRC VDK AT89S8252, CHC NNG TNG CHN ........................7

Cc bng thanh ghi (Register Banks). .......................................................... 12

Cc thanh ghi chc nng c bit (Special Function Register). ................ 13

TM TT TP LNH CA AT89S8252 ......................................................... 21

Cc ch nh v ( addressing mode ) ....................................................... 21

2.4.1.1 S nh v thanh ghi ( Register Addressing) ............................................ 21

iu khin thit b qua PC

2.4.1.4 S nh v a ch tc thi (Immediate Addressing) ............................... 23

Cc kiu lnh (instruction types) ................................................................... 25

2.4.2.1 Cc lnh s hc (Arithmetic Instrustion): ................................................ 25

HOT NG CA PORT NI TIP AT89S8252. ........................................ 31

Gii thiu .......................................................................................................... 31

Cc mode hot ng (Mode Of Operation) ................................................. 33

S khi ng, truy xut cc thanh ghi port ni tip.................................... 34

2.5.4.1 S cho php b thu (Recive Enable) ......................................................... 34

S truyn ca b x l a knh ................................................................. 35

HOT NG TIMER CA AT89S8252 .......................................................... 39

Gii thiu .......................................................................................................... 39

Timer 0 v Timer 1 ......................................................................................... 39

2.6.2.1 Thanh ghi iu khin Timer TCON (Timer Control Register).............. 41

iu khin thit b qua PC

2.6.2.4 S bt u, kt thc v s iu khin cc Timer (Starting, Stoping And

2.6.3.1 Thanh ghi T2CON (Timer/Counter 2 Control Register) ........................ 46

GIAO TIP CNG SONG SONG (CNG MY IN) ..................................... 51

Khong cch ghp ni .................................................................................... 51

Tc truyn d liu ...................................................................................... 51

Cu trc cng song song................................................................................. 51

Cc thanh ghi cng song song. ................................................................... 53

GIAO TIP CNG NI TIP (RS232) ............................................................. 53

Cu trc cng ni tip. .................................................................................... 53

Truyn thng ni tip gia 2 nt. .................................................................. 56

TM HIU V USB ............................................................................................... 57

Khi nim ......................................................................................................... 57

M rng cng USB ......................................................................................... 58

Cc t tnh ca USB ...................................................................................... 59

USB 2.0 ............................................................................................................ 60

USB 3.0 ............................................................................................................ 60

CHNG 4: CHUN TRUYN THNG NI TIP RS232.................................. 62

U IM CA GIAO DIN NI TIP RS232. ............................................. 62

NHNG C IM CN LU TRONG CHUN RS232. ..................... 62

CNG RS232 TRN PC....................................................................................... 63

QU TRNH D LIU. ....................................................................................... 64

iu khin thit b qua PC

Bit chn l hay Parity bit. .............................................................................. 65

CHNG 5. THIT K MCH PHN CNG IU KHIN ............................. 67

KHI NGUN NUI VI IU KHIN, MCH. ........................................... 67

KHI CHUYN I TN HIU RS232 THNH TTL DNG MAX232... 68

Gii thiu v MAX232 ................................................................................... 68

MCH IU KHIN NG NGT TI AC. ................................................ 69

CHNG 6: THIT K CODE V GIAO DIN IU KHIN.......................... 71

THIT K CODE IU KHIN VI X L .................................................... 71

tng thit k ............................................................................................... 71

Lu gii thut ............................................................................................. 72

Code iu khin ............................................................................................... 72

THIT K GIAO DIN IU KHIN .............................................................. 75

MCH NGUYN L ........................................................................................... 83

CHNG 7: HNG PHT TRIN CA TI................................................. 85