Electronic System Level (ESL) Design Design SoC

2008. 10

(joonhwan.yi@kw.ac.kr) joonhwan.yi@kw.ac.kr)

ESL design ESL design


ESL design
Background Electronic system level (ESL) design ESL design tasks

ESL design

Background

Design Productivity Gap

10,000 10,000,000 1,000 1,000,000 100 100,000 10 10,000 1 1,000 0.1 100
xx x xx x x x

Complexity Logic Transistor per Chip (M) C

100,000 100,000,000

1,000 1,000,000 58%/Yr. compounded Complexity growth rate 100 100,000 10 10,000 21%/Yr. compound Productivity growth rate 1 1,000 0.1 100 0.01 10

0.01 10 0.001 1

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

Source: Sematech, ITRS (international technology roadmap for semiconductor)

Complexity outpaces design productivity

Demands for Complex Designs

Example: Data transfer rate for communication standards
2G (GSM/GPRS/EDGE/CDMA2000 1x) ( ) 3G (WCDMA/CDMA2000 1x EV-DO Beyond 3G (HSPA/WiBro/LTE) 4G 100 Kbps p ~ 3 Mbps 10 ~ 200 Mbps 100 Mbps ~ 1 Gbps 10,000 x

Example: Mobile convergence
Voice + broadcasting + entertainment + camera + security + etc.

On-chip communications/computations consume less power than off-chip ones

2009

Productivity (K) Trans./Staff - Mo.

Logic Tr./Chip Tr./Staff M th T /St ff Month.

10,000 10,000,000

Architecture Matters
Complex design means more functionality, more data movement, more computation on SoCs
The performance of each IP as well as SoC architecture matters

Efforts to h Eff t t enhance S C performance SoC f

HW SW IP

IP : multi-processor SoC (MPSoC)

???

IP HW-SW interaction =
Architecture design based on scientific analysis is necessary

design productivity IP productivity !! !!

Slow simulation time problem

SoC

Higher Level of Design Abstractions

higher level of design abstraction design productivity
Transistor level gate level electronic system level (ESL) Hide unnecessary details Higher simulation speed Cope with more complex designs
Higher level of abstraction

register transfer level (RTL)

Higher level of design abstraction f

Time 2000s 1990s 1980s 1970s

Level of abstractions Electronic system level RTL Gate level Transistor level

Design size 10M+

Languages C/C++/SystemC

100K ~ 10M Verilog, VHDL 1K ~ 100K ~ 1K Schematic SPICE netlist, layout

Design Cost for Mobile SoCs

Electron system nic level (E ESL) design

: 2005 ITRS

Design cost increases exponentially

Electronic System Level (ESL) Design

Electronic System Level (ESL)

An abstraction level of electronic circuit designs
Higher than register transfer level (RTL) Lower than algorithm level
Design abstraction Function accuracy Cycle accuracy Communication method Description languages RTL
Flip-flop level

ESL
Register accurate level Bus-functional level Both (with or without cycle accuracy) are possible Signal Transaction Function calls C/C++/SystemC

Algorithm level
Behavior level

Cycle accurate

No timing

Signal (bit-level)

Function calls

Hardware description language (Verilog, VHDL)

C/C++/SystemC

abstraction layer
1: bus-functional transaction level model w/ cycle-accuracy () 2: bus-functional transaction level model w/o cycle-accuracy (SW )

Popular Levels in ESL

Programmers view (PV) register accurate but no timing Architectural view (AV) register accurate & cycle approximate Verification view (VV) register and cycle accurate
Processors / Accelerators
CPUs DSPs Interrupt controller, DMA controller, etc. HW accelerators
Software

Memory

On-chip communication
Software

Memory controller

- Bus fabric - Arbiter, bus matrix - Bus bridges

CPU CPU

DSP DSP GPS MPEG Bus bridge

Interfaces & host models

- USIM, SDIO, USB, PCMCIA, UART, etc. - Corresponding host models - CDMA/Wibro modem & basestation models

SoC
USIM SDIO USB

Software
PCMCIA Modem

- OS, device driver - Middleware - Application software

Host

Host

Host

Host

Basestation

ESL Design
Efficient hardware-software co-design in early design stage
/ hardware-software co-simulation

Availability Simulation Simulation Hardware-software co-design

ESL design (Virtual platform) (Vi l l f )

Early ( ) (RTL 3000 )

RTL
Late ( ~ )

FGPA
Very late ( ~ )

Early Stage Performance Analysis

ESL design
Requirements / specification

& margin Infeasible region solution poor quality solution

Architecture exploration
ESL

Behavioral synthesis
RTL

Logic/physical synthesis
Gate-level

Logic/physical synthesis

Layout

Layout

Infeasible region

Infeasible solution Optimum solution Refinement-needed solution

Early Stage Performance Analysis

Infeasible region
Requirements / specification

Simulation speed
Architecture exploration @ ESL

Abstraction
Behavioral synthesis
RTL model

Flexibility

Logic/physical synthesis

Gate-level model

Accuracy Analysis time Modeling efforts

Layout

Trade-offs between accuracy, analysis time, modeling efforts, and design flexibility between abstraction levels

ESL Design
Requirements HW IPs SW IPs

IP
(algorithm / SW)

IPs

+
ESL 1

HW-SW partitioning

Late HW-SW co-verification

Yes

Architecture exploration

ESL 2

Architecture

Initial architecture

Architecture design

Architecture design

ESL 3
Implementation

HW-SW coverification

Implementation

Early HW-SW co-verification

Verification

Verification

HW on silicon + SW (integration + verification)

Time to silicon advantage

Problem?

No
Success

Time to market advantage

ESL Design Tasks

ESL Design Tasks

Architecture exploration Parallel development of hardware and software HardwareHardware-software partitioning HardwareHardware-software co-verification coPerformance analysis RTL generation Power analysis

Architecture Exploration
P Performance Legend Initial architecture

Infeasible region Poor quality region

(with ( i h same d i design effort) ff ) gate-level RTL ESL Specification

Exploration space at different abstraction levels

Optimum O ti architecture curve

Intersection of the curve within a circle represents the set of optimum architecture solutions searchable at the abstraction level

Cost

HardwareHardware-Software Co-Design Co
Sequential development: hardware software

ESL design design

Parallel development: hardware software

Old flow

Architecture

Hardware

Software

New fl N flow

Architecture A hit t ESL design

Hardware H d ESL design Software

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HardwareHardware-Software Partitioning
Definition
A process that makes decisions whether a required functionality of a system is more advantageously implemented in hardware or in software Fundamental phase of hardware-software co-design p g

ESL design technique plays an crucial role

Fast iterative performance analysis is essential
Start with all HW (or SW) implementation

ESL design

Is the performance requirement met?

No

Change HW-SW partitions Reschedule jobs

Yes

ESL design

Is it optimum? Yes

No

Optimum system architecture

HardwareHardware-Software Co-Verification Co sequential development

Hardware-software co-verification Big surprise (/ ) long iteration

ESL design parallel development design

Hardware-software co-verification co-verification big surprise iteration Old flow Architecture Hardware Long iterations New flow Architecture ESL design
Short iterations

Software

Hardware ESL design Software

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Performance Analysis
ESL design tool data
Function call trace F i ll Cache hit rate Function execution time Variable value

Information (Data )
Function call overhead F i ll h d Cache size optimization Software execution time Software bug

SW

HW

Bus and signal waveform Bus utilization Register value waveform

HW-SW co-verification Bus & system architecture Hardware initialization

System

HW & SW data

System performance HW-SW partitioning system

RTL Generation
Behavioral synthesis
Automatic ESL to RTL mapping

Architecture design

ESL design
Architecture exploration

Initial architecture document

ESL design
Behavioral synthesis (RTL generation)

Initial software

Hardware design Start from scratch

Software design Start from scratch

Hardware design

Software design

Broken links (manual conversion)

Short time for RTL generation Short time for HW-SW co-verification

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Power Analysis
Why ESL power analysis?
Realistic scenario for power analysis Short analysis time for power analysis Base for system (HW & SW) power optimization

: ESL power analysis flow

Scenario @ESL & analysis @RTL
Realistic scenario

ESL RTL

Analysis speed

PowerTheater-ESL ORINOCO Mapae () p PowerTheater PrimePower PowerTheater PrimePower PowerMill HSPICE

Unrealistic scenario

Gate-level Transistor-level

Analysis

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