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RISC-V Memory Module Design in Verilog

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engrmm101
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14 views1 page

RISC-V Memory Module Design in Verilog

Uploaded by

engrmm101
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

module riscv_memory (

input wire clk, // Clock signal


input wire reset_n, // Asynchronous reset (active low)
input wire wr_en, // Write enable (1 = write, 0 = read)
input wire [31:0] addr, // Address for memory access
input wire [31:0] write_data, // Data to write into memory
output reg [31:0] read_data // Data read from memory
);

// Memory array: assuming a memory of 1024 32-bit words


reg [31:0] memory_array [0:1023];

// Memory read/write logic


always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
// Reset logic: you can initialize memory here if needed
read_data <= 32'b0;
end else if (we) begin
// Write operation
memory_array[addr[9:0]] <= write_data; // Write data at the address
(considering only 10 LSBs for 1024 memory)
end else begin
// Read operation
read_data <= memory_array[addr[9:0]]; // Read data from the address
end
end
endmodule

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