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Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com The Address Bus consists of 16 wires, therefore Its "width" is 16 bits. A 16 bit Address bus can identify 2^16=65536 memory locations i.e. 0000000000000000 up to 1111111111111111. Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg 00000000000000 11 (3 in decimal), to the memory. The memory the selects box number 3 for reading or writ ing data. Address bus is unidirectional, ie numbers only sent from microprocessor to memor y, not other way. D ata Bus Data Bus: carries .8-bit data., in binary form, between P and other external unit s, such as memory. The Data Bus typically consists of 8 wires. Data bus used to transmit "d ata", i.e. information, results of arithmetic, etc, between memory and P. Bus is bi-directio nal. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then larges t number is 11111111 (255 in decimal). Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instruct ions to 256, each specified by a separate number. Control Bus It is a group of various single lines used to provide control and synchronizatio n signals. P generates different control signals for different operations. These signals are used to identify the device with which the P wants to communicate.

7. What are tri-state devices and why they are essential in a bus oriented syste m? Tri state logic devices have three states (0, 1 and high impedance). When the en able (may be active high or active low) line is activated, the device works. The disabled enable line makes the device at high impedance state and it is disconnected from the circuit. For example see the tri stated inverter in the figure shown. In microcomputer system the peripherals are connected in parallel between addres s bus and data bus. Because of tri stated interfacing devices, peripherals do not load the sys tem buses. Processor communicates with one peripheral or device at a time by enabling the tri state l ine of the interfacing peripheral or device. Tri state logic is critical to proper function ing of the microcomputer. 8. Why are program counter and stack pointer 16-bit registers? Because SP points to the beginning of stack memory (LXI SP 8000H) which is 16-bi ts. Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Also PC points to the memory locations (16-bits) of the instructions to be excec uted to maintain the proper sequence of execution of program. 9 . What are the different addressing modes in 8085? Register:Data is provided through the registers. Or operand is only register(s). Example: MOV Rd, Rs. Register indirect:Operand M or register pair. Example: MOV A,M; LDAX B; STAX D; MVI M,32H (excepti on for immediate addressing mode). D irect:Operand 8-bit port address or 16-bit memory address. Example: IN 84H, OUT 84H, a ll CALLs. Immediate:Instruction having the letter I. Or immediate data to the destination provided. Also all jump instructions as the meaning is jump immediately. Example MVI M, 2H; ADI 47H; LXI H 2050 (exception for direct addressing mode). Implicit:No operand. Example: XCHG. 10. What is the difference between MOV and MVI? Opcode Operand Bytes M-cycles T-states MOV Rd, Rs, M, Rs, Rd, M 1 1 2 2 4 7 7 MVI reg, data

M, data 2 2 2 3 7 10 Rd = Destination register, Rs = Source register, M =Memory location pointed out by HL register pair, reg =Regiser, data = 8-bit data. 11. What are the functions of RIM, SIM, IN? Read Interrupt Mask (RIM): RIM is a multipurpose instruction used to read the status of interrupts 7.5, 6.5 , 5.5 and to read serial input data bit. RIM loads 8-bit data in the accumulator with the followin g interpretation: Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Actually RIM does the following three tasks: Read the interrupt mask (bit 2, 1, 0). Identify pending interrupts (bit 6, 5, 4). Receive serial input data bit (bit 7). Set Interrupt Mask: SIM is a multipurpose interrupt used to implement the 8085 interrupts (RST 7.5, 6.5, 5.5) and serial data output. SIM interprets the accumulator content as follows: Actually, SIM does the following three tasks: * Mask the interrupts (bit 2, 1, 0). * Reset RST 7.5 (bit 4). This is mainly used to overwrite RST 7.5 without servin g it. * To implement serial I/O (bit 7, 6). If bit 6 = 1 is used to enable serial I/O and bit 7 is used to transmit serial output data bit. Input D ata to Accumulator from a Port with 8-bit Address (IN) The contents of the input port designated in the operand are read and loaded int o the accumulator. The operand is an 8-bit address. During execution, this port addres s is duplicated in the lower order and higher order address buses. Any one of the sets of address l ines can be decoded to enable the input port. 12. What are the different flags in 8085? The 8085 has 5 flags represented by 5 bits of the flag register which are set or reset after an operation according to data conditions of the result (of that operation) stor ed in the accumulator and other registers. They are:Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Sign flag (S):- For D7=1 or 0, S=set (result is unsigned) or reset (result is si

gned). Zero flag (Z):- For the result containing 00H, Z=set, for non zero result Z=rese t. Auxiliary carry flag (Ac):- For any result generating a carry / borrow in the D3 bit position and passing it to D4 bit position, Ac=set. Else it is reset. Parity flag (P):- For a result containg even number of 1s there is even parity a nd odd number of 1s there is odd parity. Carry flag (Cy):- For the result generating any carry Cy is set else reset. 13. What happens during D MA transfer? To make a fast data transfer, the MPU releases the control of its buses to DMA. DMA acts as an external device and the active high input signal HOLD goes HIGH when the DMA is requesting to the MPU to use its buses. After receiving the HOLD request from DM A, the MPU releases the buses in the following machine cycle and generates an active high o utput signal HLDA indicating the release of buses. Once the DMA gains that control, it acts i n the role of the MPU for data transfer. 14. What is PSW? PSW (Program Status Word) represents the contents of the accumulator and the fla g register together considering the accumulator as the high order and flag as the low order register as if it is the AF register pair. For example POP PSW. 15. What is ALE? Explain the functions of ALE in 8085. It is the acronym for Address Latch Enable (pin number 30) used to demultiplex t he multiplexed lower order address/data bus. During T1 the ALE goes HIGH. When ALE goes HIGH, the latch is enabled. So the o/p changes according to the i/p data. During T1 the o/p of latch is 05H. When ALE goes LOW, the data byte 05H is latched until the next ALE . And after the latching operation the o/p of the latch represents the lower order address b us A0-A7. The following figure will illustrate the function: Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com 16. Which line will be activated when an output device require attention from CP U? Interrupt Request (INTR, pin 10, it is an input signal to P). It goes high when t he external devices want to communicate. 17. Can an RC circuit be used as clock source for 8085? Yes, it can be used, if an accurate clock frequency is not required. Also, the c omponent cost is low compared to LC or Crystal. 18. Which interrupt is not level-sensitive in 8085? RST 7.5 is a raising edge-triggering interrupt. 1 9 . What does Quality factor mean?

The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of a circuit. Higher the Q, the lower are the losses. 20. What are level-triggering interrupt? RST 6.5 & RST 5.5 are level-triggering interrupts. 21. Comparison between full address decoding and partial address decoding? Full Address D ecoding Partial Address decoding 1. All higher address lines are decoded to select the memory or I/O device. 1. Few higher address lines are decoded to select the memory or I/O device. 2. More hardware is required to design 2. Hardware required to design decoding l ogic

Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com The Address Bus consists of 16 wires, therefore Its "width" is 16 bits. A 16 bit Address bus can identify 2^16=65536 memory locations i.e. 0000000000000000 up to 1111111111111111. Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg 00000000000000 11 (3 in decimal), to the memory. The memory the selects box number 3 for reading or writ ing data. Address bus is unidirectional, ie numbers only sent from microprocessor to memor y, not other way. D ata Bus Data Bus: carries .8-bit data., in binary form, between P and other external unit s, such as memory. The Data Bus typically consists of 8 wires. Data bus used to transmit "d ata", i.e. information, results of arithmetic, etc, between memory and P. Bus is bi-directio nal. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then larges t number is 11111111 (255 in decimal). Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instruct ions to 256, each specified by a separate number. Control Bus It is a group of various single lines used to provide control and synchronizatio n signals. P generates different control signals for different operations. These signals are used to identify the device with which the P wants to communicate. 7. What are tri-state devices and why they are essential in a bus oriented syste m? Tri state logic devices have three states (0, 1 and high impedance). When the en

able (may be active high or active low) line is activated, the device works. The disabled enable line makes the device at high impedance state and it is disconnected from the circuit. For example see the tri stated inverter in the figure shown. In microcomputer system the peripherals are connected in parallel between addres s bus and data bus. Because of tri stated interfacing devices, peripherals do not load the sys tem buses. Processor communicates with one peripheral or device at a time by enabling the tri state l ine of the interfacing peripheral or device. Tri state logic is critical to proper function ing of the microcomputer. 8. Why are program counter and stack pointer 16-bit registers? Because SP points to the beginning of stack memory (LXI SP 8000H) which is 16-bi ts. Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Also PC points to the memory locations (16-bits) of the instructions to be excec uted to maintain the proper sequence of execution of program. 9 . What are the different addressing modes in 8085? Register:Data is provided through the registers. Or operand is only register(s). Example: MOV Rd, Rs. Register indirect:Operand M or register pair. Example: MOV A,M; LDAX B; STAX D; MVI M,32H (excepti on for immediate addressing mode). D irect:Operand 8-bit port address or 16-bit memory address. Example: IN 84H, OUT 84H, a ll CALLs. Immediate:Instruction having the letter I. Or immediate data to the destination provided. Also all jump instructions as the meaning is jump immediately. Example MVI M, 2H; ADI 47H; LXI H 2050 (exception for direct addressing mode). Implicit:No operand. Example: XCHG. 10. What is the difference between MOV and MVI? Opcode Operand Bytes M-cycles T-states MOV Rd, Rs, M, Rs, Rd, M 1 1 2 2 4 7 7 MVI reg, data M, data 2 2

2 3 7 10 Rd = Destination register, Rs = Source register, M =Memory location pointed out by HL register pair, reg =Regiser, data = 8-bit data. 11. What are the functions of RIM, SIM, IN? Read Interrupt Mask (RIM): RIM is a multipurpose instruction used to read the status of interrupts 7.5, 6.5 , 5.5 and to read serial input data bit. RIM loads 8-bit data in the accumulator with the followin g interpretation: Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Actually RIM does the following three tasks: Read the interrupt mask (bit 2, 1, 0). Identify pending interrupts (bit 6, 5, 4). Receive serial input data bit (bit 7). Set Interrupt Mask: SIM is a multipurpose interrupt used to implement the 8085 interrupts (RST 7.5, 6.5, 5.5) and serial data output. SIM interprets the accumulator content as follows: Actually, SIM does the following three tasks: * Mask the interrupts (bit 2, 1, 0). * Reset RST 7.5 (bit 4). This is mainly used to overwrite RST 7.5 without servin g it. * To implement serial I/O (bit 7, 6). If bit 6 = 1 is used to enable serial I/O and bit 7 is used to transmit serial output data bit. Input D ata to Accumulator from a Port with 8-bit Address (IN) The contents of the input port designated in the operand are read and loaded int o the accumulator. The operand is an 8-bit address. During execution, this port addres s is duplicated in the lower order and higher order address buses. Any one of the sets of address l ines can be decoded to enable the input port. 12. What are the different flags in 8085? The 8085 has 5 flags represented by 5 bits of the flag register which are set or reset after an operation according to data conditions of the result (of that operation) stor ed in the accumulator and other registers. They are:Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com Sign flag (S):- For D7=1 or 0, S=set (result is unsigned) or reset (result is si gned). Zero flag (Z):- For the result containing 00H, Z=set, for non zero result Z=rese t.

Auxiliary carry flag (Ac):- For any result generating a carry / borrow in the D3 bit position and passing it to D4 bit position, Ac=set. Else it is reset. Parity flag (P):- For a result containg even number of 1s there is even parity a nd odd number of 1s there is odd parity. Carry flag (Cy):- For the result generating any carry Cy is set else reset. 13. What happens during D MA transfer? To make a fast data transfer, the MPU releases the control of its buses to DMA. DMA acts as an external device and the active high input signal HOLD goes HIGH when the DMA is requesting to the MPU to use its buses. After receiving the HOLD request from DM A, the MPU releases the buses in the following machine cycle and generates an active high o utput signal HLDA indicating the release of buses. Once the DMA gains that control, it acts i n the role of the MPU for data transfer. 14. What is PSW? PSW (Program Status Word) represents the contents of the accumulator and the fla g register together considering the accumulator as the high order and flag as the low order register as if it is the AF register pair. For example POP PSW. 15. What is ALE? Explain the functions of ALE in 8085. It is the acronym for Address Latch Enable (pin number 30) used to demultiplex t he multiplexed lower order address/data bus. During T1 the ALE goes HIGH. When ALE goes HIGH, the latch is enabled. So the o/p changes according to the i/p data. During T1 the o/p of latch is 05H. When ALE goes LOW, the data byte 05H is latched until the next ALE . And after the latching operation the o/p of the latch represents the lower order address b us A0-A7. The following figure will illustrate the function: Microprocessor 8085 http://saravanamoorthy-physics.blogspot.com 16. Which line will be activated when an output device require attention from CP U? Interrupt Request (INTR, pin 10, it is an input signal to P). It goes high when t he external devices want to communicate. 17. Can an RC circuit be used as clock source for 8085? Yes, it can be used, if an accurate clock frequency is not required. Also, the c omponent cost is low compared to LC or Crystal. 18. Which interrupt is not level-sensitive in 8085? RST 7.5 is a raising edge-triggering interrupt. 1 9 . What does Quality factor mean? The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of a

circuit. Higher the Q, the lower are the losses. 20. What are level-triggering interrupt? RST 6.5 & RST 5.5 are level-triggering interrupts. 21. Comparison between full address decoding and partial address decoding? Full Address D ecoding Partial Address decoding 1. All higher address lines are decoded to select the memory or I/O device. 1. Few higher address lines are decoded to select the memory or I/O device. 2. More hardware is required to design 2. Hardware required to design decoding l ogic Microprocessor 8085 - Two Mark Questions Download this Document for Free Print Mobile Collections Report Document Info and Rating microprocessor 8085 two mark questions with answers short answer question with answers Follow sns_apk

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