Digital Logic Design

Nguyen Thanh Kien Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology

About
 Author: Nguyen Thanh Kien  Office:
Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology

 Mobile: +84 983 588 135  Email: kiennt-fit@mail.hut.edu.vn thanhkien84@yahoo.com ftp://dce.hut.edu.vn/kiennt

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Content
1. Introduction 2. Function Minimization Methods 3. Larger Combinational Systems 4. Sequential Systems 5. Hardware Design Languages

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Acknowledge
 The following materials are used as reference for this slide:
– “Logic Circuits” slide, Dr. Trinh Van Loan. – Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw Hill,2005 – Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

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Reference textbooks
 Introduction to Logic Design, 2nd Ed,, Alan B, Marcovitz, Mc. Graw Hill,2005  Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

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Grading policy  Homework: 20%  Lab work: 20%  Midterm: 30%  Final Exam (multichoice and writing): 30% Page  6 .

2.1.1. Review of Number Systems 1. Introduction 1. Switching Algebra and Logic Circuits Page  7 .

Chapter 1. Introduction Page  8 .

1.5 Binary Coded Decimal (BCD) 1.1.1. Review of Number Systems 1.1.2 Binary Addition 1.1.1.6 Other Codes Page  9 .1 Number Representation 1.4 Binary Subtraction 1.1.3 Signed Numbers 1.1.

1 Number Representation  1.5 Binary Coded Decimal (BCD)  1.1.4 Binary Subtraction  1.1.1.1.3 Signed Numbers  1.6 Other Codes Page  10 .1. Review of Number Systems  1.1.2 Binary Addition  1.1.1.

7 – Hexadecimal: b=16.D.6.1.4.3..C.8..F Page  11 .3.2.5.5..2.1.8.4..1.B.1.(b-1) • 0 ≤ ai ≤ (b-1) – Binary: b=2..E.A.4.7.a−1a− 2 .9 – Octal: b=8.7.1 – Decimal: b=10.6.a1a0 .5. digits:0.2.3.a− m – Base/radix: b (the number of digits) – Digits: 0.9.1. digits: 0.1. digits: 0. digits: 0.6. Number Representation  Numbers are normally written using a positional number system: N (b ) = an an −1an − 2 .

+ a1.b 0 + a−1.b n + an −1.b i n i 11101.b1 + a0 .b n −1 + ..11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2= 29..b −1 + .1.a−1a− 2 . Number Representation N (b ) = an an −1an − 2 .a− m N (10 ) = an .. + a− m ......1.a1a0 .1.b − m N (10 ) = i =− m ∑ a .75(10) Page  12 .

9 Page  13 .a1a0 .1.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2 ai = 0. Number Representation  Decimal: – b=10 – Digits: 0.3.1.a−m – Eg: 539...5.2..1.9 N (10 ) = an an −1an − 2 .1.6.a−1a− 2 .4...8.7.

25 + 0.a−1a− 2 .011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.125 Page  14 = 11.375(10) . Number Representation  Binary: – b=2 – Digits: 0..1 N (10 ) = i =− m ∑ a .1 bit – binary digit N ( 2 ) = an an −1an −2 .1.a−m – Eg: ai = 0.a1a0 .2 i n i 1011...1..1.

1.a1a0 from 0 to 2n-1 – MSB – Most Significant Bit – LSB – Least Significant Bit 0001 = 1 0010 = 2 0011 = 3 0100 = 4 0101 = 5 0110 = 6 0111 = 7 1000 = 8 Page  15 1001 = 9 1010 = 10 1011 = 11 1100 = 12 1101 = 13 1110 = 14 1111 = 15 . Number Representation  Binary (cnt’) – n-bit binary number can represent which range? • an-1.1..1..

F – Digits: 0.4.5..1.A..B..6.7 – Eg: 503...071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3 ai = 0.1.7 N (8) = an an −1.C.8.2.D.a−1a− 2 .E..4.3.F 1010 0011(2)= A3(16) Page  16 503.a− m  Hexadecimal: – b=16 – Eg: N (16 ) = an an −1..071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3 ..a1a0 ..1.a1a0 .2.a− m ai = 0.7.1. Number Representation  Octal: – b=8 – Digits: 0.9.1.6.3.5.a−1a− 2 ..

Convert from base b to base 10 Base b to base 10 conversion N (b ) = an an −1an − 2 ..b 0 + a−1.b −1 + .a− m Eg:0 N (10 ) = an ....125+0.b n −1 + .11(8)= 0*80+1*81+0*82+1*83 + 1*81 +1*8-2 = 0+8+0+512+0.a1a0 . + a1.75 – 1010.b1 + a0 .11(2)= 10...b − m – 1010..015625 Page  17 – A12(16)= 10572 = 2*160 + 1*161 + 10*162 = .a−1a− 2 . + a− m ..b n + an −1.

011(8)=?(10) 110.011(16)=?(10) 6.375 72. Page  18 .110.039..0175 272.011(2)=?(10) 110..

– For the odd part after “.Convert from base 10 to base b  Base 10 to base b conversion – For integer part: • Divide integer part by b until the result is 0 • Write remainders in reverse order to get the converted result.” • Multiply by b until the result is 0 Page  19 .

5 • 0.75(10) = ?(2) Page  20 .625 x 2 = 1.25 x 2 = 0.625(10) = 110.Convert from base 10 to base 2  Eg1: 6.0 6.5 x 2 = 1.” • 0.101(2)  Eg2: 20.25 • 0.625(10) = ?(2) – The integer part 6 0 2 3 1 2 1 1 2 0 – The odd part after “.

75(10) = ?(2) 10100.0 Page  21 .75 * 2 = 1.5 0.5 * 2 = 1.11(2)  20 2  0 10     0 2 5 2 0 1 1 2 0 1 2 2 0. 20.

 20.11(2) = 24.75(10)=?(8) =10100.6(8)  20 8 4  2 2 8 0 0.0 Page  22 .75 * 8 = 6.

C(16) .110(2)=12.110(2)=A.Convert from base 2 to base 2n  Group from right to left n-bit groups and replace the equivalent values in base 2n  Eg:  101011(2) = ?(8)  101011(2) = ?(16) Page  23 1010.6(8) 1010.

 Eg:  37A.B(16)=?(2) = 0011 0111 1010 . 1011(2) Page  24 .Convert from base 2n to base 2  Each digit in base 2n is replaced by n bit in base 2.

use base 2 as an intermediate base: – Eg: base 8 → base 2 → base 16 – 735.37(8)= 000111011101.01111100(2) = 1DD. use base 10 as an intermediate base: – Eg: base 5 → base 10 → base 2 Page  25 .Convert from base i to base j  If both i and j are powers of 2.7C ?(16)  Else.

1. Review of Number Systems  1.1.1.3 Signed Numbers  1.5 Binary Coded Decimal (BCD)  1.1.1 Number Representation  1.4 Binary Subtraction  1.1.1.2 Binary Addition  1.1.6 Other Codes Page  26 .1.

carry A B sum decimal binary 110 11110 2565 6754 9319 10110 11011 110001 Eg: 10101(2) + 11011(2) = 110000 ? (2) Page  27 .2 Binary Addition  Binary long addition similar to decimal long addition.1.1.

2 Binary Addition  Overflow: – Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits) – In 8-bit computer. the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflow Page  28 .1.1.

.b1b0 Page  29 .1.1...a1a0  B = bn-1bn-2..2 Binary Addition  n-bit adder in computer:  A = an-1an-2.

1.1.1.5 Binary Coded Decimal (BCD) 1.1.1. Review of Number Systems 1.3 Signed Numbers 1.2 Binary Addition 1.1.6 Other Codes Page  30 .4 Binary Subtraction 1.1.1.1 Number Representation 1.

1. 1: negative  Eg: represent signed numbers using 4 bit: – +5 = 0101. -5 = 1101.1.3 Signed Numbers  Represent sign and amplitude  Use the most-left-bit to represent sign: – 0: positive. -3 = 1011 – Using 3 right bits to represent amplitude. – Drawbacks: • +0 = 0000. we can represent from -7 to +7. -0 = 1000 => complex when calculating Page  31 => need an other representation .

– -3 is stored as 28-3=11111101 in a 8-bit system – The most negative number can be stored is -2n-1 Page  32 .2’s complement representation  Most left bit is still sign bit  Positive and 0 numbers are expressed in usual binary format. – The largest number can be represented is 2n-1-1 – n=8 => largest signed number: 28-1-1 = 127  Negative number a is stored as the binary equivalent of 2na in a n-bit system.

10 = 28-10 = 1 0000 0000 – 0000 1010 1111 0110 .10 = 1111 0110  +10 + (-10) = ? 0000 1010   Page  33 1111 0110 1 0000 0000 .2’s complement representation  +10 = 0000 1010  .

1=>0) – Add 1  Eg: find representation of -13 in 8-bit signed number system using 2’s complement: • Magnitude: • Complement: • Add 1: • -13 = Page  34 13 = 0000 1101 1111 0010 + 1 1111 0011 .2’s complement representation  Procedure to find binary representation of negative number in 2’s complement: – Find the binary equivalent of the magnitude – Complement each bit (0=>1.

2’s complement representation  Range of representation: – Use n bit to represent 2’s complement numbers – Range: -2n-1 => 2n-1-1 Page  35 .

4 bit representation of unsigned and signed (2’s complement) Binary format 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Page  36 Unsigned 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signed 0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1 1111 .

2’s complement representation  To find the magnitude of a negative number: – Complement each bit – Add 1  Eg:    1001 0110(2) = -106? 0110 1001 + 1 = 106 01101010 Page  37 .

-5 1011 +7 0111 +2 0010 Page  38 -5 1011 -5 +3 -2 1011 0011 1110 +5 0101 0 0000 .  To add any two numbers. we just do binary addition on their representation. no matter what the sign of each is.Addition of signed numbers  The reason that 2’s complement is so popular is the simplicity of addition.

Addition of signed numbers  Overflow – Occur when? – Add two numbers of the opposite sign? – Add two positive numbers? – Add two negative numbers? maybe ⇒Overflow occurs when adding two numbers with the same sign and the result is in different sign 0110 0101 = 101 + 0101 0010 = 82 Page  39 1011 0111 .

6 Other Codes Page  40 .1.2 Binary Addition 1.1.1.1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1. Review of Number Systems 1.3 Signed Numbers 1.1 Number Representation 1.1.

then add.4 Binary Subtraction  Find the 2’s complement of the second operand.1.  a – b = a + (-b)  Eg: 7 – 5 = ? 5 0101 1010 + 1 7 -5 2 0111 +1011 0010 -5 1011 Page  41 .1.

1.1.4 Binary Subtraction 1.1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.6 Other Codes Page  42 .5 Binary Coded Decimal (BCD) 1.

Binary-Coded Decimal .BCD  BCD: – Use four bits (a nibble) to represent each of the decimal digits 0 through 9. – Eg: 375 = 0011 0111 0101(BCD) Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 Page  43 15 .

1.3 Signed Numbers 1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes Page  44 .1.1 Number Representation 1.1.2 Binary Addition 1.4 Binary Subtraction 1.1. Review of Number Systems 1.1.1.1.

ASCII  Use seven bits to represent various characters on the standard keyboard as well as a number of control signal Page  45 .ASCII  American Standard Code for Information Interchange .

Page  46 .

Represent the following signed numbers: a.011(2)=?(10)  6A1. -74 in 8-bit signed 2’s complement. -74 in 16-bit signed 2’s complement.625(10)=?(2)  11011. b. Convert the following unsigned numbers:  98. Page  47 .1E(16)=?(8) 2.Problems 1.

1. Switching Algebra and Logic Circuits Page  48 .1.2. Review of Number Systems 1. Introduction 1.

NOR.5 Implementation of Functions with AND.2.1 Definition of Switching Algebra 1.1.2.2. NAND. OR.4 Representations of Algebraic Functions 1.2.2 Basic Properties of Switching Algebra 1.3 Manipulation of Algebraic Functions 1. XOR Gates Page  49 .2. NOT.2. Switching Algebra and Logic Circuits 1.

OR.2 Basic Properties of Switching Algebra 1. NOT.1.4 Implementation of Functions with AND.2.1 Definition of Switching Algebra 1. XOR Gates Page  50 . NOR. NAND.2.3 Representations of Algebraic Functions 1.2.2.2.3 Manipulation of Algebraic Functions 1.2. Switching Algebra and Logic Circuits 1.

switch: up/down. – Three operators: • OR: • AND: • NOT: a+b a. voltage: low/high..2..1.1 Definition of Switching Algebra  Switching algebra is binary: – All variables and constant take on 0 or 1.b a’ Page  51 . – Quantities which are not naturally binary must be coded into binary format. • Light on/off.

NOR.1. OR. Switching Algebra and Logic Circuits 1.2. XOR Gates Page  52 . NAND.2.3 Manipulation of Algebraic Functions 1.2 Basic Properties of Switching Algebra 1. NOT.2.4 Implementation of Functions with AND.1 Definition of Switching Algebra 1.2.2.2.3 Representations of Algebraic Functions 1.

(b.1=a  P4: • a+1=1 a.a  P2: Associative: • a + (b + c) = (a + b) + c a.0=0 Page  53 .Basic Properties of Switching Algebra  P1: Commutative: • a+b=b+a a.b).c) = (a.b = b.c  P3: • a+0=a a.

c Page  54 a + b.a=a (a)n=a  P6: no coefficient and no exponent  P7: complement • (a’)’ = a  P8: distributive: • a.c = (a+b). a’ = 0 a.b + a.Basic Properties of Switching Algebra  P5: • a + a’ = 1 • a+a=a • n.(a+c) .(b+c) = a.a=a a .

Basic Properties of Switching Algebra Basic Properties of Switching Algebra  P9: adjacency • ab + ab’ = a (a+b)(a+b’)=a  P10: • a + a’b = a +b a(a’+b) = ab  P11: De Morgan • (a + b)’ = a’b’ (ab)’ = a’ + b’  P12: absorption • a + ab = a a(a+b) = a Page  55 .

Basic Properties of Switching Algebra  P13: redundant • ab+b’c+ac = ab+b’c A B C Page  56 .

Prove the following equalities: a. xy+xz’+yz=xy+x’z => prove it incorrect c. xy’+y=x+y b. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1 Page  57 .Problems 1. x’y’z+yz+xz=z d.

OR.2.2.5 Implementation of Functions with AND.2.1 Definition of Switching Algebra 1.4 Representations of Algebraic Functions 1. NOT.3 Manipulation of Algebraic Functions 1. Switching Algebra and Logic Circuits 1. NOR.2.2. NAND. XOR Gates Page  58 .2.1.2 Basic Properties of Switching Algebra 1.

Manipulation of Algebraic Functions  A literal: – Is the appearance of a variable or its complement – Eg: x and x’ are two different literals – Expression ab’+bc’d+a’d+e’ has 8 literals  A product term: – Is one or more literal connected by AND operators – Expression ab’+bc’d+a’d+e’has 4 product terms – Note: A single literal is also a product term Page  59 .

either uncomplemented or complemented.Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A standard product term .d: • the product term a’bc’d is a standard product term • the product term a’bd’ is not Page  60 . – Eg: for a function of four variables a.b.c.minterm: – Is a product term which includes every variable of the function.

Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A sum of product .c: • ab’c + abc’ + abc is a canonical sum • ab’c + abc’ + a is not Page  61 .b.SOP: – Eg: – Is one or more product terms connected by OR operators ab’c+abc’+a’c+a’ »d  A canonical sum – sum of standard product term – Is a sum of products expression where all terms are standard product terms. – Eg: A function of three variables a.

z) = x’y+xy’+xz • F4(x.z) = x’yz’+x’yz+ xy’z’+xy’z+xyz • F2(x.z) = x’y+xy’+xyz • F3(x.F4 are minimum SOP of F1 .y.Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A minimum sum of products: – Is one of those SOP expression for a function that has the fewest number of product terms.y.y. – If there is more than one expression with fewest number of terms.y. then minimum is defined as one or more of those expressions with the fewest number of literals.z) = x’y+xy’+yz Page  62 F3. – Eg: • F1(x.

Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A sum term: – Is one or more literals connected by OR operators – Eg: • a + b’ + c’ • b’  A standard sum term .y.maxterm: – Is a sum term that includes each variable of the problem.z. either uncomplemented or complemented – Eg: For a function of four variables x.t • x+y+z’+t’ is a maxterm • x+y+t’ is not Page  63 .

Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A product of sum – POS: – Eg: – Is one or more sum terms connected by AND • (w+x’+y’)(w+y+z’)(w+x+z) •w  A canonical product – product of standard sum terms: – Is a product of sum term where all sum terms are standard Page  64 .

Manipulation of Algebraic Functions Manipulation of Algebraic Functions – fewest number of terms – the same number of terms => fewest number of literals  A minimum POS is defined the same way as SOP: Page  65 .

Canonical forms  Three-variable minterm and Maxterm Decimal 0 1 2 3 4 5 6 7 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 minterm x’y’z’ x’y’z x'yz’ x'yz xy’z’ xy'z xyz' xyz (m0) (m1) (m2) (m3) (m4) (m5) (m6) (m7) Maxterm x+y+z x+y+z’ x+y’+z x+y’+z’ x’+y+z x'+y+z’ x'+y’+z x'+y’+z’ (M0) (M1) (M2) (M3) (M4) (M5) (M6) (M7) Page  66 .

Canonical forms  Properties of minterm/Maxterm: – mimj=0 if i≠j =mi if i=j – Mi+Mj=1 = Mi if i≠j if i=j – mi=Mi’ and Mi=mi’ for every i Page  67 .

Page  68 . – By multiplying (ANDing) those maxterm for which the function takes a value 0.Canonical forms  An algebraic expression of a Boolean function can be derived from a given truth table in two ways: – By summing (ORing) those minterm for which the function takes a value 1.

4.7) Canonical sum-of-products (SOP) f(x2.x0)=M0M2M3 = Π(0.3) Canonical product-of-sums (POS) Page  69 .6.x0)=m1+m4+m5+m6+m7 =Σ(1.5.2.x1.x1.Canonical forms Decimal x2 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 x1 0 0 1 1 0 0 1 1 x0 0 1 0 1 0 1 0 1 f 0 1 0 0 1 1 1 1 f(x2.

c)= abc’+a’b’ Decimal 0 1 2 3 4 5 6 7 a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 f 1 1 0 0 0 0 1 0 F(a.b.c)=m0+m1+m6 – ∑(0.1.6) Page  70 .F(a.b.

NAND. NOR.1 Definition of Switching Algebra 1. XOR Gates Page  71 .3 Manipulation of Algebraic Functions 1.2 Basic Properties of Switching Algebra 1.2.4 Representations of Algebraic Functions 1. Switching Algebra and Logic Circuits 1.2.2.2. OR. NOT.1.2.2.5 Implementation of Functions with AND.

4 Representations of Algebraic Functions  Truth table  Venn diagram  Karnaugh map Page  72 .2.1.

Truth table  List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables. Page  73 .

Truth table  n independent variables and m dependant functions: 2n rows n+m columns 3 independent variables 2 dependent functions 23 rows Page  74 .

B A B C F(A.B.B)=A.C)=C.Venn diagram  Venn diagram using ‘space’ to present logic  F(A.not(B) Page  75 .

B Page  76 A+B .Venn diagram A A A+B A.B A.

 K-map may be used for any variables number.Karnaugh map  A Karnaugh map is a graphical method for representing the true table of a Boolean function. C BC A AB 0 0 1 1 00 0 1 Page  77 01 0 1 11 3 10 2 00 01 11 10 2 3 4 5 7 6 6 7 4 5 . but often at most six.

BC A 00 0 1 0 01 1 11 3 10 2 4 5 7 6 Page  78 .  2n cells are arranged in logical pattern for minimization purpose.Karnaugh map (K-map)  If variables number is n => 2n cells in K-map.

Two-variable K-map  F(A.B) B A 0 0 1 1 A B 0 0 1 2 0 1 0 1 2 3 1 3 Page  79 .

Two-variable K-map  F(A.B) = AB B A 0 0 1 0 0 1 0 1 Page  80 .

B.Three-variable K-map  F(A.C) C AB BC A 0 0 1 1 00 0 1 0 01 1 11 3 10 2 00 01 11 2 3 6 7 4 5 7 6 10 Page  81 4 5 .

Three-variable K-map  F(x.y.z) = xyz + yz’ + x x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 0 1 0 1 1 1 1 x yz xy z 0 0 1 1 1 1 0 0 1 1 00 0 1 0 1 01 0 1 11 0 1 10 1 00 01 1 11 10 Page  82 .

C.B.Four-variable K-map  F(A.D) CD AB 00 00 01 11 10 01 11 10 Page  83 .

Four-variable K-map
 F(A,B,C,D) = AB + CD’ + BCD

CD AB

00 00 01 11 10
0 0 1 0

01
0 0 1 0

11
0 1 1 0

10
1 1 1 1

Page  84

Five-variable K-map

E

0

1

CD 00 01 11 10 CD 00 01 11 10 AB AB 00 00 01 01 11 11 10 10 5 variables Karnaugh Map consists of two 4 variables Karnaugh Map connected up/down.

Page  85

Six-variable K-map

E

F

0

1 CD 00 01 11 10 AB 00 1 1 01 11 1 1 10 1 1 CD 00 01 11 10 AB 00 1 1 01 11 1 1 10 1 1

CD 00 01 11 10 AB 00 1 1 0 01 1 1 11 1 1 10 CD 00 01 11 10 AB 00 1 1 1 01 1 1 11 1 1 10

Page  86

Karnaugh map with don’t care

CD AB 00 01 11 10

00

01

11 1

10 1

1 −

1 − − − − −

don’t care ~ input conditions that not occur

Page  87

1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.4 Representations of Algebraic Functions 1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

Page  88

Basic logic gates  AND OR NOT A 0 0 1 1 B 0 1 0 1 out 0 0 0 1 A 0 0 1 1 B 0 1 0 1 out 0 1 1 1 A 0 1 out 1 0 Page  89 .

Basic logic gates NAND NOR XOR A 0 0 1 1 Page  90 B 0 1 0 1 out 1 1 1 0 A 0 0 1 1 B 0 1 0 1 out 1 0 0 0 A 0 0 1 1 B 0 1 0 1 out 0 1 1 0 .

OR  Assume all inputs are available in uncomplemented and complemented F2 = x’y+xy’+xz Page  91 F1 = x’yz’+x’yz+xy’z’+xy’z+xyz .Implementation of Functions with AND.

Implementation of Functions with AND. OR. NOT  Complemented inputs can be produced using inverters NOT: X Y F Z Page  92 .

Multilevel circuits  A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output two-level circuit Page  93 three-level circuit .

B B (A’. every expression can be represented using only NAND gates.B’)’ =A+B B Page  94 AND .Implementation of Functions with NAND  Using equivalent change steps. OR A NOT A A.

b.c) = ab + bc’ + b’ = ab + bc + b = ab + bc + b = ab.bc.b Page  95 .Implementation of Functions with NAND  Represent the following expression using only NAND: – F(a.

B 7402N B' 7402N A U3A A) A' 7402N ( A+ ' = U10A U11A Page  96 7402N 7402N . U8A A' A 7402N U9A U7A ( A' + ) ' = B B' A. every expression can be represented using only NOR gates.Implementation of Functions with NOR  Using equivalent change steps.

b.Implementation of Functions with NOR  Represent the following expression using only NOR: – F(a.c) = ab + bc’ + b’ Page  97 .

Chapter 2. Logic Function Minimization Methods Page  98 .

2 The Karnaugh Map Method 2.2.3 Quine-McCluskey Method Page  99 . Function Minimization Methods 2.1 Algebraic Method 2.

2. Function Minimization Methods  What is minimization? – Number of operands is minimal and number of literal in each operand is minimal  Why minimization needed? – Minimize electronic components used to construct the circuit to implement that expression Page  100 .

2 The Karnaugh Map Method 2. Function Minimization Methods 2.1 Algebraic Method 2.3 Quine-McCluskey Method Page  101 .2.

2. Algebraic Method  Use algebraic properties to minimize expressions  Drawback: – Heuristic.1. depending on experience – no formal method/procedure – Manually – Not sure whether the last expression is minimal or not Page  102 .

Algebraic Method  Eg: Minimize these expressions using algebraic method: – F0(x.B.z)=xyz+x’yz+xy’z+xyz’ – F1(a.d)=ab+abc+a’cd+a’c’d+a’bcd’ – F2(A.1.d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d) Page  103 .2.D)= ( A + BC ) + A.b.b.c.c.y.z)=(x+y)(x+y+z’)+y’ – F4(a.C.( B + C )( AD + C ) – F3(x.y.

Function Minimization Methods 2.3 Quine-McCluskey Method Page  104 .2 The Karnaugh Map Method 2.1 Algebraic Method 2.2.

2. Product of Sums 4. Multiple Output Problems Page  105 .2 The Karnaugh Map Method 1.and Six-Variable Maps 6. Don’t Cares 3. Minimum Cost Gate Implementation 5. Five. Minimum Sum of Product Expressions Using the Karnaugh Map 2.

Prime Implicant  An implicant of a function is a product term that can be used in a SOP CD AB 00 00 01 11 10 1 1 01 11 1 1 10 Implicants of F Minterm A’B’C’D’ A’B’CD A’BCD ABC’D’ ABCD’ ABC’D ABCD Groups of 2 A’CD BCD ABC’ ABD ABC ABD’ Groups of 4 AB 1 1 1 Page  106 .Implicant.

Implicant. CD AB CD 00 01 11 1 1 1 1 1 1 1 1 1 BC B D * 10 1 00 01 11 10 1 B D* AD Page  107 AB . Prime Implicant  A prime Implicant is an implicant which can not be contained in any other implicants.

CD AB CD 00 01 11 1 1 1 1 1 1 1 1 1 BC B D minterm 0 is only contained in PI B’D’ minterm 5 is only contained in PI BD => BD & B’D’ are two Essential PI * 10 1 00 01 11 10 1 B D* AD Page  108 AB .Essential Prime Implicant  Essential PI is a PI which contains at least one minterm which is not contained in other PI.

Number of cells is 2n. – Rule 3: Each group will be a part of result.1 Minimum Sum of Product Expressions  Rules to minimize using K-map: – Rule 1: Fill K-map cells with corresponding values – Rule 2: Group adjacent cells whose values are 1. Variables in each group will be excluded: 2n cells => exclude n variables.2.2. Page  109 .

Number of cells is 2n.1 Minimum Sum of Product Expressions  Step 2: Group adjacent cells whose values are 1.2.2. CD AB CD 00 00 01 11 10 01 11 10 AB 00 00 01 1 11 1 10 1 1 01 11 10 1 1 1 1 1 1 1 1 1 1 Page  110 .

D) = A’BC’ + AC 1 1 22 cells => eliminate 2 variables 1 1 Page  111 .C. CD AB 00 00 01 11 10 1 01 11 10 21 cells => eliminate 1 variable 1 F(A.1 Minimum Sum of Product Expressions  Step 3: Each group will be a part of result.2. Variables in each group will be excluded: 2n cells => exclude n variables.B.2.

5.6.14. F(A.14) Page  112 .C.11.2.9.9.2.8.C.11.15) – e.B.5.5.13.14) – b.3.4.5.13.13.D)=R(1.6.3. F(A.B. F(A.1 Minimum Sum of Product Expressions  Example 1: Minimize these functions using K-map: – a.4.7.D) = R(2.15) – c. F(A.3.13) – d.14.B.D) = R(1.B.C.D) = R(0.D)= R(1.B.9.C.2.9. F(A.4.12.C.6.9.12.7.

2.5. F(A.C.9.14) = BC’D + AB’D + BCD’ + A’B’D’ CD AB 00 00 01 11 10 1 01 11 10 1 1 1 1 1 1 1 Page  113 .– a.D) = R(0.B.11.6.13.

12.B.14) = B’D + BD’ CD AB 00 00 01 11 10 1 1 01 1 11 1 10 1 1 1 1 Page  114 .9.4. F(A.C.– b.11.6.3.D) = R(1.

2.2 The Karnaugh Map
1. Minimum Sum of Product Expressions Using the Karnaugh Map 2. Don’t Cares 3. Product of Sums 4. Minimum Cost Gate Implementation 5. Five- and Six-Variable Maps 6. Multiple Output Problems

Page  115

2.2.2 Don’t care
 If the function has don’t care values in cells:
– Cells with don’t care values can be grouped with ‘1’ cells – Do not group only don’t care cells in one group.
CD AB 00 01 11 10 1 − 1 − − − − − 00 01 11 1 10 1

F ( A, B, C , D) = BC + BC
Page  116

Examples:

F(a,b,c,d)=R(1,3,5,7,12,13) don’t care (0,4,10,15)
CD AB

00 00 01 11 10
-

01
1

11
1

10

-

1

1

1

1

-

-

Page  117

2. Function Minimization Methods
2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method

Page  118

2.3 Quine-McCluskey Method
1. Quine-McCluskey Method for One Output 2. Iterated Consensus for One Output 3. Prime Implicant Tables for One Output 4. Quine-McCluskey for Multiple Output Problems 5. Iterated Consensus for Multiple Output Problems 6. Prime Implicant Tables for Multiple Output Problems

Page  119

Quine-McCluskey method has no limitation with number of variables. Quine-Mcluskey method Karnaugh map cannot handle more than 6 variables.2. ABC+ABC+ABC+ABC+ABC AB 00 01 11 10 Page  120 C 0 1 1 1 1 1 1 010 *10 110 11* 111 1*0 1** 100 1*1 101 10* find a pair of numbers of 1 bit difference . and is suitable for computer algorithm.3.

Quine-Mcluskey Procedure  1: Represent minterms in binary numbers  2: Group each minterm by the number of ‘1’ appearance  3: Make set of 1 bit different numbers between neighboring group • write the difference within parenthesis • mark * to the number which is not included in a set  4: Make set of 1 bit different sets with the same number in a parenthesis • append the difference to parenthesis • mark + to the set which is not included in a set  5: Iterate these step until all the generated set is marked *  6: Select prime implicants Page   7:121 Convert to logic variable .

14.8.E.12.B.7.C.41.15.2.10) f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 Page  122 .F)=Σ(0. Represent minterms in binary numbers f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF f(A.S1.6.D.

S2. Grouping f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 group each term by the appearance of 1 group 0 group 1 group 2 group 3 group 4 no times 000000 once 000010 001000 twice 000110 001100 001010 three times 000111 001110 101001 four times 001111 Page  123 .

6(4) 2.2 (2) 0.15(1) find a pair of 1 bit difference between neighboring group write difference within ( ) group 2 group 3 mark to the number not included in any set group 4 Page  124 .12(4) 6.14(4) 12. Making set (1) group 0 group 1 000000 000010 001000 000110 001010 001100 000111 001110 101001 001111 0 2 8 6 10 12 7 14 41 15 0.10(8) 8.10(2) 8.14(8) 10.S3 & S4.7(1) 6.14(2) 7.8 (8) 2.15(8) 14.

Making set (2) 0.8.8) when all the set is marked finish .15(1.14(2.6.8 (8) 2.10(2) 8.15(1) 0.14.14(2) 7.14(8) 10.S3 & S4.7(1) 6.8) 8.14(4.7.10(2.14(4) 12.10.2 (2) 0.12.12(4) 6.2.10(8) 8.6(4) 2.8) find a pair of 1 bit different sets with the same value in ( ) between neighboring group append difference within ( ) Each pair appears in duplicate 2.4) mark to the set not involved in the next level set 6.15(8) Page  125 14.10.

7.6.8.14(2.4) 6.10.8) 2. then the row is inevitable implicant .14(4.8) x 2 x x 6 x x 7 8 x 10 12 14 15 41 x x x x x x x x x x x write x into the position where minterm is included in the prime implicant inevitable implicant If only one x in a column.8) 8.2.10(2. Selecting Prime Implicants (1) minterms (given at first) Prime implicant (   marked ) Page  126 0 41 0.15(1.14.12.10.S6.

2.10(2.14(2.12.10.7.8) 2.4) 6.6.8) 8.14. Selecting Prime Implicants (2) mini term 0 41 0.15(1.S6.8.8) x 2 x x 6 x x x 7 8 10 12 14 15 41 x x x x x x x x x x x prime implicants Page  127 mark minterms involved in the inevitable implicants inevitable implicants .10.14(4.

2.14(2.4) ABCF 6.8) 8.S7.10(2.14.12.7.8) Page  128 ABDE .8.15(1. Conversion to logic variables 41 101001 000000 000010 001000 001010 001000 001010 001100 001110 000110 000111 001110 001111 ABCDEF ABDF F=ABCDEF +ABDF +ABCF +ABDE 0.10.

e.46.25.53.54.61) Page  129 .f) = ∑(17.49.b. d. c. F(a.Examples:  Minimize the following functions using QuineMcluskey method: – a. f) = ab d ef + abce f + bcd f + ab d e f – b.21.45.52.47. F(a. 44.d. e. b.47.29.55.c.

remove from A  4: Apply Quine-McCluskey method for A and B  5: Be careful not to include B in selecting prime implicants Page  130 .Quine-Mcluskey method with don’t care  1: Represent logic function in sum of mini terms ==>A  2: Represent don’t care in sum of mini terms ==>B  3: If there exist duplication in A and B.

15(4.8) 5.5(4) 2.3.7(4) 3.13.15(4) 13.3(2) 1.2) 1.3(1.7(2) 5.Quine-Mcluskey method with don’t care f=ABCD+BCD+ACD+ABCD+ABCD don’t care AD mini term decimal ABCD 0 0000 1 0001 2 0010 3 0011 5 0101 7 0111 11 1011 13 1101 15 1111 Page  131 first comparison second comparison 0.5.15(2.2.13(8) 7.1(1) 0.2(2) 0.7.1.15(2) .8) 5.3(1) 1.7(2.11(8) 3.4) 3.15(8) 11.7.11.

2.8) 5.4) 3.7(2.2) 1.5.3(1.7.7.11.15(4.15(2.3.1.13.Quine-Mcluskey method with don’t care 0.8) 0 x 2 x 11 13 15 ABCD x x x x 00** 0**1 **11 *1*1 f=AB+CD+BD Page  132 .

Larger Combinational Systems Page  133 .Chapter 3.

Introduction  Logic circuits are divided into two classes: – Combinational logic circuits • Output signals only depend on current input signals • Memoryless circuits – Sequential logic circuits • Output signals not only depend on current input signals. but also depend on those input signals in the past • Memory circuits Page  134 .

7 Three-State Gates  3.6 Demultiplexers  3.4 Encoders  3.5 Multiplexers  3.2 Adders and Other Arithmetic Circuits  3.1 Delay in Combinational Logic Circuits  3.3. PLAs and PALs  3.9 Larger Examples Page  135 . Larger Combinational Systems  3.8 Gate Arrays-ROMs.3 Decoders  3.

the output of that gate doesn’t change immediately.1 Delay in Combinational Logic Circuits  Delay through logic gates – When the input to a gate changes. – The output is stable after the longest delay path A B C X F Page  136 . but there is a small delay Δ.3.

Larger Combinational Systems  3.4 Encoders  3.8 Gate Arrays-ROMs. PLAs and PALs  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.9 Larger Examples Page  137 .5 Multiplexers  3.7 Three-State Gates  3.1 Delay in Combinational Logic Circuits  3.6 Demultiplexers  3.3.

Half Adder a 0 a b HA b 0 1 0 1 Σ 0 1 1 0 r 0 0 0 1 Σ=a ⊕ b r = ab Σ (Result) r (Carry-out) 0 1 1 a =1 Half Adder Σ b & r Page  138 .

Addition of two n-bit numbers r3 A= +B = r4 a3 b3 Σ3 r3 r2 a2 b2 Σ2 r2 r1 a1 b1 Σ1 r0 a0 b0 r1 Σ 0 Summation Page  139 Σ4 Σ3 Σ2 Σ1 Σ0 .

Full Adder Σi 00 0 01 11 10 ai ri bi FA Σi ri aibi ri+1 1 1 ai 0 0 0 0 1 1 1 1 Page  140 bi 0 0 1 1 0 0 1 1 ri 0 1 0 1 0 1 0 1 Σi 0 1 1 0 1 0 0 1 ri+1 1 1 1 0 0 0 1 0 1 1 1 1 1 aibi ri ri+1 00 0 01 11 10 1 1 1 Σi = ai ⊕ bi ⊕ ri ri+1 = ai bi + ri (ai ⊕ bi) .

– S2: Construct truth table – S3: For each output. – S4: Draw the circuit.Combinational logic circuit design procedure  Problems: design a combinational logic circuit to do smth. Page  141 . using K-map to minimize from truth table. outputs and relations.  Design procedure: – S1: Find inputs.

the number of bit of M is selected properly. N is 3-bit binary number.Example 1  Problem: Design a combinational logic circuit to implement this operation: M=N+3.  Solution: – S1: three inputs: n2n1n0 four outputs: m3m2m1m0 Page  142 .

Example 1  S1: three inputs: n2n1n0 four outputs: m3m2m1m0  S2: truth table n2 n1 n0 m0 1 0 1 0 1 0 1 0 1 0 1 1 1 n2 0 0 0 0 0 m3 m2 m1 m0 n2 0 0 0 0 1 1 1 1 Page  143 n1 0 0 1 1 0 0 1 1 n0 0 1 0 1 0 1 0 1 m3 0 0 0 0 0 1 1 1 m2 0 1 1 1 1 0 0 0 m1 1 0 0 1 1 0 0 1  S3: m3 = n2n0 + n2n1 n1n0 00 01 11 10 .

b0 Ex2 Page  144 .b2.a0 • Outputs: b3.Example 2  Problem: design a combinational logic circuit to calculate square of a 2-bit binary number.  Solution: – Step1: find inputs.b1. outputs • Inputs: a1.

a0 • b2 = a1.Example 2 – Step 2: truth table a1 0 0 1 1 a0 0 1 0 1 b3 0 0 0 1 b2 0 0 1 0 b1 0 0 0 0 b0 0 1 0 1 – Step3: using K-map to minimize outputs • b3 = a1.a0’ b1 = 0 b0 = a0 Page  145 .

5 V X3 2.a0 • b2 = a1.5 V X2 2.Example 2 – Step 4: Draw circuit • b3 = a1.a0’ b1 = 0 b0 = a0 X1 2.5 V b3 U1A J1 a1 V1Key = A 5V R1 100 7408N U1B b2 b1 b0 a0 7408N U2A J2 V2Key = B 12 V 7404N R2 100 Page  146 .5 V X4 2.

Full Adder ri ai bi & & ≥1 =1 =1 Σi ri+1 Page  147 .

Full Adder ri ai bi HA & =1 =1 Σi HA & ≥1 ri+1 Page  148 .

.a1a0 ..b1b0 an-1 bn-1 an-2 bn-2 rn-1 rn-2 FA a1 b1 r1 a0 b0 r 0= 0 FA FA rn FA r2 Σn Page  149 Σ n-1 Σ n-2 Σ1 Σ0 Delay = n x Δ? ..n-bit Adder  Serial n-bit adder A = an-1an-2.. B = bn-1bn-2.

n-bit Adder  Parallel n-bit adder: ri+1 = aibi + ri(ai ⊕ bi) Pi = ai ⊕ bi and Gi = aibi → ri+1 = Gi + ri Pi r1 = G0 + r0P0 G1 ≥ 1 r2 G0 ≥ 1 r1 P0 r0 & G0 P1 & τ1 τ2 Page  150 P0 r0 & τ2 r2 = G1 + G0P1 + r0P0P1 τ1 .

Parallel 4-bit addition a3 b3 a2 b2 a 1 b1 a0 b0 r0 Calculate Pi and Gi P3 G3 P2 G2 P1 G1 P0 G0 Carry calculation r4 r3 a 3 b3 a2 r2 b2 a1 r1 b1 r0 a0 b0 Sum calculation r4 = Σ 4 Page  151 Σ3 Σ2 Σ1 Σ0 .

Subtractor  To subtract a-b.  Second choice: Half Subtractor => Full Subtractor => n-bit Subtractor Page  152 . simply add a to 2’s complement of b.

Subtractor  Subtractor by using 2’s complement B3 A3 A2 B2 A1 B1 A0 B0 A B A C B A C B A C B C4 C+ FA S C3 C+ FA S C2 C+ FA S C1 C+ FA S C 1 S3 Page  153 S2 S1 S0 .

Adder and Subtractor A3 B3 A2 B2 A1 B1 A0 B0 MPX MPX MPX MPX sel A B A C B A C B A C B C4 C+ FA S C3 C+ FA S C2 C+ FA S C1 C+ FA S C S3 Page  154 S2 S1 S0 .

3.9 Larger Examples Page  155 .5 Multiplexers  3.2 Adders and Other Arithmetic Circuits  3.7 Three-State Gates  3. PLAs and PALs  3.4 Encoders  3.3 Decoders  3.1 Delay in Combinational Logic Circuits  3. Larger Combinational Systems  3.8 Gate Arrays-ROMs.6 Demultiplexers  3.

Page  156 . – m = 2n => complete decoder  Fundamental property: only one output is 1 for any given input combination. where m≤2n.Decoder  An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines.

nxm decoder .Decoder  Complete decoders: m=2n x1 x2 D0 xn E .Y1…Y7 Page  157 . . . + 8 bit outputs Y0. . .x2. . D1 x1 x2 x3 D0 3x8 decoder . .x3. D1 D7 Dm-1 Eg: + 3 bit inputs x1.

. D1 D7 En if (En=0) Disable or D0..D7=0 else if (En=1) Function as a 3x8 decoder Page  158 .Design 3x8 decoder x1 x2 x3 D0 3x8 decoder . . .

. . . . . . . . . . . . . . . Y9 0 0 0 0 0 0 0 0 0 1 Page  159 .BCD-to-decimal decoder N 0 A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 Y0 1 0 0 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 0 0 A B C D BCD to decimal Decoder : : Y0 Y1 Yi Y9 1 2 3 4 5 6 7 8 9 . . . . . .

BCD-to-decimal decoder Y0  A B C D CD AB Y1  A B C D Y2  BCD 00 01 11 10 1 00 01 11 10 Y3  BCD Y4  BC D Y5  BC D Y6  BC D Y7  BCD Y8  AD Y9  AD − − − − − − Page  160 .

.Decoder  4x16 decoder using two 3x8 decoders x2 x3 x4 D0 3x8 decoder . . D9 D15 Page  161 . . D1 D7 x1 3x8 decoder D8 . .

Decoder implementation of arbitrary functions

x1 x2 x3 x4 4x16 decoder

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

F1

F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)
Page  162

BCD-to-7segment decoder

a f e d g b c
N 0 1 2 3 4 5 A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 1 1 1 1 b 1 1 1 1 1 0 0 1 1 1 c 1 1 0 1 1 1 1 1 1 1 d 1 0 1 1 0 1 1 0 1 1 e 1 0 1 0 0 0 1 0 1 0 f 1 0 0 0 1 1 1 0 1 1 g 0 0 1 1 1 1 1 0 1 1

Each segment is a Light Emitting Diode (LED)

A

K

6 7 8 9

Page  163

BCD-to-7segment decoder

CD AB

00

01

11

10

00 01 11 10

1 0

0 1

1 1

1 1

B D

&


1


1

− −

− −
A C

&

≥1

a  A  C BD  B D

Page  164

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  165

Encoder
 An encoder is a circuit that performs the function of a decoder in reverse.  An mxn encoder has m inputs, n outputs where m≤2n. The outputs generate the binary codes corresponding to m inputs.  For example: encoder for PC’s keyboard
Key <=> Character <=> Key code 102 keys, 8 bit ASCII

Page  166

Keyboard encoder ‘1’ P1 P2 Pi 1 2 i Encoder A B C D 9 N=i P9  9 keys  4-bit key code. Page  167 .

Keyboard encoder N 1 2 3 4 5 6 7 8 9 Page  168 ABCD 0001 0010 0011 0100 0101 0110 0111 1000 1001 A = 1 if (N=8) or (N=9) B = 1 if (N=4) or (N=5) or (N=6) or (N=7) C = 1 if (N=2) or (N=3) or (N=6) or (N=7) D = 1 if (N=1) or (N=3) or (N=5) or (N=7) or (N=9) .

Keyboard encoder N=1 ≥ 1 D N=2 N=3 N=4 N=5 N=6 N=7 N=8 N=9 ≥ 1 C ≥ 1 B ≥ 1 A Page  169 .

3.9 Larger Examples Page  170 .3 Decoders  3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3. Larger Combinational Systems  3.7 Three-State Gates  3.8 Gate Arrays-ROMs. PLAs and PALs  3.6 Demultiplexors  3.5 Multiplexors  3.4 Encoders  3.

 Function: select one of input for output MUX 2-1 X0 MUX 4-1 Y X1 X2 X3 C0 C1 Y X0 X1 C0 control inputs C0 0 Page  171 C1 0 0 1 1 C0 0 1 0 1 Y X0 X1 X2 X3 Y X0 X1 1 .Multiplexor  Multiplexor has one output and more than one input.

2-to-1 Multiplexor MUX 2-1 X0 X1 C0 Y C0 C0 0 1 Y X0 X1 0 0 0 0 10 1 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 Y 0 1 0 1 0 0 1 1 X1X0 C0 00 01 1 11 1 1 0 1 Y  X0C 0  X1C 0 Page  172 .

2-to-1 Multiplexor Page  173 .

4-to-1 Multiplexor Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3 Page  174 .

Application of multiplexor  Select source Source 1 A = a3 a2 a1 a0 B = b3 b2 b1 b0 Source 2 C0 Receiver Y3 Y2 Y1 Y0 Page  175 .

Application of multiplexor  Convert parallel-serial A a0 a1 a2 a3 C0 C1 C0 1 Y 0 C1 1 0 Y a0 a1 a2 a3 t t t Page  176 .

0) f(1.1 Y  C1C 0X 0  C1C 0X1  C1C 0X 2  C1C 0X 3 f(0.0) Inputs to select function f(0.B)  A Bf(0.1) x2 x3 A Page  177 x0 x1 Y = f(A.0) .Application of multiplexor  Implementation of arbitrary functions: f(A.1) f(1.B) C1 C0 Variables B .1  A Bf(1  A Bf(1 ) ) .0)  A Bf(0.

Example 0 Inputs to select function 1 1 0 x0 x1 x2 x3 A Y = f(A.B) C1 C0 Variables B  F(A.B) = A’B + AB’ Page  178 .

3 Decoders  3.3.9 Larger Examples Page  179 .5 Multiplexers  3.8 Gate Arrays-ROMs.1 Delay in Combinational Logic Circuits  3.4 Encoders and Priority Encoders  3. PLAs and PALs  3. Larger Combinational Systems  3.6 Demultiplexers  3.7 Three-State Gates  3.2 Adders and Other Arithmetic Circuits  3.

Demultiplexor  Demultiplexor has one input and more than one output  Function: select one of outputs for input DeMUX 1-2 S0 E C0 S1 S 0 = C0 E S1 = C0 E Page  180 .

Demultiplexor 1-4 S0 E S1 S2 S3 C1 C0 Page  181 .

9 Larger Examples Page  182 .4 Encoders and Priority Encoders  3.8 Gate Arrays-ROMs.6 Demultiplexers  3.1 Delay in Combinational Logic Circuits  3.3 Decoders  3.7 Three-State Gates  3.2 Adders and Other Arithmetic Circuits  3.3. Larger Combinational Systems  3. PLAs and PALs  3.5 Multiplexers  3.

7 Three-State Gates (Tristate)  Three state gates exhibit three states instead of two states.3. We can have AND or NAND three-state gates but the most common is threestate buffer gate Page  183 . The three states are: – High : 1 – Low : 0 – High impedance : z • In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant.

3. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide) Page  184 .  Note that buffer produces transfer function and can be used for power amplification.7 Three-State Gates (Tristate)  We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate.

Three-State buffer Three-state buffer C A Y ---------------------0 0 z 0 1 z 7 0 0 1 1 1 Page  185 .

Application of three-state buffer  Three-state buffers can be used to implement multiplexer Page  186 .

PLAs and PALs  3.1 Delay in Combinational Logic Circuits  3.3.9 Larger Examples Page  187 .4 Encoders and Priority Encoders  3.3 Decoders  3.2 Adders and Other Arithmetic Circuits  3.7 Three-State Gates  3.ROMs. Larger Combinational Systems  3.5 Multiplexers  3.6 Demultiplexers  3.8 Gate Arrays .

Programmable Array Logic  ROM Page  188 .Programmable Logic Arrays  PAL .ROM.3.8 Gate Arrays . PLA and PAL  PLA .

PLA .Programmable logic arrays  Pre-fabricated building block of many AND/OR gates – actually NOR or NAND – "personalized" by making or breaking connections among the gates – programmable array block diagram for sum of products form A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z1 0 0 1 0 0 1 1 1 Z2 1 0 1 0 1 0 1 0 • • • inputs m0 m1 m2 m3 m4 m5 m6 m7 AND array product terms OR array outputs • • • Page  189 .

all AND and OR gates are NANDs Page  190 .Before programming  All possible connections are available before "programming" – in reality.

After programming  Unwanted connections are "blown" – fuse (normally connected. make wanted connections) A B C AB B'C AC' B'C' A Page  191 F0 F1 F2 F3 . break unwanted ones) – anti-fuse (normally disconnected.

PLA example  Multiple functions of A. B. C – F1 = A B C – F2 = A + B + C – F3 = A' B' C' – F4 = A' + B' + C' – F5 = A xor B xor C – F6 = A xnor B xnor C A 0 0 0 0 1 1 Page  192 1 B C F1F2F3F4F5 000 0 1 1 0 0 010 1 0 1 1 1 100 1 0 1 1 1 110 1 0 1 0 0 000 1 0 1 1 1 010 1 0 1 0 0 100 1 0 1 0 0 F6 A B C bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC full decoder as for memory address F1 F2 F3 F4 F5 F6 .

PALs and PLAs  Programmable logic array (PLA) – what we've seen so far – unconstrained fully-general AND and OR arrays  Programmable array logic (PAL) – constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms Page  193 .

ROM – Read Only Memories  Two dimensional array of 1s and 0s – entry (row) is called a "word" – width of row = word-size – index is called an "address" – address is input – selected word is output Example: 10 address x 8 data ROM 210 words x 8 ROM 1024 words x 8 ROM 1k x 8 ROM internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) n 2 -1 i decoder j 0 word[i] = 0011 word[j] = 1010 1 1 1 1 word lines (only one is active – decoder is just right for this) Page  194 .

ROM – Read Only Memories  Combinational logic implementation (two-level canonical form) using a ROM F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 Page  195 B C F0 F1 F2 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 1 truth table 1 0 1 0 F3 0 0 0 1 1 0 1 0 ROM 8 words x 4 bits/word A B C F0 F1 F2 address outputs block diagram F3 .

ROM structure  Similar to a PLA structure but with a fully decoded AND array – completely flexible OR array (unlike PAL) n address lines • • • inputs decoder 2n word lines memory array (2n words by m bits) outputs • • • m data lines Page  196 .

7 Three-State Gates  3.3.9 Larger Examples Page  197 .8 Gate Arrays-ROMs. Larger Combinational Systems  3.4 Encoders and Priority Encoders  3. PLAs and PALs  3.3 Decoders  3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.6 Demultiplexers  3.5 Multiplexers  3.

9 Larger Examples  1.3. Comparator Page  198 . Seven-segment displays  2.

Comparator  1-bit full comparator: Gi Li Ei ai bi 1bit Full Comparator ai > bi ai < bi ai = bi Gi=1 Li=1 Ei=1 Gi = ai .bi Ei = ai ⊕ bi Page  199 .bi Li = ai .

Comparator  N-bit parallel comparator: Page  200 .

Page  201 . Represent the following function in the canonical form SOP: F(A.D.7.4.8.6.11.10.Midterm examination (90’)  1. Design 4x16 decoder using only 2x4 decoders.B.9.E)= ∑(1. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A.B. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).C.C)=(A+B’)C  2.  4.15)  3.

B.C) = AB + B’C  4.C)=C  2. Using 3x8 decoder to implement the following function: F(A.D. Page  202 .7.15)  3.B. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).13.4.12.E)= ∑(1.Midterm examination 2 (90’)  1.8. Represent the following function in the canonical form SOP and POS: F(A.B.6. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A.11.C.

Chapter 4. Sequential Systems Page  203 .

2 State Tables and Diagrams  4.4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4. Sequential Systems  4.1 Definitions  4.6 Solving Larger Sequential Problems Page  204 .

 In a circuit with memory.4. the circuit must have some feedback connections from its outputs to its inputs.1 Definitions  Combinatorial circuit is memoryless.  To achieve this. . an output value at tn+1 must be a function not only of the inputs at tn+1 but also of the outputs at tn . Page  205 A circuit with memory is a combinatorial circuit incorporating some feedback connections.

 But then. which in turn depends on tn-2… The circuit maps input sequences to output sequences Page  206 . signals are fed back from outputs to inputs using memory devices.  A memory device stores an output value at time tn so that it can be input to the circuit at tn+1.Feedback and memory devices  To implement feedback. output at tn depends on input at tn-1.

Combinatorial circuit . . . x1 z1 Circuit inputs x2 xn . .Sequential circuit model  Circuits with memory are called sequential circuits. . z2 Circuit outputs yk Memory device Yk Present state y1 Page  207 . Next state Y1 Memory device . . .

y = Fy(X.sn • Y: finite outputs.S) • Fy : output function..... s = Fs(X..l outputs: y1. n states: s1.S)  Moore: ~Mealy • Difference: Fy = Fy(S) Page  208 .y2. m inputs: x1.x2..s2...xm • S : finite states..Sequential circuit model  Mealy model: • X : finite inputs.yl • Fs: state function.

Asynchronous/Synchronous sequential circuits  The timing of the signal in the circuit determine two types of sequential circuits: – Synchronous – Asynchronous. Page  209 .

 To achieve that. the circuit uses a timing device. the state can change only at discrete instants of time. called a clock generator. The operation of the circuit is synchronized with the clock pulse input. Page  210 . that produce trains of periodic or aperiodic clock pulses.  The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence.Synchronous sequential circuits  In a synchronous sequential circuit.

Asynchronous sequential circuits  The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time. Page  211 .  There is no timing device in asynchronous sequential circuit (unclocked memory).

5 Design of Sequential Systems  4.4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.1 Definitions  4.6 Solving Larger Sequential Problems Page  212 . Sequential Systems  4.2 State Tables and Diagrams  4.

– Mealy state diagram 0/0 0/0 a 0/0 b 1/0 c 0/0 d 1/0 1/1 Page  213 .State diagram  Depict graphically the operation of a sequential circuit.

1 /0 0 /0 0 /0 0 /0 1 /0 0 /0 A B 1 /0 C D 1 /1 Page  214 .Example of state diagram  Example: a sequential circuit is used to detect the string “0101” from one input.

State diagram  Depict graphically the operation of a sequential circuit. – Moore state diagram 1 0 f/1 0 1 e/1 a/0 1 0 b/0 1 c/0 0 1 Page  215 0 d/0 1 0 .

– Mealy state table – Moore state table Page  216 .State table  State table presents in a tabular form the same information contained in the state diagram.

Mealy state table 0/0 0/0 PS: Present State NS: Next State a 0/0 b 1/0 c 0/0 d 1/0 1/1 PS x=0 a b c d b b d b NS x=1 a c a c Output (z) x=0 0 0 0 0 x=1 0 0 0 1 a b c d PS NS/Output (z) x=0 b/0 b/0 d/0 b/0 x=1 a/0 c/0 a/0 c/1 k memory devices => 2k rows n circuit inputs => NS portion contains 2n columns Page  217 Output portion also contains 2n columns .

Page  218 . The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row.Moore state table 1 PS x=0 a b c d e f b b d d f f NS x=1 a c c e e a Output z 0 0 0 0 1 1 1 0 f/1 0 e/1 a/0 1 0 b/0 1 c/0 0 1 0 d/0 1 0 The output portion always contains a single column.

Incompletely specified Mealy state table  Two inputs: x1.x2  A single output: z PS 00 a b c d e f Page  219 NS/Output (z) 01 c/1 -/f/1 -/f/0 -/11 b/-/-/e/d/1 c/1 10 e/1 -/-/b/1 a/0 b/0 -/e/0 f/0 a/-/c/0 .

1 Definitions  4. Sequential Systems  4.4.6 Solving Larger Sequential Problems Page  220 .5 Design of Sequential Systems  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.

.3.4. Latches and Flip-Flops  Simplest memory devices: Delay element Yi ΔT yi Yi yi yi(t+ΔT) = Yi(t) ΔT In practice. we don’t have to actually insert delay elements because propagation time delays between the inputs and the outputs of the combinatorial part of the circuit provide Page  221 sufficient delay across the feedback loops.

– Two types: • Latch • Flip-flop Page  222 . Latches and Flip-Flops  Bistable devices: – Two stable states: • Q=0 : the device is reset (reset state) • Q=1: the device is set (set state) – A bistable device remains in one of two states indefinitely until directed by an input signal to change state.3.4.

– The state change only in response to a transition of a clock pulse at clock input. – Used to implement memory part of synchronous circuits Page  223 . – Used to implement the memory part of asynchronous circuits. called clock.4.  Flip-flop: no transparency property – Has a control (triggering) input.3. Latches and Flip-Flops  Latch: transparency property: – Change state when the input values change – The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch.

R (reset)  Two complementary outputs: Q.SR Latch  Two inputs: S (set). Q’ S Q S R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 - Current state Next state R Q’ 0 S Q 0 0 0 1 R Q' 1 1 Page  224 Q = (R+Q’)’ Q’= (S+Q)’ 1 Indeterminate .

SR Latch S Q R Q’ S 0 0 1 1 R 0 1 0 1 Q+ Q 0 1 Indeterminate S Q R Q' Equivalent characteristic table SR=’00’ => Output no change A logic ‘1’ at inputs can change outputs’ states => active-HIGH latch Page  225 .

SR Latch

S

Q

S

Q

R

Q’

R

Q’

S

Q

Q S

R

Q'

R Q'

active-HIGH SR Latch

active-LOW SR Latch

Page  226

SR Latch
 Timing chart (NOR implementation)

S

Q

S R

R

Q'

Q Q
set reset set reset

Page  227

SR Latch
 Timing chart (NAND implementation)

Q S

S R

R Q'

Q Q
set reset set reset

Page  228

SR Latch

R

Q

Q 0

Q+ 0 1 0 1

S 0 1 0 -

R 0 1 0

S

0 1 1

Circuit showing feedback

Excitation table

Q+ = R’Q + R’S SR=0 => Q+ = R’Q + R’S + RS = R’Q + S
for active-HIGH SR Latch
Page  229

D Latch

D

Q

D

S

Q

Q’

R

Q’

Graphic symbol

Implementation using SR Latch
Q Q* 0 1 0 1 D 0 1 0 1

D 0 1

Q* 0 1

0 0 1 1

Equivalent characteristic table
Page  230

Q* = D

Excitation table

E R Q' Page  231 .Gated Latches S E R Q E: Enable input control The latch will not change state as long as E=0 E=1 SR=10 => Set E=1 SR=01 => Reset Q’ S Q ⇒The operation of latch is synchronized with the E input => E: synchronous input A latch with synchronous input is called gated latch.

FF has clock input and changes state synchronously with clock.Flip-flops  Latches implement memory part in asynchronous sequential circuits  Flip-flops do the same for synchronous circuits.  Four common types of flip-flops: – SR – D – JK – T Page  232 .

indicates that the device responds only to an input clock transition from LOW (0) to HIGH (1) => Positive edge-triggered  Appending a small circle to the CLK input indicates that the flip-flop responds only to an input clock transition from HIGH (1) to LOW (0) => Negative edge-triggered Page  233 .SR flip-flop S CLK R Q S CLK Q S CLK Q Q R Q R Q Positive edge-triggered Negative edge-triggered Pulse-triggered (Master-Slave)  The triangle called dynamic indicator.

Q’ Pulse-triggered (Master-Slave) Difference between Latch and Flip-flop? Page  234 • The flip-flop can not change state except on the triggering edge of clock pulse => synchronous • Present and next states in a latch are separated In time by gate delays. but the flip-flop does change state (the output is postponed) until the trailing edge of the clock pulse.SR flip-flop S CLK R Q  The information is entered on the leading edge of the clock pulse. they are separated by clock periods in a flip-flop. .

SR flip-flop Current state S 0 0 0 0 1 1 1 1 R Q 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 - Next state Q Q(t+1) S 0 0 1 1 R 0 1 0 1 Q(t+1) Q(t) 0 1 Indeterminate 0 0 1 1 0 1 0 1 S 0 1 0 R 0 1 0 Reduced characteristic table Indeterminate Excitation table Characteristic table (S=1 & R=1) is inhibited Page 235 Q(t+1) = R’Q(t) + S .

Implementation of SR-FF S CL R Implementation of SR-FF by SR-Latch S CL R Page  236 Q Q S   Q SR-latch R   Q Q Q .

SR flip-flop  Timing chart S S CLK R Q Q R CL Q Q Page  237 .

D flip-flop D CLK Q D S CLK R Q CLK Q’ Q Positive edge-triggered D flip-flop Implementation using SR flip-flop  D flip-flop is useful for storing a single bit Page  238 .

D flip-flop Current state D 0 0 1 1 Q 0 1 0 1 Q(t+1) 0 0 1 1 Next state Q Q(t+1) 0 D 0 1 Q(t+1) 0 1 0 1 1 0 1 0 1 D 0 1 0 1 Characteristic table Reduced characteristic table Excitation table Q(t+1) = D Page  239 .

JK flip-flop J CLK K Q S CLK R Q Q’ Q Positive edge-triggered JK flip-flop Implementation using SR flip-flop  JK = 00 => Q* = Q  JK = 01 => Q* = 0  JK = 10 => Q* = 1  JK = 11 => Q* = not(Q) Page  240 REMEMBER RESET SET INVERT .

JK flip-flop Current state J 0 0 0 0 1 1 1 1 K Q 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 1 0 Next state Q Q(t+1) J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 [Q(t)]’ 0 0 1 1 0 1 0 1 J K 0 1 - 1 0 Reduced characteristic table Excitation table Characteristic table Page  241 Q(t+1) = K’Q + JQ’ .

Page  242 .Master-Slave flip-flop  A pulse-triggered flip-flop is a bistable device – states depend on the values of synchronous inputs at the leading edge of the clock pulse – those states does not change until the trailling edge of the clock pulse.

Master-Slave flip-flop S C R Master S E R Q’ Q Slave S E R Q’ Q Q Q’ Master latch works when C=1 Slave latch works when C=0  A pulse-triggered flip-flop consists of two latches. where one acts as a master and the other acts as a slave => Master-slave flip-flop Page  243 .

Edge-Triggered flip-flop  A edge-triggered flip-flop is a bistable device whose state depends on the synchronous inputs either at the positive edge or at the negative edge of a clock pulse. Page  244 .

Edge-Triggered flip-flop Y1 Q CLK Q Y2 D Positive edge-triggered D flip-flop Page  245 .

Edge-Triggered flip-flop J Q CLK Q K Positive edge-triggered JK flip-flop Page  246 .

Flip-Flop conversions Each FF can mutually converted How to implement y-FF by using x-FF (1) Prepare expanded state table of y-FF (2) Prepare excitation table of x-FF (3) Combine (1) and (2) (4) Calculate logic function for each input of x-ff combinatorial circuit input of y-FF a  Q x-FF CL    b Q Q Q Page  247 CL .

Flip-Flop conversions  Example: Implement T-FF using SR-FF SR-FF S 0 0 0 0 1 1 1 1 Page  248 T-FF Q+ 0 1 0 0 1 1 T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Expanded state table shows the state transition by the input .

Flip-Flop conversions  Example: Implement T-FF using SR-FF expanded state table excitation table SR-FF S 0 0 0 0 1 1 1 1 Page  249 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 - state       input Q    Q+    S    R 0 0 0 0 1 1 0 1 0 0 1 1 1 0 Excitation table shows the input value corresponding to the state transition .

Flip-Flop conversions  Example: Implement T-FF using SR-FF T-FF T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 excitation table state     input Q    Q+    T 0 0 0 0 1 1 1 0 1 1 1 0 Page  250 .

Flip-Flop conversions  Example: Implement T-FF using SR-FF expanded state table of T-FF T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 excitation table of SR-FF state       input Q    Q+    S    R 0 0 0 0 1 1 0 1 0 0 1 Page  251 1 1 0 T 0 0 1 1 Q 0 1 0 1 Q+ S R 0   0 1 .0 1 1 0 0 0 1 .

Flip-Flop conversions  Example: Implement T-FF using SR-FF T 0 0 1 1 Q 0 1 0 1 Q+ S R 0   0 1 .0 1 1 0 0 0 1 Q 0 1 0 .0 0 1 1 T Q 0 1 0 0 1 1 0 T Karnaugh Map of R S Q T Q Q Karnaugh Map of S R=TQ S=TQ CL R Q Calculate logic function for FF input Page  252 CL .

1 Page  253 1 1 .1 1 1 1 .0 D 0 0 1 1 Q 0 1 0 1 Q+ J K 0   0 0 .0 .Flip-Flop conversions  Example: Implement D flip-flop using JK FF Q+ D Q 0 0 0 0 0 1 1 1 0 1 1 1 expanded state table of D-FF excitation table of JK-FF state     input Q    Q+    J K 0 0 0 0 1 1 1 0 .

0 Q 0 1 0 0 1 1 D Q 0 1 0 .Flip-Flop conversions  Example: Implement D flip-flop using JK FF D 0 0 1 1 Q 0 1 0 1 Q+ J K 0   0 0 .1 .0 1 D Karnaugh Map of J J Q D Page  254 Karnaugh Map of K Q Q J=D K=D CL CL K Q .1 1 1 1 .

4.2 State Tables and Diagrams  4.4 Analysis of Sequential Systems  4.6 Solving Larger Sequential Problems Page  255 .1 Definitions  4.3 Latches and Flip Flops  4. Sequential Systems  4.5 Design of Sequential Systems  4.

Flip flop excitation equation  Flip Flop excitation equation express each synchronous input of each flip-flop as a function of the present state and the inputs of the circuit. Page  256 .  These Boolean functions are derived directly from the combinational part of the circuit.

and output equations. Establish state table. Establish state diagram.  S3.  S2.Analysis procedure of sequential circuits  S1. Find excitation equations. Page  257 .

this is Moore model – z = q2’ . and not directly of input.Example1: A D flip-flop Moore model circuit x D1 ~ 1PR 1D 1Q q1 D2 ~ 1PR 1D 1Q q2 z 1CLK ~ 1Q 1CLK ~ 1Q ~ 1CLR ~ 1CLR Cl ock  Excitation equations: – D1 = q1q2’ + xq1’ – D2 = xq1  Output equations: Page  258 Since output is only a function of state z=q2’.

Example1: A D flip-flop Moore model circuit q1* = d1 = q1q2’ + xq1’ q2* = d2 = xq1 State table 0 00 1 q1*q2* q1q2 00 01 10 11 Page  259 x=0 00 00 10 00 x=1 10 10 11 01 z 1 0 1 0 1 0 1 01 0 10 1 0 1 11 0 0 1 State diagram .

and not directly of input.Example2: A JK flip-flop Moore model circuit z x ~ 1PR 1J 1CLK 1K ~ 1Q ~ 1CLR 1Q A ~ 1PR 1J 1CLK 1K ~ 1Q ~ 1CLR 1Q B Cl ock  Excitation equations: – JA = x KA = xB’ – JB = KB = x + A’  Output equations: Page  260 Since output is only a function of state z=A+B. this is Moore model – z=A+B .

Example2: A JK flip-flop Moore model circuit A* = A’JA + AKA= A’x+AxB’ B* = B’JB + BKB = B’(x+A’) + B(x+A’)’ State table 0 0 00 0 A*B* AB 00 01 10 11 Page  261 1 x=0 01 00 10 11 x=1 11 10 01 10 z 01 1 11 1 0 0 1 1 1 1 1 10 1 1 0 State diagram .

Example2: A JK flip-flop Moore model circuit Page  262 .

Example3: A D flip-flop Mealy model circuit x z ~ 1PR 1D 1Q q1 ~ 1PR 1D 1Q q2 1CLK ~ 1Q 1CLK ~ 1Q ~ 1CLR ~ 1CLR Cl ock  Excitation equations: – d1 = xq1 + xq2 – d2 = xq1’q2’ Page  263  Output equations: – z = xq1 Since output is a function of both present input and state z=xq1. this is Mealy model .

we return to state 00. Whenever there is a 0 input. 2. . State 11 is never reached. this example really only has 3 states.Example3: A D flip-flop Mealy model circuit 0/0 q1* = d1 = xq1 + xq2 q2* = d2 = xq1’q2’ 1/0 0/0 00 11 q* q 00 01 10 11 Page  264 z 01 0/0 0/0 1/1 x=0 x=1 x=0 x=1 00 01 0 0 00 10 0 0 00 10 0 1 00 10 0 1 10 1/0 1/1 Notice that: 2.

Example3: A D flip-flop Mealy model circuit  Mealy timing trace: x q1 q2 0 ? ? 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 z 0 0 0 0 0 0 1 1 0 0 0 Page  265 .

Example3: A D flip-flop Mealy model circuit Page  266 .

4 Analysis of Sequential Systems  4.6 Solving Larger Sequential Problems Page  267 .3 Latches and Flip Flops  4.2 State Tables and Diagrams  4.1 Definitions  4. Sequential Systems  4.5 Design of Sequential Systems  4.4.

Page  268 . that is. code the inputs and outputs in binary. determine what needs to be stored in memory. From a word description. what are the possible states.  S3.Design Procedure for Sequential Systems  S1. Produce the logic equation and draw a block diagram.  S2. but has fewer states.  S7. that is.  S4. Derive a state table or state diagram to describe the behavior of the system. Choose a state assignment. code the states in binary. If necessary.  S5.  S6. Choose a flip flop type and derive the flip flop input maps or tables. Use state reduction techniques to find a state table that produces the same input/output behavior.

otherwhile y=0. Use Mealy model x=0101011.Example1: Design sync sequential circuit using JK  Design a synchronous sequential circuit using JK flip-flop. Output is 1 when receiving a string 0101 in input. The circuit has one input x. wait for 0 D: had 010. System y=0001010. A: wait for first 0 B: had 0. one output y... wait for 1 1/0 0/0 0/0 0/0 0/0 A B 1/0 C D 1/1 1/0 Page  269 . wait for 1 C: had 01.

Example1: Design sync sequential circuit using JK Use two state variables q1q2 to encode states in binary q1 q2 0 A B 1 C D q1 q2 x S A B C D 0 0 B.0 01.0 D.0 C.1 Q1Q2 State table Page  270 State table after assignment .1 1 x 00 01 10 11 0 01.0 10.0 01.0 B.0 A.0 10.0 1 A.0 00.0 Q1Q2 1 00.0 B.0 11.0 C.

1 00.0 q 0 0 1 1 q* 0 1 0 1 J 0 1 - K 1 0 x 0 J 1 K1 J2K2 00 01 11 10 Application table q1 q2 1 J1K1 01-0 -1 J 2 K2 q1*q2* 00 01 11 10 00-1 -0 1-0 -0 1- 0-1 -1 0- Excitation table Page  271 .0 10.Example1: Design sync sequential circuit using JK x q1q2 0 01.0 10.0 01.0 11.0 1 00.0 01.

Example1: Design sync sequential circuit using JK Minimization for J1 x q1 q2 00 01 11 10 0 0 0 1 q1 q2 J 1 K1 x 0 J2K2 J 1 K1 1 J2K2 0-1 -1 0- 00 0 1 - 00-1 -0 1-0 -0 1- 01-0 -1 01 11 10 Excitation equations: J1 = xq2 J2 = x Page  272 K2 = x K 1 = xq 2 + q 2 x Output equation: y = xq1q2 .

Ex 1: Design sync sequential circuit using JK x 1 J2 CLK K2 q2 & & J1 q1 y CLK q2 =1 K1 q1 CLOCK Page  273 .

Ex 2: Design sync sequential circuit using JK  Design a synchronous sequential circuit using JK flip-flop. Page  274 . otherwhile y=0. The circuit has one input x. Output is 1 when receiving a string 0111 in input. one output y.

if x=1 the circuit counts down from 3 downto 0 and repeat.Ex 3: Design sync sequential circuit using JK  Design a synchronous up/down counter using JK with one input x. Page  275 . If x=0 the circuit counts up from 0 to 3 and repeat.

 S5. Produce the logic equation and draw a block diagram.  S2. code the inputs and outputs in binary.  S3. determine what needs to be stored in memory. Choose a flip flop type and derive the flip flop input maps or tables.Design Procedure for Sequential Systems  S1. Choose a state assignment. that is. Use state reduction techniques to find a state table that produces the same input/output behavior.  S7. Page  276 .  S4.  S6. that is. If necessary. From a word description. but has fewer states. what are the possible states. Derive a state table or state diagram to describe the behavior of the system. code the states in binary.

State reduction technique aims to simplify sequential circuit by reducing redundancy of the state transition diagram.S4. State reduction  State transition diagram may include redundancy.  Equivalence: – two states are equivalent if output sequences are the same when the same input sequence is given  Method 1: Procedure to get equivalent states  Method 2: Reduction of incompletely specified state table Page  277 .

State reduction  Examples: 0/0 B 0/0 0/0 D 1/1 A 1/0 C 1/1 0/0 1/0 1/0 F E 0/0 0/0 0/0 D B 1/1 1/1 0/0 1/0 AF 1/0 E 0/0 C 0/0 1/0 0/0 1/0 unify A and F Page  278 A and F have the same output and transition state for the same input .

State reduction  Examples: B 0/0 0/0 D 1/1 1/1 C 0/0 1/0 AF 1/0 E 0/0 B 0/0 0/0 1/1 1/0 C 0/0 1/1 DE 0/0 0/0 1/0 AF 1/0 unify D and E D and E have the same output and transition state for the same input Page  279 .

State reduction  Examples: B 0/0 0/0 1/1 1/0 C 0/0 1/1 DE 0/0 0/0 1/0 AF BC 0/0 1/1 DE 0/0 AF 1/0 1/0 unify B and C Page  280 .

State reduction current state A B C D E F next state 0 B D E D E B 1 C E D F F C output 0 0 0 0 0 0 0 1 0 1 1 0 0 0 current state AF B C D E next state 0 1 B C D E E D D AF E AF output 0 0 0 0 0 0 1 0 1 1 0 0 current state AF BC DE Page  281 next state 0 1 BC BC DE DE DE AF output 0 0 0 0 1 0 1 0 current state AF B C DE next state 0 1 B C DE DE DE DE DE AF output 0 0 0 0 0 1 0 1 1 0 .

the set includes nonequivalent state. Then divide the nonequivalent set and iterate (2) Page  282 .s2.…) – (2) Rewrite state transition table by using the set of state.State reduction  Method 1: Procedure to get equivalent states – (1) Find multiple states that have the same output with the same input. and treat them as a set of state S1 (s1. – (3) If the next state of the member of the set are different.

Example of method 1 (1/4)  Reduce the state of the state transition diagram 0/0 1/0 a 1/0 0/0 b 1/0 1/1 f 0/1 0/1 c Page  283 0/1 1/1 e 1/1 0/1 current state a b c d e f next state 0 1 a b d c a b f e d c e a output 0 0 4 0 1 1 1 1 0 1 0 1 1 0 d .

S2 equivalent c : S1.S1 d : S3.Example of method 1 (2/4) current state a b c d e f next state 0 1 a b d c a b f e d c e a output 0 0 4 0 1 1 1 1 0 1 0 1 1 0 (b.S2 e : S2. divide S2 into S2 and S4 S1 S2 S4 S3 a : S1.d.c) S2 (b.S1 f : S2.S1 Page  284 .S1 equivalent e : S4.e) and d are not equivakent hence.S2 b : S4.S2 b : S2.S2 f : S2.S1 d : S3.S2 c : S1.e) S3 (f) (2) Rewrite next state by using set of state S1 S2 S3 a : S1.S1 (1) Find a set of state with the same output S1 (a.

S1 d : S3.S2 b : S4.Example of method 1 (3/4) (2) Rewrite state transition table current state a b c d e f next state 0 1 a b d c a b f e d c e a output 0 0 4 0 1 1 1 1 0 1 0 1 1 0 S1 S2 S4 S3 a : S1.S2 f : S2.S1 current state S1 S2 S4 Page  285 S3 next state 0 1 S1 S2 S4 S1 S3 S2 S2 S1 output 0 0 4 1 1 1 0 1 1 0 .S1 e : S4.S2 c : S1.

Example of method 1 (4/4) Generate state transition diagram 0/0 1/0 a 1/0 0/0 current state S1 S2 S4 S3 next state 0 1 S1 S2 S4 S1 S3 S2 S2 S1 output 0 0 4 1 1 1 0 1 1 0 0/0 b 1/1 f 0/1 0/1 1/1 1/0 c 0/1 1/1 1 0/1 1/0 e 1/1 0/1 2 1/1 3 0/1 d Page  286 0/1 4 .

output are the same .State reduction  Method 2: Reduction of incompletely specified state table Incompletely specified: don’t care appears in the next state and output – 1: Find non compatible pairs – 2: Find compatible set that doesn’t involve non compatible pairs – 3: Obtain maximum compatible set – 4: Calculate minimum closed set – 5: Generate reduced state transition table Page  287 compatible pair: for every input.

c) (a.f) Page  288 .Example of method 2 (1/5) Implication table current state a b c d e f next state output input X1X0 input X1X0 00 01 10 11 00 01 10 11 d e a a d e b b c b e f - a e d e 0 1 1 1 0 - 0 0 0 1 0 0 0 b de c × ae d be × de ad e be ae ○ ef bf f × de × × ad ae bc a b c d e 1:fill in × at incompatible pair 2: fill in conditions to be compatible a set of not compatible pairs (a.d) (c.f) (b.f) (d.

f) (c.d.f) (c.e) (b.Example of method 2 (2/5) Decompose state set by non compatible pairs (a.e).(b.f) (d.e.e.(a.e) (b.e.e) (b.d.b.f) (d.f) other node Page  289 Maximum compatible set is (a.c.b.f) remove duplicated node remove pair involved to (d.(c.d.c.b.e) (e.f) (b.f) (a.f) (b.d.f) (b.d) (b.f) (a.f) (a.e.f) (a.f) (a.e.d) (c.d) (b.d.c.f) (c.e) (d.f) (d.d.(b.b.c) (a.f) (c.d.c.e) (a.e).c.e) .f) (b.d) (b.e.e.c) (a.b.d.e.e.f).d.d.e.e.e).

f) C4:(b.e) Logic function to represent each set involved a: C1+C2 b: C1+C3+C4 c: C4+C5 d: C2+C5 e: C1+C2+C4+C5 f: C3 Minimum closed set is a subset of maximum compatible set that involves all the state axbxcxdxexf = 1 (C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3 =(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4)C3 =C1C3C5+C2C3C5+C2C3C4 Page  290 hence (C1.C3.Example of method 2 (3/5) Maximum compatible set C1:(a.C3.(C2.C5).d.d.e) C5:(c.C5).e) C2:(a.e.(C2.e) C3:(b.c.C4) are candidates for minimum closed set .C3.b.

e) →(a.C4 is closed Implication table b de c × ae d be × de ad e be ae ○ ef bf f × de × × ad ae bc Page  291 a b c d e .C3.e) C5:(c.f) →C1.f).e).f)(a.(b.C5).d.C4) check state transition of each candidate by using Implication table C1→(d.e)(a.e).C3.Example of method 2 (4/5) C1:(a.(b.e)(b.c) →(a.e.(C2.(d.(C2.(b.e) C2:(a.f) →(C2|C5).c.C3 C2 →(b.e) C3:(b.C3.C4 C4→(a.f) C4:(b.(b.e).(b.e) →(C1|C2) C5→(d.c) →C2.e)(b.b.e).(a.(a.f) →(b.e).d).e).f).C3.C5).d.d) →C3.C2 C3→(a.d.(e.e) candidate for minimum closed set: (C1.(e.C3 C2.d).(a.d).e.d.e.

d.e).e.c.Example of method 2 (5/5) C2:(a.C4:(b.C3:(b.e) are used current state a b c d e f next state output input X1X0 inputX1X0 00 01 10 11 00 01 10 11 current state C2 C3 C4 next state input X1X0 00 01 10 11 output input X1X0 00 01 10 11 d e a a d e b b c b e f - a e d e 0 1 1 1 0 - 0 0 0 1 0 0 0 C2 C3 C3 C2 0 0 0 0 C2 C4 C3 C2 1 1 1 0 C2 C4 C3 C2 1 1 0 0 Reduced State Transition Table Page  292 .f).

 S4. determine what needs to be stored in memory.  S5. that is.  S2.Design Procedure for Sequential Systems  S1. that is. Choose a state assignment. Page  293 . code the states in binary. what are the possible states. code the inputs and outputs in binary. but has fewer states. Choose a flip flop type and derive the flip flop input maps or tables. Produce the logic equation and draw a block diagram. Use state reduction techniques to find a state table that produces the same input/output behavior. Derive a state table or state diagram to describe the behavior of the system. If necessary. From a word description.  S6.  S7.  S3.

 SP (Substitution Property): indicator for good state allocation.State assignment  State assignment is to encode the state table into binary notation. the result is a transition table that combines nextstate table and the output table.  Better state allocation results in an easy logic function for input of FF. C C1 a b c d a b c d divide state into blocks so that the next state of the same block exists in the same block C2 state is allocated to distinguish blocks of SP Page  294 .

State assignment current state q1 q2 q3 q4 q5 q6 current state u 1u2 u 3 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 next state input   X 0 q2 q3 q1 q5 q6 q4 1 q4 q6 q5 q2 q1 q3 block 1 (q1.q3) block 2 (q4.q2.q6) This partition is SP The first bit is used to distinguish the blocks. 0 u u u 3+ 1+2+ 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 next state input   X 1 u u2+ 3+ 1+ u 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 Page  295 .q5.

Chapter 5. Hardware Design Languages Page  296 .

The circuit counts from 0 to 13 then repeat. If x=0 the circuit counts up from 0 to 3 and repeat.  Problem 3: Page  297 .  Problem 2: Design a synchronous counter using JK with one input x.Problems  Problem 1: Design a synchronous up/down counter using JK with one input x. if x=1 the circuit counts down from 3 downto 0 and repeat.

6.d.b.8.13.d  Chapter 7: 7.Problems for sequential circuit design  Textbook:  Chapter 6: 6.15 Page  298 .5 – 7a.c. – 8a.5.9.11.b.d – 9a.c.6 – 4.c.b.

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