Self-Aligned Double Patterning (SADP) Compliant Design Flow

Yuansheng Maa*, Jason Sweisb, Hidekazu Yoshidaa, Yan Wanga, Jongwook Kyea, and Harry J. Levinsona
a
GLOBALFOUNDRIES, 1050 E Arques Ave, Sunnyvale CA 94085, USA
b
Cadence Design Systems, Inc., 555 River Oaks Pkwy, San Jose CA 95134, USA

*Corresponding authors: Yuansheng.Ma@globalfoundries.com; jsweis@cadence.com;

Double patterning with 193 nm optical lithography is inevitable for technology scaling before EUV is ready. In general,
there are two major double patterning techniques (DPT): Litho-Etch-Litho-Etch (LELE) and sidewall spacer technology,
a Self-Aligned Double Patterning technique (SADP). So far LELE is much more mature than SADP in terms of process
development and design flow implementation. However, SADP has stronger scaling potential than LELE due to its
smaller design rules on tip-tip and tip-side as well as its intrinsic self-align property. In this paper, we will explain in
detail about how to enable a SADP-friendly design flow from multiple perspectives: design constructs, design rules,
standard cell library and routing. In addition, the differences between SADP and LELE in terms of design, scaling
capability and RC performance will be addressed.

Keywords: Optical lithography, double patterning, LELE, SADP, design rule, standard cell library, placement, routing,
RC variations, timing

1. INTRODUCTION
Double patterning with 193nm optical lithography is inevitable for technology scaling before EUV is ready. In general,
there are two major double patterning techniques (DPT) [1-2]: Litho-Etch-Litho-Etch (LELE) and sidewall spacer
technology, a Self-Aligned Double Patterning technique (SADP). A lot of researches have been done for LELE in terms
of process development and design flow implementation; so far LELE is much more mature than SADP. However, with
the technology scaling, triple or quadruple patterning is needed with litho-etch-litho-etch type of process for a design,
which presents significant challenges towards process control such as overlay, decomposition as well as design strategy.
We anticipate that SADP may use fewer masks to implement the same design function due to its smaller design rules on
tip-tip and tip-side spacings, and it will have more relaxed process control requirements because of its intrinsic self-
aligning property.

Traditionally, people think designs for SADP are much too restrictive: 1D layout is preferred, 2D is extremely difficult.
Our previous papers[3-4] already showed that the above argument is not true - we can design wide ranges of 1D or 2D
features with any CD for the damascene layer if the spacer and/or the block layer are used for dielectric isolation. It is a
common view that it is very difficult to create a SADP-compliant design, which is understandable because unlike with
LELE, where features on the two masks come from the actual design, with SADP the features on the core mask and the
block mask cannot fully represent the actual design – you have to combine both masks to visualize the actual layout,
which is not intuitive in most cases. Due to the above reasons, SADP has never been considered seriously for the logic
design in manufacturing. There are many concerns about its process complexity, reliability and cost at this stage, on
which we also had some brief discussions in our previous papers[3-4].

In this paper, we will discuss why and how to make SADP-friendly design flow. In Section 2, we describe how to enable
SADP-friendly designs in terms of design constructs and design rules. In Section 3, we show an SADP-friendly standard
cell design, and explain the pin-accessibility advantage over its corresponding LELELE-friendly design. In addition, the
challenges for a SRAM design will be addressed. In Section 4, we discuss why SADP-aware routing uses less tracks and
2D jogs than LELE, and show the scaling capability and RC-variation differences between the two technologies. Finally,
Section 5 gives summary.

2. SADP-FRIENDLY DESIGN ENABLEMENT

Proper design rules are needed to enable double patterning (DPT)-compliant designs for either self-aligned double
patterning (SADP) or lithography-etch-lithography-etch (LELE). For a large scale of design, we rely on decomposition

Design for Manufacturability through Design-Process Integration VI, edited by Mark E. Mason, John L. Sturtevant,
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 tools to checkk if the design is DPT friendlly or not by inccorporating corrresponding ruules. Due to thee fundamental process-p
flow differennces between SADP
S and LELLE, the SADP decomposition
d strategy is draastically differeent from LELE E[3-4].
Unlike LELE E, where every y design featuree must be sent tot one of the twwo masks to meetm the single-exposure
requirementss, the SADP deecomposition puts p part of the design featurees on the core mask m as such thhat the rest feattures
can be defineed by the spaceers formed arouund the cores – not by the maask. The final target t design iss then completeed by
using the bloock mask to deffine tip or cornner locations ass well as large isolation
i areas. Hence, the SA ADP decompoosition is
not as intuitivve and straighttforward as LEELE is. In addittion, the core mask
m could beccome complicated when manyy 2D
features are involved
i - multtiple solutions are possible. It is understanddable that a dessigner may thinnk that creatingg a
SADP-compliant layout, esspecially on thee standard cell level for non-rrouting layers, is intimidatingg because it demands a
certain amouunt of knowledg ge on both process and decom mposition besiddes design.

Our goal is too help designerrs, including EDA

E tools, to design
d for SAD
DP better even if
i they cannot visualize
v the coore and
block masks by setting up design
d rules annd disallowing certain design constructs in advance.
a

In this section, we first clarrify the design challenge diffeerences betweeen LELE and SADP,
S and thenn discuss the design
d
rules to elimiinate mask rulee check (MRC)) violations. Finally,
F we showw re-compositiion results from
m the core andd block
masks.
2.1 The “O
Odd” differeence betweeen LELE an
nd SADP
As we mentiooned earlier, th he SADP proceess flow and thhe decomposition approach iss completely diifferent from LELE.L
Therefore, thhe correspondin ng design challlenges will be different
d for thhem. One of thee common queestions people haveh is
whether the odd
o cycle for LELE
L is also a problem for SAADP. As we know,
kn the odd cycle
c is the term
minology usedd to
describe the color-conflictio
c on aroused in LELE
L decompositions wheree adjacent featuures cannot be decomposed with w two
a example havving LELE oddd cycles due to the sub-resoluution side-side and tip-tip spaces.
colors. Figurre 1(a) shows an
Polygons #1,, #2, and #3 haave to be on thrree masks; and the same appllies to polygons #4, #5 and #66 unless we moove
polygon #6 further
f apart fro
om #4 as show wn in Fig. 1(b). However, withh SADP these constructs no longer
l are odd cycles,
and they are SADP friendly y as shown in Fig.
F 1(c). This is mainly becaause the tip-tip space can be resolved
r using the
block mask, and the side-siide is defined by b the spacer – not by the mask. The minim mum tip-tip/sidde spacings for SADP
are almost eqquivalent to thee different-massk tip spacings for LELE, andd are much smaaller than the same-mask
s rulees. As
such, this typpe of construct should be encoouraged in SA ADP-compliant designs even though
t they haave to be forbiddden in
LELE.

(a)
( (b) (c)
Figure 1. Simple line space (a) decomposition
d o LELE (b) and SADP (c).
of

The typical bad

b constructs for SADP are thoset with oddd-jogs – the 2D D jog with odd sub-resolution-
s -pitch. (See Taable I.)
Odd-jogs maay take a varietty of different shapes.
s Table I lists some of the
t most comm mon ones with odd-pitch U shhapes
and Z shapess. Here we claim m a design to be
b SADP-friendly if no blockk mask is used in i edge definittions, and a dessign to
be LELE-frieendly if no stitcching is neededd. Regardless of o their large orr small tip-tip or
o tip-side spacces, these consttructs
won’t be SAD DP friendly, allthough they (eexcept the singgle-pitch U) cann be decompossed with SADP P by using the block
b
mask to definne some of their edges. For LELE,
L it is seenn that without stitching,
s thesee constructs aree not decompossable
either; to be LELE
L decomp posable, the tip--to-side spacinngs for these coonstructs have to t be large enoough to enable the
stitching – thhe construct with odd-pitch Z needs a largerr tip-side spacee than the U. Siince there is noo room left for

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 stitching on the single-pitch Z feature with technology scaling, we couldn’t avoid using two-colors for a track as shown
in Table I – this is completely unwanted for the standard cell library design.

Table I. Problematic odd-pitch jogs for SADP.

SADP Decomposition LELE Decomposition

SADP Decomposition LELE Decomposition
Design Constructs (No Block-defined- (without stitching)
(Block-defined-edge) (with stitching)
edge)
Odd-
pitch
U (1-
pitch)
Odd-
pitch
U (3-
pitch)
Odd-
pitch
Z (1-
pitch)

Problematic odd-pitch jogs are those constructs with features following the same orientation as the jog sides, as in Table
I. The constructs in Table II have odd-pitch jogs, but they are SADP-friendly since features have orientations different
from the jog sides.

Table II. SADP-friendly Odd-jogs.

SADP Decomposition
Design Constructs
(No Block-defined-edge)

Odd-pitch U (Three-pitch)

Odd-pitch Z (Three-pitch)

To determine whether or not a design is LELE-friendly is by checking if it has odd cycles. However, being free of odd-
cycles will not guarantee a design is SADP-friendly, especially when it has odd jogs as shown in Table III. Although
they are SADP decomposable by using the block mask to define some of their edges, the design may not be desired
because the misalignment between core and block masks can induce CD changes which are particularly unwanted for the
critical design features.

Table III. Constructs that are free of odd cycles - LELE-friendly, but they are not SADP-friendly.

Design Constructs LELE Decomposition SADP Decomposition

Odd-pitch U (Three-pitch)

Odd-pitch Z (single pitch)

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 In order to have a construct with U shapes in an odd-pitch n (n=3, 5, 7 …) be SADP friendly, the maximum number of
lines with the minimum line-width inside a U is n-3; and they can be single pitch apart and triple/more pitches apart from
each other, but not two pitches apart. Therefore, no feature with the minimum line-width should be inserted inside a 3-
pitch U construct, and at most 2 features for constructs with 5-pitch. It should be noted that similar rules also apply for
constructs with odd-pitch Z. Table IV illustrates how to enable designs with odd-pitch constructs to be SADP-friendly
by following the above rules. In general, two adjacent partial tracks will be wasted in SADP-friendly designs with odd-
pitch U or Z; while one partial track for LELE-friendly design as shown in Table III. In addition, the SADP tip-tip or tip-
side rules advantages over LELE can’t be fully used in any designs with odd-pitch U or Z, since the same-mask rule has
to be applied given some design situations as shown below in Table IV.

Table IV. SADP-friendly design with odd-pitch U and Z constructs when only minimum-line-width features are permitted: dashed
rectangles represent the must-be-skipped tracks.

SADP Decomposition
Design Constructs Comments
(No Block-defined-edge)
(Equivalent to) 3-pitch U
cases: no features should
be inserted inside

(Equivalent to) 5-pitch U

cases: at most two features
can be inserted inside

It is observed that wide features can be used to break the non-SADP-friendly odd jogs. By merging those two adjacent
partial tracks - those to be skipped in designs with minimum line-width, we can achieve SADP friendly designs. Table
V shows some SADP-friendly examples with wide lines in odd-pitch jogs; it can be seen that their SADP
decompositions are clean and straightforward, and the tip-to-side spacing may take spacer width or
2Spacer_width line_width depending on the design.

Table V. SADP-friendly design with odd-pitch U and Z constructs when wide features are allowed.

SADP Decomposition
Design Constructs
(No Block-defined-edge)

An SADP-friendly design initially seems to be more restrictive than a LELE-friendly one: for cases with odd-pitch U or
Z shapes, two partial or complete tracks have to be skipped in a SADP-friendly design in contrast to one track for LELE
if only minimum-line-width features are to be used. However, the design capability between the two becomes equivalent
when wide lines are allowed to be used in designs.

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 Since U or Z shapes need to be put on cores or formed by spacers altogether at once with SADP, it restricts the dummy
core from insertion for constructs with odd-pitch U or Z shapes. L-shape or T-shape provides more flexibility, and is
generally SADP friendly. If a design allows breaking the U or Z shapes, as seen in Table I, into L shapes, then it can
become SADP friendly by following proper tip rules as shown in Table VI. For smaller technology nodes, the odd-pitch
Z-to-L construct cannot occur in designs because the half pitch of the tip-side space is less than the required design rules.

Table VI: SADP-friendly design with L-shape constructs.

Design Constructs SADP Decomposition LELE Decomposition

Odd-pitch U-to-L (single

pitch)

Odd-pitch U-to-L (Three-

pitch)

Odd-pitch Z-to-L (single pitch)

With even-pitch U or Z constructs, a design can be both SADP and LELE friendly as shown in Table VII, and every
track can be used under any situations, which provides enough flexibility for design. A SADP-friendly design with even-
pitch jog can fully take advantage of the smaller tip-tip or tip-side rules allowed.

Table VII. SADP-friendly design with even-pitch U or Z constructs.

Design Constructs SADP Decomposition LELE Decomposition

2-pitch U construct

2-pitch Z construct

2.2 Design rules to avoid block mask MRC

Stitching is a common method of resolving odd-cycles for the LELE process, and it is the major cause for MRC
violations with LELE decompositions. For SADP, the MRC challenges mostly come from the block mask. Now let’s use
an example and explore the various MRC violations sources. Fig. 2 (a) is an example of a LELE-complaint design with
sub-resolution pitch, and Fig. 2 (b) shows the core mask through decomposition. Adding spacer around these core
structures results in Fig. 2(c).

(a) (b) (c)

Figure 2. (a) a LELE-complaint design with lines and spaces; (b) Core mask from the SADP decomposition of (a); (c) Spacer formed
around features on the core mask

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 Areas that are not spacer will be filled with metal unless they are blocked using the second mask. The complexity of the
block mask can be challenging for the OPC and mask manufacturing, but we will explain how these can be overcome.
Let’s look at the example after we apply the block mask on top of spacer shown in Fig. 2 (d). Looking at the block mask
alone as in Fig. 2 (e), we can see better where the areas of concern would be: single-point-contact, narrow block spacing,
and small steps etc.

(d) (e)
Figure 2. (d) Block layer is added on top of spacer; (e) Block mask alone

They cause MRC violations to occur for mask manufacturing where dimensions are smaller than permitted minimum
widths/spaces. However, upon further inspection using Fig. 2 (d) showing spacer you can see that some of these
violations always occur over a spacer. There will be no metal deposited in these locations so whether the block mask
merges or opens in these locations is irrelevant. These locations can be exported to a waiver file for any inspection tool,
but the concern is that it would give rise to OPC/RET and defect-inspection difficulty on wafers later on. Table VIII
summarizes three typical constructs causing the above MRC errors. By restricting a minimum line end separation or
overlap on adjacent tracks we can avoid these MRC issues altogether: the minimum block line width or space are
guaranteed, and those single-point contacts, narrow block space and small steps can be eliminated.

Table VIII. Design rules to avoid potential MRC errors.

Rule Name Design Construct SADP Decomposition Design Rule

Adjacent-track line tip to tip

space
A min. block width

Parallel run length of adjacent

tracks
B min. block space

A 0;
Step height of non-aligned tips
or A min. block width

We need to avoid 2D L shapes on the block mask as much as possible in designs, because the corner-rounding issues
after patterning can generate sharp or non-rectangle line ends, which may cause reliability problems. Therefore, under
the conditions that the design rules are followed, lines on two adjacent tracks should align their ends as much as possible
by either stretching or squeezing their line lengths as long as their surrounding environment permits. As such, more
rectangular blocks on the block mask can be generated. The design in Fig. 2 (a) can be modified to a design shown in
Fig. 3 (a) without changing its circuit function. Fig. 3 (b) shows its SADP decomposition result. It can be seen that
MRCs are removed by following the design rules in Table VI, and 2D L shapes on the block mask are reduced
significantly because of aligned line ends. It is unrealistic to completely prevent L-shape components on the block mask.
But we can enlarge the step size of the L-shape to relieve the corner rounding impact. In that case, designers, including
EDA tools, need to consider features on at least three tracks per line-end, instead of two, so that the minimum step height
is about the double-pitch size instead of single-pitch.

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 (a) (b)
Figure 3 (a) Modified design from Fig. 2 (a) with more aligned line ends; (b) SADP decomposition result

2.3 Re-composition of Core and Block Masks

For designs with 2D constructs, taking the core and block mask to perform a re-composition on wafer would likely yield
some “stubs” at certain locations. An example is shown in Table IX. There are two even-pitch Z constructs in the design.
In SADP decomposition, pseudo-core features are added to create T shapes to assist spacer generation; but they have to
be blocked later to realize the design purpose. Since critical edges are to be formed by spacers, the process tolerances,
such as overlay, CDU and LER, must be taken into account in block edges definitions. Thus a certain space needs to be
left between core and block features, which induces the occurrence of stubs as seen below. As long as pseudo cores are
involved in 2D-feature generations in SADP, stubs will appear. We deem these stubs to be negligible for design and they
will be naturally rounded off by the process.

Table IX. “stub” resulted from the recomposition for 2D constructs.

Design SADP – Core SADP - Block Re-composition

3. SADP-FRIENDLY STANDARD CELL LIBRARY AND SRAM

A standard cell library is a collection of standard cells which provides boolean logic functions such as AND, OR, XOR,
XNOR, inverters, more complex ones like AOI, or storage functions as with flipflops or latches. The cells in the library
are typically full-custom layouts, and are realized with a fixed height so that they can be placed in rows, easing the
process of automated placement and routing. With technology scaling, both logic and SRAM designs become extremely
challenging because smaller cell heights and areas require corresponding design rules scaling without significant cost
change.

In this section, we first compare two physical designs for a standard cell with SADP and LELE rules respectively, and
then discuss an SRAM design.

3.1 Standard Cell Library

With design rules and design constraints in mind, we have created SADP-friendly and LELE-friendly standard cell
libraries. To be noted that in order to have more flexibility in cell designs, we don’t intentionally forbid odd-pitch
constructs – we will use it as long as it is needed and the design rules are followed. Table X shows two physical designs
for a standard cell by using LELE and SADP design rules respectively. It is seen that due to the tip-side limitation,
triangular color conflictions arise in the design following LELE rules, thus 3 masks are needed. For the physical design
following SADP rules, only 2 masks are required because tip-side space can be either defined by spacer or by the block
mask.

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 Table X. Physical designs for a standard cell realized with SADP-friendly rules and LELE-friendly rules.

Design Constructs Corresponding Decomposition

SADP-Friendly Design

LELELE-Friendly Design

Note that the above example is a five-pin cell. The pin accessibility is always one of the biggest concerns for placement
and routing. As we know, the more tracks that are accessible to a pin, the better the routing capability. By assigning
tracks to each design with pin numbers labeled as shown in Table XI, we found out that only one track is available to the
first 4 pins of the LELELE-friendly design – those two tracks on the boundary of the pins cannot be used. There are 2
tracks for the 5th pin but this requires via drops at the L corners, which is not process friendly. In contrast, the SADP-
friendly design has much better pin accessibility: 3 tracks available to pin #1 and #5; 4 tracks to the rest of pins. The
LELELE design needs to be improved so that more tracks can access the pins, but how much remains the question
because of the characteristic decomposition method and design rules.

Table XI. Track assignment to each design.

LELE-Friendly Design SADP-Friendly Design Comments

Black lines represent the middle

of tracks accessible by pins

3.2 SRAM
In general, a SRAM design is very regular, thus intrinsically it prefers SADP. But it is also the densest region on the chip
– designs are fully customized so that not a single nanometer is wasted. As such, the block mask patterning could be
challenging. Table XII shows an example of SRAM design, and it can be seen that two masks may be needed for the
block patterning if there is not enough space between tip and line, unless proper design rules are enforced to prevent this
from occurring.

Table XII. An SRAM metal-1 layer and its SADP decomposition.

A SRAM Design SADP Core SADP Core + Block (zoom-in)

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 4. SADP PLACEMENT AND ROUTING
Place and route is a stage in the design of integrated circuits. As the name implies, it has two steps: placement and
routing (P&R). Placement decides where to place all the standard cells to form large blocks of logic designs in a
generally limited amount of space; routing decides how to connect the placed components. As mentioned in our previous
paper[4], these steps must be DPT-aware. Utilization, a special terminology, is used to describe the design density after
placement and routing: the larger the utilization, the smaller the chip area needed for a design, so the better the scaling
capability. Placement and routing are usually performed by electronic design automation (EDA) tools. Due to the
process and design constraints differences, we expect different optimized P&R tools to realize SADP-friendly and
LELE-friendly designs.

In this section, first we show the pin-accessibility differences in P&R for SADP-friendly and LELE-friendly designs,
then compare their scaling capability by checking the maximum utilization each can use, finally discuss about their
process-variation induced RC performance variations differences .

4.1 Pin Accessibility

We used the SADP-friendly standard cell library in our placement and routing study for both SADP and LELE because
of its better pin accessibility as seen from Table XI in section 3. Taking the same SADP-friendly standard cell in Table
X as an example, Table XIII shows how via drops and track assignments are adjusted to access pins so that design rules
are met for SADP and LELE. Assuming the access to the first three pins is set initially, and then in a SADP-friendly
design the rest two pins can be accessed straightforwardly and more flexibly: there is no need to change the first three
track locations; the newly assigned two tracks are interchangeable if the need arises. Furthermore, if a design asks for the
change in accessing the first three pins, it won’t affect the already-set arrangement of the rest two pins, which is
beneficial for P&R optimization. However, this design won’t be LELE-friendly because of the small tip-tip spacing
induced odd-cycle. In order to make it LELE-friendly, the first three track assignments should be adjusted to leave
enough rooms for the tip-tip spacing, and the track assignment for the rest two pins are not interchangeable. It is
expected that in a LELE design, any access change to any single pin will cause corresponding track assignment change
to other pins, which could place a significant toll on P&R tools.

Table XIII. Track assignments for pin-access in a SADP-friendly design and a LELE-friendly design.

A standard cell with 3 pin accessed Pin access in a SADP-friendly design Pin access in a LELE-friendly design

The above shows the pin-accessibility difference for an individual standard cell. Table XIV shows the process flow for
pin-connection in two cells. Here, the blue color represents the layout on Mx level, pink on Mx+1 level, and yellow on
Mx+2 level. The first item shows the initial settings of standard cells placement and track assignments. The two cells are
2-pitch size apart from each other. Two pins from these two cells are highlighted in green to be connected as seen in item
2. Unlike in LELE-friendly design where a 2D Z-jog is needed to connect them, no 2D construct is needed for a SADP-
friend as shown in item 3. If two cells are moved closer in a design with higher density shown in item 4 – now 1-pitch
size apart from each other, and if there is a track from Mx+1 to assist a connection with a track from Mx+2 as shown in
item 4, the resulted small tip-side space in the LELE design could require entirely new track assignments thus routing
across layers, which won’t occur in a design for SADP. Therefore, a SADP-friendly design will use less tracks and 2D
constructs than a LELE-friendly one, which means a better scaling potential than LELE.

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 Table XIV. The process flow for pin-connection in two cells with SADP-friendly rules and LELE-friendly rules.

1. Two adjacent standard cells

with tracks assigned to certain
pins

2. Two pins from these cells to

be connected

SADP-friendly design LELE-friendly design

3. Pin Connection in a two-layer

setting

4. Pin Connection in a three-

layer setting;
To be noted that cells are
moved closer in designs with
higher density

In order to check the scaling capability of these two different technologies, we used Cadence EDI to implement the P&R
at different utilizations with the SADP-friendly standard cell library for both SADP and LELE. The major set-up
difference is on the different tip rules used in SADP and LELE designs. Fig. 4 shows how the DRC errors vary with the
utilization.

Figure 4. Scaling capability difference between SADP and LELE: for the same amount of DRC errors, SADP use smaller chip size
than LELE
It is seen that the larger the utilization, the larger the DRC errors. In addition, the number of DRC errors in LELE
designs is generally larger than those in SADP designs. The most difficult errors come from color errors. Some of DRCs
can be fixed, but it becomes harder when the utilization increases. For the same amount of DRC errors, higher utilization
can be achieved in SADP than LELE, and the utilization gap between the two, which represents their scaling capability
difference, is quite significant based on our experiments data. In general, SADP has better scaling capability than LELE.

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 4.2 RC Performance
Double patterning processes bring new elements into circuit RC variation. It is commonly understood that a SADP
processes will provide better control on intra-layer line spacing and hence will have less impact on interconnect RC
variation compared with a LELE process. However, no study has yet been done to compare the variation gap between
SADP and LELE processes in an advanced technology node for real design data. In this paper, a method has been
established to assess circuit RC variation from LELE and SADP processes based on projected design dimensions and
process control capabilities. The result for a standard cell design case has been compared and summarized.

The major contributors to line-width and space-width variations from a LELE process is misalignment and lithography
and process critical dimension uniformity (CDU)[5-6]. In a SADP process, misalignment no longer plays a role. However,
spacer CD variation originating from spacer deposition and etching processes and core sidewall angles can affect the
metal line space and hence needs to be considered[3-4]. Fig. 5 illustrates how the misalignment, lithography and spacer
CD variations may affect silicon dimensions in LELE and SADP processes, respectively.

Figure 5: (a) Silicon dimensions of a 3 line pattern for LELE process with both mask1 and mask2 CD increase of α and mask2
misaligned to the left side of mask1 by β; (b) Silicon dimensions of a 3 line pattern for a SADP process with core CD increase of α
and spacer CD decrease of δ

The impact of each components on silicon CD and interconnect RC is also summarized in Table XV for possible worst
cross-couple case.

Table XV. Silicon dimension, metal line resistance (R) and coupling capacitance (C) impact from each process variation component
for LELE and SADP processes.

To fully capture the overall double patterning process impact on circuit RC and delay, a data shift and sizing method has
been applied to LELE and SADP design databases to mimic 3 sigma double pattering process variations with all possible
combinations of alignment and CDU. The RC of critical nets is then extracted through traditional post layout RC
extraction flow for each design. The total RC variation is summarized and compared between LELE and SADP
processes. The whole characterization flow is illustrated in Fig. 6. Results of standard cell designs are shown in Fig. 7.
Data show approximately twice the capacitance variation for a LELE process over a SADP process. The study also
shows the difference of net resistance variation of the two processes is relatively small in the cell level. The total RC
variation is hence also about twice as large for a LELE processes compared with a SADP processes for the critical nets.

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 Since the assessed design case has relatively short metal routing, the actual impact difference could be bigger for a
design that is more sensitive to interconnect coupling capacitance. The cell level data indicates that SADP process have
an advantage over LELE process from an electrical performance point of view.

Figure 6: SADP vs. LELE RC impact characterization flow

Figure 7. (a) Comparison of SADP and LELE double pattering process impacts on total net capacitance variation; (b) Comparison of
SADP and LELE double pattering process impacts on total net RC variation.

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 5. SUMMARY
The design challenges are completely different for SADP and LELE due to their own characteristic process flows and
the decomposition approaches. In general, a LELE-friendly design needs to avoid any 1D or 2D constructs with odd-
cycles. But free of odd-cycle does not guarantee a design to be SADP-friendly. Typically, problematic designs for SADP
have odd-pitch jogs; they can be fixed either by inserting wide features or skipping two adjacent partial tracks within the
jogs boundary, but the tip-side spacing needs to be as large as the same-mask tip-side space for LELE in most cases. A
SADP-friendly design can contain any constructs in L-shape or even-pitch-jog constructs in U or Z shapes, which allows
no waste on track space and no lose on the tip-side spacing advantages provided by the SADP process.

For the non-routing-layer design in a SADP-friendly standard cell library, any constructs, either in odd-pitch or in even-
pitch, can be tried or used; but routing layers which are implemented with EDA tools, the odd-pitch jogs with U or Z
shapes should be discouraged as much as possible to avoid the routing complexity.

In addition, it is seen that a SADP-friendly standard cell library can have better pin-accessibility than a LELELE-
friendly one: a pin accessible by more tracks provides more flexibility for routing. Given a fixed cell height, we can have
2-mask solution with SADP-friendly design as opposed to 3-mask solution with LELELEL because SADP allows
smaller tip-tip or tip-side spacings than LELE. Due to the same reason, SADP uses less tracks and 2D jogs in routing.
Our preliminary routing results with the SADP-friendly standard cells show that SADP has better scaling capability than
LELE. Furthermore, since the critical dielectric space is governed by spacer which can be well controlled, the
capacitance and RC variations on the cell level with SADP could be twice less than LELE. In summary, it is seen that
the SADP technology provides a better platform for scaling before EUV is ready, and it is time to put effort to make it
happen.

ACKNOWLEDGEMENTS
The authors would like to thank Roja Veeramachaneni for cadence EDI support.

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