Analysis of Ground Void Patterns for Differential
Microstrip Impedance Matching on Surface Mount Pads
Kuan-Ting Wu, Hank Lin, Bin-Chyi Tseng, and Jackson Yen
Advanced Electromagnetic & Wireless Communication R&D Center
ASUSTeK Computer Inc.
Taipei, Taiwan
Abstract—The mounting pads of surface mount device
introduce transmission line discontinuities and cause signal
2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC) | 978-1-7281-7621-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/APEMC49932.2021.9597190
integrity degradation. To compensate for the excess parasitic
capacitance, ground void may be utilized on the ground plane
underneath the pads. In this paper, conventional patterns of
plane cutout are presented and analyzed using a 3-D full wave
solver. In addition, new void patterns with circular outline are
proposed and investigated. From the simulation results, for a
pair of 85-Ohm differential traces with 0201 package-sized
components in series, suitable design of ground void can be
determined, and can effectively control the trace impedance.
Keywords—ground void, ground plane cutout, circular outline,
surface mount pad, signal integrity
I. INTRODUCTION
As integrated circuit (IC) and printed circuit board (PCB)
technologies continue to advance, system designers inevitably
confront more challenges such as higher data rate, more than
a couple of gigabits per second, which introduces non-ideal
electrical properties associated with frequency-dependent
effects [1]. Since signal integrity issues put limits on the high-
speed performance, ensuring reliable broadband transmission
has been a key factor to competitive product design.
Differential routing takes advantage of noise immunity,
and it may be used with some surface mount devices (SMDs)
to provide common-mode suppression, DC-blocking, electro-
static discharge (ESD) or short-circuit protection. However,
the width of surface mount technology (SMT) mounting pads,
which mostly are wider than the trace width, results in excess
shunt capacitance and causes transmission line discontinuity.
To compensate for this undesired effect, the region on the
ground plane underneath SMT pads can be properly removed
to minimize impedance variation along the propagation path.
For scenarios involving SMD package dimension of 0402,
0603 and 0805, previous works used rectangular ground void
on the ground plane next to the routing layer, fixed the cut-out
length equal to end-to-end distance of two pads, optimized the
cut-out width [2][3][4], or even varied the substrate thickness
corresponding to the distance between the SMT pad and the
layer underneath the ground void to mitigate discontinued
characteristic impedance [4].
Apart from the above mentioned reactance compensation
methods, related design practice such as avoiding right angle
corners on PCB traces also aims at eliminating parasitic
capacitance at 90-degree bends [5][6], and preventing from
DC current crowding with regard to heating and reliability
issues [7]. In addition, skin effect plays a critical role in high-
frequency current distribution [1]. While curve routing has
been widely adopted in PCB design for high-speed signals, the
effects of right angle on the current return path are rarely
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found in literatures. In relevant fields, some previous studies
numerically computed the electrostatic potential regarding the
size of a rectangular or circular aperture [8][9], demonstrated
the plane-pair discretization algorithms for arbitrary shape
with cutouts [10][11], and illustrated the conformal mapping
approach to optimize the cutout parameters [3].
In this study, ground void patterns with rectangular and
circular outlines are proposed for standard 0201 packages.
These patterns are used in conjunction with 85-Ohm
differential routing, which is common in high-speed interfaces.
Although these voiding methods apply to design with other
package sizes, 0201 package with the smallest pad width
possesses the lowest impedance discontinuity among others,
and saves precious board area. Comparison of simulated
differential return loss and insertion loss, impedance profile,
and surface current density are presented. These results may
provide the layout guide for SMD impedance matching and
expedite the design process for future applications.
Il. CUTOUT PATTERNS OF GROUND PLANE UNDERNEATH THE
SMT PADS
Physical geometries and material properties determine the
behavior of electromagnetic wave propagation in the PCB
structure. According to transmission line theory [1], the
characteristic impedance of a lossless line is
L
40=\G (1)
where L and C are inductance per unit length and capacitance
per unit length, respectively. The void on the ground plane
aims to lower the magnitude of C in (1). To compare various
cutout patterns, the structure to be analyzed shown in Fig. |
with 0201 SMT pads and reference planes for S-parameter de-
embedding, is designed and modeled in a 3-D simulator.
15 mm
Reference plane —
as 10 mm
25 mm eae
Reference plane —
13 mm
30 mm
(a)
Fig. 1. Test structure with a pair of differential traces. (a) Top view.
 (a)
» Mg ~ 7
Mi porn
hi fe.
(b)

Fig. 2. Void patterns underneath the SMT pads. Two vertical rectangular
frame indicate the SMD placement, and four-squared outlines mark the pad
locations on top layer. (a) No cut-out. (b) Four squares. (c) Rectangle pair.
L1_ Top ; | (d) One big rectangle. (e) Four circles. (f) Capsule pair. (g) One big circle.
L2_Gnd

L3_Inl
TABLE II. SUMMARY OF CUT-OUT AREA OF GROUND VOID PATTERNS

4 _VCC
Fie . Cut-out Area Fig " Cut-out Area
(c)
(a) 0 (e) Aw?
Fig. 1. (continued) Test structure with a pair of differential traces.
(b) Zoom-in view of the 0201 SMT pads. (c) The stackup. (b) Aw? (f) 2w?[1 + 2(¢ 7) + x/w)]
(c) 2w( x + 2w ) (g) (x + 2w )(y + 2w )
(d) (x + 2w )(y + 2w )
Table I gives the stack-up information from portion of a w is the width of the square pad.
x is the edge-to-edge distance between two pads of a SMD.
practical design. The 4-mil trace width and 6-mil intra-pair - y is the edge-to-edge distance between pads from one to the other SMD.
distance give an 85-Ohm differential impedance, typically To determine the diameter D of circular cutout(s), one can use the identity
adopted in modern high-speed interfaces, like DisplayPort™, A =r =nD"/4
where A is the calculated area.
High Definition Multimedia Interface (HDMI), Peripheral
Component Interconnect Express (PCIe), and Thunderbolt™.

TABLE I. STACKUP INFORMATION

Layers Material | Thickness (mil) DK* DF*

Solder Mask 0.6 4 0.035
L1_ Top Copper 1.55
Prepreg 2.2 3.62 0.016
L2_ Gnd Copper 0.65
Core 3 3.92 0.013
L3_ Inl Copper 0.65
Prepreg 2.8 3.84 0.014
L4 Vcc Copper 1.2
* DK and DF are dielectric coefficient and dissipation factor at 10 GHz.

Fig. 2 presents various ground void patterns for L2_ Gnd

layer in Fig. 1-(c). Fig. 2 also indicates the SMD placement by
vertical rectangular frames, and pad locations on L1 Top
layer by four squared outlines. The L3_ In layerandL4 Vcc
layer are solid ground planes and remain unchanged. It is
worth mentioning that squares in Fig.2-(b) and circles in
Fig.2-(e) have the same area, and the capsule shapes in Fig.2-
(f) are padded from Fig.2-(e). Moreover, both the rectangle in
Fig.2-(d) and the circle in Fig.2-(g) have equal area. Table II
summarizes the area of each cutout patterns.
There are four ground vias included in this analysis, and
they are plated-through holes (PTH) vias close to the SMT
pads, as shown in Fig. |. These vias are used to connect each
ground plane in the PCB stackup. Meanwhile, to capture the (d) (g)
reactance variation solely from the plane cut-out, two pads are Fig. 3. 3-D isometric view of ground void patterns corresponding to Fig. 2
with solder mask window on the top layer.
shorted together for each SMD and simulated using a 3-D field
solver, which is similar to the methodology discussed in [12].

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 UI. SIMULATION RESULTS
Simulated Differential Insertion Loss
According to the simulated mixed-mode S-parameters,
differential return loss and differential insertion loss are 00 Re ——
obtained for each ground cutout pattern in Fig. 2. Furthermore,
Fig. 3 demonstrates the 3-D view of each cutout and the solder a oe SS ———
S -0.4 NSS
mask window on top layer. a
E -0.6 _ — sS
As shown in Fig. 4, “one big circle” cutout almost provides >
~
=~
“4
E -0.8 \
the most effective impedance matching, since it has mostly the a ™~N
lowest Sgai1 curves from 18 GHz to 22 GHz, and from 24 GHz a -1.0 “
nN NX
to 40 GHz, while “one big rectangle” surpasses the others at -1.2 ~
the frequency below 18 GHz. “Capsule pair’ also has -1.4
relatively good differential return loss. In addition, “capsule 0 5 10 15 20 3925 30 = 35 40
pair” is superior to “rectangle pair,” and others are not so Frequency (GHz)
effective. However, the discrepancy between “four circles”
and “four squares” is not significant, which means their effects
------ One big circle (1C) One big rectangle (1R)
on field distribution are quite similar. Fig. 5 gives the Sai
simulation results, and indicates the insensitivity of Capsule pair Rectangle pair
differential insertion loss to the void patters. However, the — -— Four circles (4c) Four squares (4s)
case without ground cutout is inferior to those with cutouts, — — Nocut-out
and their difference is larger than 0.1 dB beyond 10 GHz.
The impedance profiles from time-domain reflectometer Fig. 5. Simulated differential insertion loss with different patterns of
ground cutout underneath the SMT pads.
(TDR) simulation are shown in Fig. 6. The results show that
“1C”, “IR”, and capsule-pair ground voids may have more
efficacy than other patterns in controlling routing impedance.
The contour plots of simulated surface current density Jsurr at Simulated TDR Waveforms
20 GHz are given in Fig. 7 to Fig. 9, and their peak values are
summarized in Table III. For patterns with equal cut-out area, 90
the void with circular outline has lower maximum Jur than
the void with right-angle outline; the cases of larger cut-out
area also manifest larger discrepancies in their peak values. S \
3 \\. +
The three new ground void patterns proposed in Fig. 2-(e) = 75 \ /
oO
to (g) with round edge having the smaller perimeter, compared a.S \\ /
70 /
to Fig. 2-(b) to (d), may not only have lower current crowding,
but also allow more smooth current path and field distribution
to alleviate impedance discontinuities. For characteristic
65
\/
impedance requirements other than 85 Ohm, the cutout area 60
0 20 40 60 80 100
can be optimized by using different radius in Fig. 2-(e) to (g)
to properly cope with the excess shunt capacitance. Time (ps)

oo---- One big circle (1C) One big rectangle (1R)

Simulated Differential Return Loss
Capsule pair Rectangle pair
— -— Four circles (4c) Four squares (4s)
— — Nocut-out
S-Parameters (dB)

Fig. 6. Simulated impedance profile with different patterns of ground

cutout underneath the SMT pads.

Other advantage of using circular-outlined void patterns

could be found in high density PCB layouts. If there is any
PTH via close to the added rectangular cutout, the corner of
0 5 10 15 20 25 #30 35 + =©40 this cutout and the via antipad lead to a narrow area on the
Frequency (GHz) ground plane, of which the dimension may be smaller than the
allowable minimum width of conductors dmin suggested by the
ee One big circle (1C) One big rectangle (1R) manufacturing process. As a result, more than expected areas
Capsule pair Rectangle pair should be removed from the ground. The circular cutouts may
free from this situation once the center-to-center distance
— -— Four circles (4c) Four squares (4s)
between the void pattern and the closest via satisfies
— — Nocut-out
L > Feutout + Amin + 7 antipad (2)
Fig. 4. Simulated differential return loss with different patterns of ground
where /cutout ANd /antipad are the radius of the circular-outlined
void underneath the SMT pads.
cutout and the radius of PTH via antipad, respectively.

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 ACKNOWLEDGMENT
The authors would like to acknowledge their colleagues,
Steven Tsai, Jiaming Kang, JenYung Li, and Jerry Bai from
EM Numerical Simulation & Modeling Department in ASUS,
for their support and valuable comments.

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IV. CONCLUSIONS
From the simulation results, various ground void patterns
on the ground plane underneath the SMT pads are investigated.
The comparison results of differential return loss, differential
insertion loss, impedance profile, and surface current density
indicate that larger circular-outlined cutouts are suitable
choices among the proposed patterns for 85-Ohm differential
traces with 0201-sized SMDs in series. A proper ground void
design can effectively achieve impedance matching, while the
patterns with round edge may also alleviate the current
crowding at sharp corners. Designs for matching to other
target routing impedance may be presented in future work.

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